JPS5263672A - Production of semiconductor device - Google Patents

Production of semiconductor device

Info

Publication number
JPS5263672A
JPS5263672A JP50139862A JP13986275A JPS5263672A JP S5263672 A JPS5263672 A JP S5263672A JP 50139862 A JP50139862 A JP 50139862A JP 13986275 A JP13986275 A JP 13986275A JP S5263672 A JPS5263672 A JP S5263672A
Authority
JP
Japan
Prior art keywords
semiconductor device
production
substrate
doublestructure
fear
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50139862A
Other languages
Japanese (ja)
Other versions
JPS5429341B2 (en
Inventor
Masaharu Noyori
Isamu Kitahiro
Hiroaki Fujimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP50139862A priority Critical patent/JPS5263672A/en
Publication of JPS5263672A publication Critical patent/JPS5263672A/en
Publication of JPS5429341B2 publication Critical patent/JPS5429341B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To obtain a semiconductor device of high reliability having no fear for disconnection by forming solder balls in the through-holes of a doublestructure substrate of a heat resistant insulating resin substrate and a resin film.
COPYRIGHT: (C)1977,JPO&Japio
JP50139862A 1975-11-20 1975-11-20 Production of semiconductor device Granted JPS5263672A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50139862A JPS5263672A (en) 1975-11-20 1975-11-20 Production of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50139862A JPS5263672A (en) 1975-11-20 1975-11-20 Production of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5263672A true JPS5263672A (en) 1977-05-26
JPS5429341B2 JPS5429341B2 (en) 1979-09-22

Family

ID=15255262

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50139862A Granted JPS5263672A (en) 1975-11-20 1975-11-20 Production of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5263672A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0307591A2 (en) * 1987-09-14 1989-03-22 Hitachi, Ltd. Method and apparatus for aligning solder balls
US6855623B2 (en) * 1999-02-24 2005-02-15 Micron Technology Inc. Recessed tape and method for forming a BGA assembly
JP2009514250A (en) * 2005-11-01 2009-04-02 アレグロ・マイクロシステムズ・インコーポレーテッド Flip chip on lead semiconductor package method and apparatus
EP3300105A1 (en) * 2016-09-26 2018-03-28 Infineon Technologies AG Semiconductor power module and method for manufacturing the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0307591A2 (en) * 1987-09-14 1989-03-22 Hitachi, Ltd. Method and apparatus for aligning solder balls
US6855623B2 (en) * 1999-02-24 2005-02-15 Micron Technology Inc. Recessed tape and method for forming a BGA assembly
JP2009514250A (en) * 2005-11-01 2009-04-02 アレグロ・マイクロシステムズ・インコーポレーテッド Flip chip on lead semiconductor package method and apparatus
JP2013219369A (en) * 2005-11-01 2013-10-24 Allegro Microsystems Llc Method and device for flip-chip-on-lead semiconductor package
EP3300105A1 (en) * 2016-09-26 2018-03-28 Infineon Technologies AG Semiconductor power module and method for manufacturing the same

Also Published As

Publication number Publication date
JPS5429341B2 (en) 1979-09-22

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