JPH1197529A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacture of a semiconductor device provided with a self-aligning contact capable of narrowing a width between gate electrodes, without forming the recess of a semiconductor substrate or lowering the conductive impurity density of a source/drain diffusion layer. SOLUTION: A first wiring A and an offset insulation film 22a on the upper layer are formed on the semiconductor substrate 10, and the etching stopper film 23 of silicon nitride is formed on the entire surface. Then, the side wall masking layer 24a of silicon oxide is formed oppositely to the side wall surface of the first wiring A and the offset insulation film 22a, ions are injected with the side wall masking layer 24a as a mask and the diffusion layer 12 of conductive impurities is formed in the semiconductor substrate 10. Then, a selection rate to the etching stopper film 23 is provided, the side wall masking layer 24a is removed, an insulation film is formed on the entire surface on the upper layer of the etching stopper film 23, and a contact hole reaching the diffusion layer 12 is opened on the insulation film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a junction by a self-aligned contact.

[0002]

2. Description of the Related Art In recent years, the integration of VLSIs has advanced to the next generation in three years, and the design rules have been reduced by 70% of those of the previous generation. This high integration has been achieved by advances in microfabrication technology in the manufacturing process of semiconductor devices, particularly by increasing the resolution of light exposure technology. The high resolution of the light exposure technology has been achieved by improving the performance of an exposure apparatus, a resist material, and a resist process while satisfying dimensional accuracy and overlay accuracy corresponding to design rules.

However, among the above exposure devices, it is difficult to reduce the variation in the alignment of the stepper, and the variation in the alignment is so large that the design margin of the alignment must be increased. As a result, it is difficult to reduce the cell size. Accordingly, there is a need for a technology that can reduce the design margin for alignment and reduce the cell size.

As one of them, a self-aligned contact (hereinafter referred to as SA) which can eliminate a design margin on a mask for alignment in a contact hole process.
(Abbreviated as C) technology is attracting attention.

There are several methods for forming the SAC. For example, when forming a SAC between a gate electrode of a MOS transistor and a silicon semiconductor substrate, an offset insulating film is formed on the gate electrode and a side surface is formed on a side wall surface. A wall insulating film is formed, and a thin silicon nitride etching stopper film is formed by covering the offset insulating film and the sidewall insulating film. Next, an interlayer insulating film is formed above the etching stopper film, and the contact is opened by etching. The etching at this time stops once when the etching stopper film is reached. By changing the etching conditions, the etching stopper film at the bottom of the contact is removed by etching, the silicon semiconductor substrate is exposed, and a plug electrode or the like is formed on the exposed surface to form a contact (SA).
C) is completed.

However, according to the above method, the side wall insulating film formed on the side wall surface of the gate electrode is SA
The opening area of C is reduced, and the contact area with the silicon semiconductor substrate in the SAC is reduced. For this reason, SAC
However, it is difficult to reduce the width between the gate electrodes when using GaN, and it is also difficult to reduce the cell size.

In order to solve the above problem, 0.35 μm
From generation to generation, it is possible to reduce the width between gate electrodes by forming sidewalls using easily removable polysilicon and removing the sidewalls before forming an interlayer insulating film that opens contacts. The method used has come to be used. Regarding the method of manufacturing a semiconductor device described above,
Typical SRAM (Static Random Access Memories)
An example will be described below with reference to the drawings.

First, as shown in FIG. 6A, an element isolation insulating film 20 is formed on a silicon semiconductor substrate 10 by, for example, a LOCOS method, and in an active region separated by the element isolation insulating film 20, for example, thermal oxidation is performed. A gate insulating film 21 is formed by a method. Next, an upper layer of the gate insulating film 21 is coated by, for example, a CVD method, and polysilicon and tungsten silicide are sequentially stacked on the entire surface to form a lower gate electrode layer 30 and an upper gate electrode layer 31. Next, for example, CV is formed on the upper gate electrode layer 31.
Silicon oxide is deposited by the method D to form the offset insulating film 22.

Next, as shown in FIG. 6B, a resist film R1 having a gate electrode and a first wiring pattern is formed on the offset insulating film 22 by a photolithography process, and RIE (reactive ion etching) is performed. The lower gate electrode layer 3 is subjected to anisotropic etching such as
0, the upper gate electrode layer 31 and the offset insulating film 22 are patterned to form a gate electrode A and a first wiring with a polycide-structured offset insulating film 22a in which polysilicon and tungsten silicide are laminated.

Next, as shown in FIG. 6C, after the resist film R1 is removed, a conductive impurity D1 is ion-implanted at a low concentration into the silicon semiconductor substrate 10 using the offset insulating film 22a as a mask, and LDD is performed. (Lightly Doped Drain
A) forming a diffusion layer (low concentration diffusion layer) 11; Next, silicon oxide is deposited on the entire surface by covering the offset insulating film 22a by, for example, a CVD method, and an etching stopper film 23 is formed.

Next, as shown in FIG. 7D, polysilicon is deposited on the entire surface of the etching stopper film 23 by, for example, a CVD method, and the sidewall mask layer 3 is formed.
7 is formed.

Next, as shown in FIG. 7E, the entire surface is etched back by etching such as RIE, leaving a sidewall mask 37a on the side wall surfaces of the gate electrode A and the first wiring. Next, using the sidewall mask 37a as a mask, the conductive impurity D2 is ion-implanted into the silicon semiconductor substrate 10 at a high concentration to form a source / drain diffusion layer (high concentration diffusion layer) 12.

In the subsequent steps, the sidewall mask layer 37a is removed by etching, an interlayer insulating film of, for example, silicon oxide is formed, and a contact hole reaching the source / drain diffusion layer (high concentration diffusion layer) 12 is opened. A desired semiconductor device is manufactured by forming an electrode or the like in the opening.

[0014]

However, when a contact hole is opened by using the above technique, the etching stopper film 23 is formed by etching back in each step of forming the side wall mask layer 37a by etch back and removing by etching. When the SAC is formed, since the offset insulating film 22a is formed above the gate electrode A and the first wiring when forming the SAC, the side wall mask is formed by the thickness of the offset insulating film 22a. Since the height of the layer 37a is high, the etching stopper 22a and the gate insulating film 21 recede in the etching in each step of forming the sidewall mask layer 37a by etching back the entire surface and removing the etching. When it has advanced, it is shown in FIG. As such, so that the source-drain diffusion layer in the semiconductor substrate 10 also (high concentration diffusion layer) to 12 would form an H dent in the semiconductor substrate 10 by etching.

The source / drain diffusion layer (high concentration diffusion layer) 12 is etched to form the semiconductor substrate 1.
As shown in FIG. 8, when the etching stopper film 23 'is formed to be a thick film for the purpose of preventing the formation of the dent H, the source / drain diffusion layer containing a conductive impurity at a high concentration (a high concentration At the time of ion implantation when forming the diffusion layer (12), it becomes difficult for ion species to penetrate the etching stopper film 23 '. In this case, the concentration of the conductive impurity in the source / drain diffusion layer (high concentration diffusion layer) 12 becomes low and does not become the intended high concentration. As a result, the driving capability of the MOS transistor decreases and the high concentration diffusion layer This will increase the sheet resistance of the diffusion layer wiring used.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and accordingly, an object of the present invention is to etch even a source / drain diffusion layer (high concentration diffusion layer) in a semiconductor substrate. Before forming an interlayer insulating film for opening a contact, a sidewall is removed without forming a dent or reducing a conductive impurity concentration of a source / drain diffusion layer (high concentration diffusion layer). It is an object of the present invention to provide a method of manufacturing a semiconductor device having a self-aligned contact that can reduce the width of the semiconductor device.

[0017]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a first wiring on a semiconductor substrate, and forming an offset insulating film on the first wiring. Forming, forming a silicon nitride etching stopper film over the entire surface by covering the offset insulating film, and forming a silicon oxide sidewall mask layer facing the first wiring and the sidewall surface of the offset insulating film. Forming, a step of performing ion implantation using the sidewall mask layer as a mask and forming a diffusion layer of a conductive impurity in the semiconductor substrate, and forming the sidewall mask with a selectivity to the etching stopper film. Removing a layer, forming an insulating film over the entire surface of the etching stopper film, and contacting the diffusion layer. And a step of opening the Lumpur in the insulating film.

The method for manufacturing a semiconductor device according to the present invention described above comprises:
A first wiring is formed on a semiconductor substrate, an offset insulating film is formed above the first wiring, and an etching stopper film of silicon nitride is formed on the entire surface by covering the offset insulating film.
Next, a sidewall mask layer of silicon oxide is formed so as to face the first wiring and the side wall surface of the offset insulating film. After forming a diffusion layer of a conductive impurity in the semiconductor substrate by performing ion implantation using the sidewall mask layer as a mask, the sidewall mask layer is removed with a selectivity to the etching stopper film, and an upper layer of the etching stopper film is formed. An insulating film is formed over the entire surface, and a contact hole reaching the diffusion layer is opened in the insulating film to form a contact in a self-aligned manner.

According to the method of manufacturing a semiconductor device of the present invention described above, an etching stopper film of silicon nitride is formed to cover the first wiring, and thereafter, the side surface of the silicon oxide is opposed to the side wall surface of the first wiring. By forming the wall mask layer, the sidewall mask layer can be removed in a later step with a selectivity to the etching stopper film. Thereby, when the sidewall is removed before forming the interlayer insulating film for opening the contact, even the source / drain diffusion layer (high concentration diffusion layer) in the semiconductor substrate is etched to form a dent in the semiconductor substrate. It is not necessary to increase the thickness of the etching stopper film in order to avoid the formation of a dent, so that the conductive impurity concentration of the source / drain diffusion layer (high concentration diffusion layer) is not reduced and the gate electrode A semiconductor device having a self-aligned contact capable of reducing the width of the semiconductor device can be manufactured.

The method for manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, the step of forming the side wall mask layer includes O ₃ and TEOS (tetraethylorthosilicate).
This is a step of forming by a CVD method containing as a raw material. Accordingly, since the etching rates of the wet etching and the dry etching are high, the formation into the sidewall shape by the etch back and the removal after the impurity introduction are facilitated.

The method of manufacturing a semiconductor device according to the present invention is as follows.
Preferably, the step of removing the sidewall mask layer is a step performed by wet etching. According to wet etching, compared to dry etching,
The uniformity of etching in the wafer surface can be improved, and the throughput of the manufacturing process can be improved.

The method of manufacturing a semiconductor device according to the present invention is as follows.
Preferably, the step of forming the sidewall mask layer includes a step of forming a sidewall mask layer over the entire surface of the etching stopper film, and a portion of the first wiring and the offset insulating film facing a side wall surface. And etching back the sidewall mask layer over the entire surface while leaving the sidewall mask layer. Thus, a sidewall mask layer of silicon oxide can be formed facing the side wall surfaces of the first wiring and the offset insulating film.

The method of manufacturing a semiconductor device of the present invention described above
Preferably, after the step of forming the offset insulating film,
Prior to the step of forming the sidewall mask layer, the method further includes a step of performing ion implantation using the first wiring as a mask to form a low-concentration diffusion layer of a conductive impurity in the semiconductor substrate; The step of performing ion implantation using the mask layer as a mask and forming a diffusion layer of a conductive impurity in the semiconductor substrate is a step of forming a diffusion layer containing a conductive impurity at a higher concentration than the low concentration diffusion layer. is there. Thereby, an LDD (Lightly Doped Drain) having a low concentration diffusion layer and a high concentration diffusion layer in a semiconductor substrate.
An impurity diffusion layer having a structure can be formed.

The method for manufacturing a semiconductor device of the present invention described above
Preferably, the method further includes a step of increasing the thickness of the etching stopper film after the step of removing the sidewall mask layer and before the step of forming an insulating film over the entire surface of the etching stopper film. Thereby, the stopping ability as an etching stopper at the time of opening a contact hole in a later step can be enhanced, and a self-aligned contact can be stably formed.

The method of manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, before the step of forming a first wiring on the semiconductor substrate, the method further includes a step of forming a channel formation region in the semiconductor substrate, and a step of forming a gate insulating film on the semiconductor substrate, The step of forming a first wiring on the semiconductor substrate is a step of forming a first wiring on the gate insulating film, and forming a field-effect transistor using the first wiring as a gate electrode. A field-effect MOS transistor can be formed from the gate insulating film in the upper layer of the channel formation region, the first wiring (gate electrode), and the source / drain diffusion layers connected to the channel formation region.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

A high resistance load type SRAM (Static) having a self-aligned contact manufactured by the manufacturing method of this embodiment
Random Access Memories Figure 1 shows a cross-sectional view of a semiconductor device.
Shown in For example, a gate insulating film 21 is formed in an active region (channel forming region) of the silicon semiconductor substrate 10 separated by an element isolation insulating film 20 formed by the LOCOS method, and is formed on an upper layer thereof and an upper layer of the element isolation insulating film 20. For example, a gate electrode (first wiring) A having a polycide structure including a lower gate electrode (lower first wiring) 30a of polysilicon and an upper gate electrode (upper first wiring) 31a of tungsten silicide is formed. An offset insulating film 22a of, for example, silicon oxide is formed on an upper layer of the gate electrode (first wiring) A, and an upper surface thereof is covered with an etching stopper film 25 of silicon nitride. LDD containing a conductive impurity at a low concentration is contained in the semiconductor substrate 10 on both sides of the gate electrode A.
A diffusion layer 11 and a high-concentration source / drain diffusion layer 12 are formed, and a gate insulating film 21, a first wiring (gate electrode) A, and a channel formation region above a channel formation region in the semiconductor substrate 10. Form a field-effect MOS transistor from the source / drain diffusion layers 11 and 12 connected to the MOS transistor.

A first interlayer insulating film 26 made of, for example, silicon oxide is formed on the gate electrode (first wiring) A covered by the offset insulating film 22a and the etching stopper film 25. A first contact hole CH1 reaching the diffusion layer 12 is opened. In the first contact hole CH1 and in the upper layer of the first interlayer insulating film 26, for example, the lower second wiring 32a of polysilicon and the upper second wiring 3 of tungsten silicide are formed.
A second wiring B having a polycide structure made of 3a is formed. A second layer of silicon oxide, for example,
An interlayer insulating film 27 is formed, and the second interlayer insulating film 2 is formed.
7, first interlayer insulating film 26, etching stopper film 25,
And a second contact hole CH2 penetrating through the gate insulating film 21 and reaching the source / drain diffusion layer 12. In the second contact hole CH2 and the second
Third wirings 34a and 34b including a high-resistance load element are formed on the interlayer insulating film 27. The high-resistance load element forming the flip-flop circuit of the SRAM semiconductor device and the high-concentration diffusion layer (storage node) are formed. The source / drain diffusion layers 12) are connected.

A third interlayer insulating film 28 made of, for example, silicon oxide is formed on the third wirings 34a and 34b, and the third interlayer insulating film 28 and the second interlayer insulating film 27 are formed.
Contact hole C that reaches through to the second wiring B
H3 is opened, and a plug 35 made of, for example, tungsten is buried in the third contact hole through an adhesion layer (not shown) such as titanium or titanium nitride. Is connected to a fourth wiring (bit line) 36. 4th
An overcoat layer 29 made of, for example, silicon nitride is formed on the entire surface so as to cover the wiring (bit line) 36.

In the SRAM semiconductor device having such a structure, the source / drain diffusion layer (high-concentration diffusion layer) in the semiconductor substrate is not etched to form a recess, and the source / drain diffusion layer (high-concentration diffusion layer) is not formed. ), The width between the gate electrodes (first wirings) can be reduced without deteriorating the transistor characteristics and increasing the sheet resistance of the diffusion layer wiring because the conductive impurity concentration is not lowered. Semiconductor device having a self-aligned contact as described above.

Hereinafter, a method of manufacturing the above-described SRAM semiconductor device will be described. First, as shown in FIG. 2A, an element isolation insulating film 20 is formed on a silicon semiconductor substrate 10 by, for example, the LOCOS method.
In the active region (channel formation region) separated by the above, the gate insulating film 21 is formed by, for example, a thermal oxidation method. Next, the upper layer of the gate insulating film 21 is coated by, for example, a CVD method, and polysilicon and tungsten silicide are sequentially stacked on the entire surface. (1 wiring) layer 31 is formed. Next, silicon oxide is deposited on the upper layer 31 for the upper gate electrode (upper first wiring) by, for example, the CVD method to form the offset insulating film 22.

Next, as shown in FIG. 2B, a resist film R1 having a gate electrode and a first wiring pattern is formed on the offset insulating film 22 by a photolithography process, and is subjected to RIE (reactive ion etching). The lower gate electrode (lower first wiring) layer 30, the upper gate electrode (upper first wiring) layer 31, and the offset insulating film 22 are patterned by anisotropic etching such as polysilicon. Then, a gate electrode (first wiring) A having an offset insulating film 22a having a polycide structure in which tungsten silicide is laminated is formed.

Next, as shown in FIG. 2C, after the resist film R1 is removed, silicon nitride is deposited to a thickness of, for example, 10 to 20 nm on the entire surface from the upper surface of the offset insulating film 22a by, for example, the CVD method. Then, an etching stopper film 23 is formed. Next, using the gate electrode (first wiring) A with the offset insulating film 22a as a mask, a conductive impurity D1 is ion-implanted at a low concentration into the silicon semiconductor substrate 10, and an LDD (Lightly Doped Drain) diffusion layer (low concentration diffusion) is formed. Layer 11 is formed.

Next, as shown in FIG. 3D, silicon oxide is deposited on the entire surface of the upper layer of the etching stopper film 23 by, for example, a CVD method, and the side wall mask layer 2 is formed.
4 is formed. Here, the side wall mask layer 24
In particular, O ₃ and TEOS (tetraethylorthos
(ilicate) as a raw material. Accordingly, since the etching rates of the wet etching and the dry etching are high, the formation into the sidewall shape by the etch back and the removal after the impurity introduction are facilitated.

Next, as shown in FIG. 3 (e), the conventional C ₄
It was etchant gas by adding CO to F _8, by etching such as RIE with 20 degree of selectivity with respect to the etching stopper film 23 of silicon nitride, the gate electrode side of the (first wiring) A and the offset insulating film 22a The entire surface is etched back except for the side wall mask 24a facing the wall surface. Next, the sidewall mask 24a
Is used as a mask to ion-implant conductive impurity D2 into silicon semiconductor substrate 10 at a high concentration to form source / drain diffusion layer (high concentration diffusion layer) 12. At this time, since the thickness of the etching stopper film 23 is relatively small, a sufficiently high impurity concentration (1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ ) can be obtained with normal ion implantation energy (30 to 60 keV). . By forming the source / drain diffusion layer (high concentration diffusion layer) 12, the source / drain of the LDD structure can be formed, and the gate insulating film 21 on the channel formation region in the semiconductor substrate 10 and the first wiring (gate electrode) A) and source / drain diffusion layer 1 connected to channel formation region
A field effect MOS transistor is formed from 1 and 12.

Next, as shown in FIG. 3F, the sidewall mask layer 24a is removed by wet etching. According to the wet etching, the etching uniformity in the wafer surface can be improved as compared with the dry etching, and the throughput of the manufacturing process can be improved. For example, according to normal hydrofluoric acid-based wet etching, the etching selectivity of silicon oxide to silicon nitride is about 20 times, and the etching time is set to a time enough to remove the sidewall mask layer. The film is not etched, so that the semiconductor substrate is not etched to form a recess in the semiconductor substrate. Also,
By dry etching which can have an etching selectivity of silicon oxide to silicon nitride of about 20,
The sidewall mask layer 24a can be removed.

Next, as shown in FIG.
Silicon nitride etching stopper film 23 by VD method
Silicon nitride is deposited on the upper layer to form an etching stopper film 25 having a thickness of about 100 nm. The portion of the silicon nitride etching stopper film 23 that has existed before the deposition of new silicon nitride becomes a part of the thick etching stopper film 25. By increasing the thickness of the etching stopper film 25, the stopping ability as an etching stopper at the time of opening a contact hole in a later process can be enhanced, and a self-aligned contact can be formed stably.

Next, as shown in FIG.
Silicon oxide is deposited on the entire surface by the VD method to form a first interlayer insulating film 26, and the surface of the first interlayer insulating film 26 is flattened by reflow, etchback, CMP (Chemical Mechanical Polishing) or the like.

Next, as shown in FIG. 4I, a resist film is patterned and formed by a photolithography process, and is subjected to etching such as RIE to form a first interlayer insulating film 26, an etching stopper film 25, and a gate insulating film. A first contact hole CH1 that penetrates through the film 21 and reaches the source / drain diffusion layer 12 is opened. First, an opening is made until the surface of the etching stopper film 25 is exposed under an etching condition that can set an etching selectivity of silicon oxide to silicon nitride to about 20, and then the etching condition is changed to open the etching stopper film 25. Through the gate insulating film 21.

Next, as shown in FIG.
The first contact hole CH1 and the first contact hole CH1 are formed by the VD method.
Polysilicon and tungsten silicide are sequentially stacked on the entire surface of the interlayer insulating film 26, and a resist film is patterned and formed by a photolithography process.
By performing anisotropic etching such as IE, the second lower interconnection 32a of polysilicon and the upper second interconnection 33a of tungsten silicide are stacked to form a second polycide structure.
The wiring B is formed.

Next, as shown in FIG. 5K, the second wiring B is covered, silicon oxide is deposited on the entire surface by, for example, a CVD method, and a second interlayer insulating film 27 is formed. A resist film is formed by patterning, and etching such as RIE is performed to form a second interlayer insulating film 27, a first interlayer insulating film 26, and an etching stopper film 2.
5 and a second contact hole CH2 penetrating through the gate insulating film 21 and reaching the source / drain diffusion layer 12. Similar to the opening of the first contact hole CH1,
Opening is performed until the surface of the etching stopper film 25 is exposed under an etching condition that allows the etching selectivity of silicon oxide to silicon nitride to be about 20; then, the etching condition is changed to open the etching stopper film 25; It penetrates to the insulating film 21.

Next, as shown in FIG. 5 (l), a wiring layer including a high resistance load element is formed in the second contact hole CH2 and in the upper layer of the second interlayer insulating film 27, and is patterned to form a third layer. The wirings 34a and 34b are formed. As a result, the high-resistance load element forming the flip-flop circuit of the SRAM semiconductor device is connected to the high-concentration diffusion layer (source / drain diffusion layer) 12, which is a storage node. Next, the third wirings 34a and 34b are covered, and silicon oxide is deposited on the entire surface by, for example, a CVD method.
Is formed, and a flattening process is performed by reflow or etch back.

Next, a third contact hole CH3 penetrating the third interlayer insulating film 28 and the second interlayer insulating film 27 and reaching the second wiring B is opened, and titanium and titanium nitride (not shown) are formed in the third contact hole. After forming an adhesion layer such as, for example, tungsten is deposited on the entire surface, and the entire surface is etched back to form a plug 35 made of tungsten. Next, an adhesion layer of titanium, titanium nitride, or the like is formed on the third interlayer insulating film 28, and a fourth wiring (bit line) 36 made of an aluminum-based alloy is connected to the plug 35 on the adhesion layer by, for example, a sputtering method. Formed. Next, an overcoat layer 2 made of, for example, silicon nitride is formed on the entire surface while covering the fourth wiring (bit line)
9 to form the SRAM semiconductor device shown in FIG.

According to the method of manufacturing a semiconductor device of the present embodiment, when removing the sidewall before forming the interlayer insulating film for opening the contact, the source / drain diffusion layer (highly doped layer) in the semiconductor substrate is removed. The source / drain diffusion layer (high-concentration diffusion layer) does not need to be etched to form the depression in the semiconductor substrate, and it is not necessary to increase the thickness of the etching stopper film to avoid the depression. It is possible to manufacture a semiconductor device having a self-aligned contact capable of reducing the width between gate electrodes without lowering the conductive impurity concentration. Further, in the prior art, an annealing step was required to densify the etching stopper film of silicon oxide formed under the sidewall mask layer of polysilicon, but according to the method of manufacturing a semiconductor device of the present invention, By using a silicon nitride film as an etching stopper film, the above-described annealing step can be reduced, which is effective in suppressing the short channel effect due to the enhanced diffusion of the MOS transistor.

The present invention is applicable to any semiconductor device having a contact hole formed in a self-aligned manner, such as a semiconductor device of a MOS transistor such as a DRAM, a bipolar semiconductor device, or an A / D converter, in addition to an SRAM. Anything can be applied. It is possible to provide a highly reliable contact bonding that does not cause formation of a dent in a substrate or increase in resistance of a diffusion layer in a substrate, in a semiconductor device in which device miniaturization and miniaturization have been advanced.

The present invention is not limited to the above embodiment. For example, the first wiring (gate electrode) and the second wiring have a polycide structure, but may have a single-layer structure or a structure having three or more layers. The upper wiring such as the third wiring may have a multilayer structure. The sidewall mask layer may also have a multilayer structure or more. In addition, various changes can be made without departing from the spirit of the present invention.

[0047]

According to the present invention, when a sidewall is removed before forming an interlayer insulating film for opening a contact, even a source / drain diffusion layer (high concentration diffusion layer) in a semiconductor substrate is etched. As a result, it is not necessary to increase the thickness of the etching stopper film in order to avoid the formation of a dent in the semiconductor substrate, thereby lowering the concentration of conductive impurities in the source / drain diffusion layer (high concentration diffusion layer). , And a semiconductor device having a self-aligned contact that can reduce the width between gate electrodes can be manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIGS. 2A and 2B are cross-sectional views illustrating a manufacturing process of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. And (c) show the steps up to the step of forming a low concentration diffusion layer by ion implantation.

FIG. 3 shows a step subsequent to that of FIG. 2; (d) shows up to a step of forming a sidewall mask layer; (e) shows up to a step of forming a high concentration diffusion layer by ion implantation; The steps up to the step of removing the sidewall mask layer are shown.

FIG. 4 shows a step subsequent to that of FIG. 3; (g) shows up to a step of increasing the thickness of an etching stopper film; (h) shows up to a step of forming a first interlayer insulating film; The process up to the contact hole opening step is shown.

FIG. 5 shows a step that follows the step shown in FIG. 4;
(K) shows up to the step of opening the second contact hole, and (l) shows the step up to the step of forming the third interlayer insulating film.

FIGS. 6A and 6B are cross-sectional views illustrating a manufacturing process of a conventional method of manufacturing a semiconductor device, in which FIG. 6A is a diagram up to a step of forming an offset insulating film, and FIG. Up to the processing step, (c) shows up to the step of forming a low concentration diffusion layer by ion implantation.

FIG. 7 shows a step subsequent to that of FIG. 6; (d) shows up to a step of forming a layer for a sidewall mask; (e) shows up to a step of forming a high concentration diffusion layer by ion implantation; The steps up to the step of removing the sidewall mask layer are shown.

FIG. 8 shows a step that follows the step of FIG. 7D, and shows a case where the etching stopper film is formed to be thick.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 11 ... Low-concentration diffusion layer, 12 ... High-concentration diffusion layer, 20 ... Element isolation insulating film, 21 ... Gate mask layer, 22, 22a ... Offset insulating film, 23, 25 ... Etching stopper film, 24 ... Sidewall mask layer, 24a Sidewall mask layer, 26 First interlayer insulating film, 27 Second interlayer insulating film, 28 Third interlayer insulating film, 29 Overcoat layer, 30 and 30a Lower gate Electrodes (lower first wiring), 31, 31a... Upper gate electrode (upper first wiring), 32, 32a... Lower second wiring, 3
3, 33a: upper second wiring, 34a, 34b: third wiring, 35: plug, 36: fourth wiring (bit line), A:
Gate electrode (first wiring), B: second wiring, CH1: first
Contact hole, CH2 ... second contact hole, C
H3: third contact hole, D1, D2: conductive impurities, R1: resist film, H: dent.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/336

Claims (7)

[Claims] A step of forming a first wiring on a semiconductor substrate; a step of forming an offset insulating film on an upper layer of the first wiring; and a step of covering the offset insulating film with a silicon nitride etching stopper film over the entire surface. Forming a sidewall mask layer of silicon oxide facing the side wall surface of the first wiring and the offset insulating film; performing ion implantation using the sidewall mask layer as a mask; Forming a diffusion layer of conductive impurities on the substrate, removing the sidewall mask layer with a selectivity to the etching stopper film, and forming an insulating film over the entire surface of the etching stopper film. And a step of opening a contact hole reaching the diffusion layer in the insulating film. 2. The method according to claim 1, wherein the step of forming the side wall mask layer comprises forming O ₃ and TEOS (tetraethylorthosilicate).
2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming is performed by a CVD method containing (1) as a material. 3. The method according to claim 1, wherein the step of removing the sidewall mask layer is a step of performing wet etching. 4. The step of forming the sidewall mask layer includes the step of forming a sidewall mask layer over the entire surface of the etching stopper film, and facing a sidewall surface of the first wiring and the offset insulating film. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of etching back the sidewall mask layer over the entire surface while leaving a portion of the sidewall mask layer. 5. After the step of forming the offset insulating film and before the step of forming the sidewall mask layer, ion implantation is performed using the first wiring as a mask, and conductive impurities of the semiconductor substrate are introduced into the semiconductor substrate. Forming a low-concentration diffusion layer, wherein the step of performing ion implantation using the sidewall mask layer as a mask and forming a diffusion layer of a conductive impurity in the semiconductor substrate is performed more than the low-concentration diffusion layer; 2. The step of forming a diffusion layer containing a conductive impurity at a high concentration.
The manufacturing method of the semiconductor device described in the above. 6. The method according to claim 6, further comprising: after the step of removing the sidewall mask layer, before the step of forming an insulating film over the entire surface of the etching stopper film, the step of thickening the etching stopper film. A method for manufacturing a semiconductor device according to claim 1. 7. The method according to claim 1, further comprising: before forming the first wiring on the semiconductor substrate, forming a channel formation region on the semiconductor substrate, and forming a gate insulating film on the semiconductor substrate. The step of forming a first wiring on the semiconductor substrate is a step of forming a first wiring on the gate insulating film, and forming a field-effect transistor using the first wiring as a gate electrode. A method for manufacturing a semiconductor device.