JPH1194916A - Semiconductor integrated circuit, its design method, and recording medium with its design program recorded - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for which a clock signal- generating circuit, etc., provided in the integrated circuit can be tested easily. SOLUTION: A select signal output circuit 10 is provided in a semiconductor integrated circuit. When '0' is inputted to the D-terminal of the circuit 10, the circuit 10 switches a selector 12 to a partial circuit 2 side and a scan FF(flip flop) 11 inputs the output of the partial circuit 2. At the time of conducting scan tests, a select signal of '0' or '1' value is inputted to the select signal output circuit 10 from a scan-in terminal 3 and further inputted to the selector 12. The selector 12 selects the partial circuit 2 side when the select signal is '0' or the clock signal of a clock signal generating circuit 9 when the select signal is '1'. The output of the partial circuit 2 or the clock signal of the clock signal generating circuit 9 inputted to the scan FF 11 is outputted to the outside from a scan-out terminal 8 through a scan path 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a semiconductor integrated circuit, and more particularly, to a method of performing a failure test of an internal circuit using a scan test, a method of designing the improved semiconductor integrated circuit, and recording a design program thereof. Related to a recorded medium.

[0002]

2. Description of the Related Art Generally, among logic circuits constituting a semiconductor integrated circuit, a logic circuit for generating a clock signal, a reset signal, a set signal, or the like is tested by a scan path method. It is difficult.

That is, in a conventional semiconductor integrated circuit, for example, a clock signal of a logic circuit (clock signal generation circuit) for generating a clock signal is selected by a selector during a normal operation, and a storage element such as a predetermined flip-flop is used. However, in the scan mode, a clock signal for scanning input from the outside is selected by the selector in place of the clock signal of the clock signal generation circuit and input to the storage element. Therefore,
In such a method, the clock signal of the clock signal generation circuit is valid during the normal operation, but becomes invalid in the scan mode, so that it is impossible to perform a test of such a clock signal generation circuit. .

Therefore, conventionally, for example, JP-A-61-23
As disclosed in Japanese Patent No. 4376, in order to test a circuit for generating a clock signal or the like, there is known a configuration in which means for observing a signal from the generator circuit is provided to test the circuit for generating a clock signal or the like. I have. Specifically, in this configuration, a selector is provided between an output side of a generation circuit for a clock signal or the like and a storage element using the clock signal, and a clock signal of the generation circuit for a clock signal or the like is provided during a normal operation. In the select and scan test mode, an external test clock signal is selected and supplied to the storage element to implement a scan test operation. Further, an external output terminal for observation is provided, and a signal line connecting the circuit for generating the clock signal or the like and the selector is branched, and the branched signal line is connected to the external output terminal for observation, whereby ,
By observing the clock signal of the clock signal generation circuit at the external output terminal, it is possible to test the clock signal generation circuit.

[0005]

However, the conventional configuration requires an external output terminal for testing the circuit for generating the clock signal and the like in addition to the external terminal for scan test. Therefore, the number of terminals of the semiconductor integrated circuit increases. In particular, when there are a large number of clock signal generation circuits, a large number of external test output terminals are required, which may be difficult to realize in recent semiconductor integrated circuits in which the number of terminals is severely restricted. Further, the conventional configuration requires a signal line connecting the clock signal generation circuit and the test external output terminal, which leads to an increase in circuit size. In particular, when there are a large number of clock signal generation circuits, the number of the signal lines increases in proportion to the increase in the number, which causes a disadvantage that the circuit scale is further increased.

In order to solve the above-mentioned drawback, a technique disclosed in, for example, Japanese Patent Application Laid-Open No. Sho 62-169066 has been proposed in which a logic circuit is connected to a storage element such as a flip-flop for storing its output. A selector is disposed, and the selector adopts a configuration in which a clock signal of a clock signal generation circuit is input to the storage element. In a scan mode, the selector outputs the output of the logic circuit and the clock signal generation circuit. By selectively switching between the clock signal and the clock signal and observing the output of the logic circuit or the clock signal of the clock signal generation circuit at the scan-out terminal, the external observation of the output signal of the clock signal generation circuit is performed. The clock signal generation circuit can be tested while eliminating the need for external output terminals and signal lines leading to this output terminal. It has to.

However, in the prior art, there is no disclosure of a specific control circuit (selection signal output circuit) for controlling the selector, and it is possible to appropriately control switching of the selector between normal operation and scan mode. Can not.

[0008] In view of the above, the present invention has the following object.
A selection signal output circuit for controlling the selector (selection circuit), whereby an external output terminal for external observation of an output signal of a clock signal generation circuit or the like while appropriately controlling the selector; It is an object of the present invention to make it possible to easily test a clock signal generation circuit or the like by eliminating the need for a signal line leading to the circuit.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising a storage element having a data input terminal and a control terminal and forming a part of a scan path. A first partial circuit for generating data to be supplied to a data input terminal of the storage element during a normal operation;
A second partial circuit for generating a signal to be supplied to a control terminal of the storage element during a normal operation, wherein the output signal of the first partial circuit and the output signal of the second partial circuit are A selection circuit that selects one of them and supplies the selected signal to a data input terminal of the storage element; and a selection signal output circuit that outputs a selection signal instructing a selection operation of the selection circuit to the selection circuit. The selection signal output circuit is configured such that the selection circuit selects the output signal of the first partial circuit during the normal operation, while the selection circuit selects the output signal of the first partial circuit and the output signal of the first partial circuit during a test of the semiconductor integrated circuit. A selection signal is output so as to arbitrarily select one of the output signals of the second partial circuit.

According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the control terminal is a clock signal input terminal, and the second partial circuit is a clock signal generation circuit for generating a clock signal. It is characterized by being.

According to a third aspect of the present invention, there is provided the semiconductor integrated circuit according to the second aspect, further comprising another selection circuit, wherein the other selection circuit outputs the output of the second partial circuit during a normal operation. While selecting a signal, a clock signal provided from a source other than the second partial circuit is selected during a test of the semiconductor integrated circuit, and the selected signal is input to a control terminal of the storage element.

According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit comprising:
A first terminal having a control terminal and forming a part of a scan path;
A second storage element having a data input terminal and constituting a part of the scan path, and a first storage element for generating data to be supplied to the data input terminal of the second storage element during a normal operation. In a semiconductor integrated circuit including a partial circuit and a second partial circuit that generates a signal to be supplied to a control terminal of the first storage element during a normal operation, an output signal of the first partial circuit and a second A selection circuit that selects one of the output signals of the partial circuits and supplies the selected signal to a data input terminal of the second storage element; and a selection signal that instructs a selection operation of the selection circuit. A selection signal output circuit for outputting to the circuit, the selection signal output circuit selects the output signal of the first partial circuit during the normal operation, and selects the output signal of the first partial circuit during a test of the semiconductor integrated circuit. As the circuit is arbitrarily selected one of the output signal of the output signal and the second partial circuit of the first partial circuit, and outputs a selection signal.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit according to the fourth aspect, the control terminal is a clock signal input terminal, and the second partial circuit is a clock signal generation circuit for generating a clock signal. It is characterized by being.

According to a sixth aspect of the present invention, in the semiconductor integrated circuit of the fifth aspect, another selecting circuit is provided separately, and the other selecting circuit outputs the output of the second partial circuit during a normal operation. While selecting a signal, a clock signal provided from a source other than the second partial circuit is selected during a test of the semiconductor integrated circuit, and the selected signal is input to a control terminal of the first storage element. .

According to a seventh aspect of the present invention, in the semiconductor integrated circuit according to the first or fourth aspect, the control terminal is a reset signal input terminal, and the second partial circuit is configured to generate a reset signal. It is a generation circuit.

The invention according to claim 8 is the semiconductor integrated circuit according to claim 1 or 4, wherein the control terminal is a set signal input terminal, and the second partial circuit is a set signal for generating a set signal. It is a generation circuit.

According to a ninth aspect of the present invention, in the semiconductor integrated circuit according to the first or fourth aspect, the selection signal output circuit has another storage element forming the scan path,
The other storage element receives the selection signal from the outside via the scan path, and outputs the received selection signal to the selection circuit.

According to a tenth aspect of the present invention, in the semiconductor integrated circuit according to the ninth aspect, the another storage element always receives a selection signal for causing the selection circuit to select an output signal of the first partial circuit. A data input terminal, a scan data input terminal to which a selection signal is input from the outside via the scan path, and an output terminal to output a selection signal to the selection circuit, and a scan enable input from the outside When the scan enable signal is not inputted, the selection signal of the data input terminal is outputted from the output terminal. When the scan enable signal is inputted, the selection signal inputted to the scan data input terminal is outputted. The signal is output from the output terminal.

According to a eleventh aspect of the present invention, in the method for designing a semiconductor integrated circuit capable of inspecting the operation of an internal circuit, the storage element having a data input terminal and a control terminal, and the storage element Inputting a netlist of a semiconductor integrated circuit comprising: a first partial circuit for generating data to be supplied to a data input terminal of the storage device; and a second partial circuit for generating a signal to be supplied to a control terminal of the storage element. A selection circuit that selects one of an output signal of the first partial circuit and an output signal of the second partial circuit and supplies the selected signal to a data input terminal of the storage element; Adding, to the semiconductor integrated circuit, a selection signal output circuit that outputs a selection signal instructing the selection operation to the selection circuit; and scanning the storage element. Together constitute the flop, characterized by comprising the step of inserting the scan path including the scan flip-flops in the semiconductor integrated circuit.

The invention according to claim 12 is the invention according to claim 11.
In the semiconductor integrated circuit design method described above, the control terminal is a clock signal input terminal, and the second partial circuit is a clock signal generation circuit that generates a clock signal.

According to a thirteenth aspect of the present invention, there is provided the method of the twelfth aspect.
In the method for designing a semiconductor integrated circuit described in the above, one of an output signal of the second partial circuit and a clock signal supplied from a source other than the second partial circuit is selected, and the selected signal is stored in the storage element. And a step of adding another selection circuit to the control terminal of the semiconductor integrated circuit to the semiconductor integrated circuit.

According to a fourteenth aspect of the present invention, in the method for designing a semiconductor integrated circuit capable of inspecting the operation of an internal circuit, the first memory element having a control terminal and the data input terminal are connected to each other. A second storage element having
A semiconductor integrated circuit, comprising: a first partial circuit for generating data to be supplied to a data input terminal of the second storage element; and a second partial circuit for generating a signal to be supplied to a control terminal of the first storage element. Entering a netlist of
A selection circuit that selects one of an output signal of the first partial circuit and an output signal of the second partial circuit and supplies the selected signal to a data input terminal of the second storage element; Adding, to the semiconductor integrated circuit, a selection signal output circuit that outputs a selection signal instructing a selection operation of the selection circuit to the selection circuit;
And a step of inserting a scan path including these scan flip-flops into the semiconductor integrated circuit.

According to a fifteenth aspect of the present invention, the fourteenth aspect is provided.
In the semiconductor integrated circuit design method described above, the control terminal is a clock signal input terminal, and the second partial circuit is a clock signal generation circuit that generates a clock signal.

The invention according to claim 16 is the invention according to claim 15.
In the method for designing a semiconductor integrated circuit described in the above, one of an output signal of the second partial circuit and a clock signal supplied from a source other than the second partial circuit is selected, and the selected signal is transmitted to the first partial circuit. And adding another selection circuit to be provided to the control terminal of the storage element to the semiconductor integrated circuit.

According to a seventeenth aspect, in the eleventh aspect,
15. The method for designing a semiconductor integrated circuit according to item 14, wherein the control terminal is a reset signal input terminal, and the second partial circuit is a reset signal generation circuit that generates a reset signal.

The invention according to claim 18 is the invention according to claim 11.
15. The method for designing a semiconductor integrated circuit according to item 14, wherein the control terminal is a set signal input terminal, and the second partial circuit is a set signal generation circuit that generates a set signal.

[0027] The invention according to claim 19 is the invention according to claim 11.
Or in the method for designing a semiconductor integrated circuit according to 14, wherein the step of inserting a scan path into the semiconductor integrated circuit includes:
The selection signal output circuit is constituted by a scan flip-flop, and the scan flip-flop is inserted into the scan path.

According to a twentieth aspect of the present invention, a recording medium recording a semiconductor integrated circuit design program is a recording medium recording a design program for designing a semiconductor integrated circuit capable of inspecting the operation of an internal circuit by a computer. The design program includes a storage element having a data input terminal and a control terminal, a first partial circuit for generating data to be supplied to a data input terminal of the storage element, and a signal to be supplied to a control terminal of the storage element. Inputting a netlist of a semiconductor integrated circuit having a second partial circuit; selecting one of an output signal of the first partial circuit and an output signal of the second partial circuit; A selection circuit for supplying a selected signal to a data input terminal of the storage element, and a selection signal for instructing a selection operation of the selection circuit to the selection circuit. Adding a selection signal output circuit to the semiconductor integrated circuit, and configuring the storage element by a scan flip-flop and inserting a scan path including the scan flip-flop into the semiconductor integrated circuit. It is characterized by including.

The invention according to claim 21 is the invention according to claim 20.
In a recording medium on which a design program for a semiconductor integrated circuit described above is recorded, the control terminal is a clock signal input terminal, and the second partial circuit is a clock signal generation circuit that generates a clock signal. .

The invention according to claim 22 is the invention according to claim 21.
In a recording medium on which a design program for a semiconductor integrated circuit according to the present invention is recorded, one of an output signal of the second partial circuit and a clock signal given from a source other than the second partial circuit is selected and selected. A step of adding another selection circuit for providing a signal to the control terminal of the storage element to the semiconductor integrated circuit.

According to a twenty-third aspect of the present invention, a recording medium recording a semiconductor integrated circuit design program is a recording medium recording a design program for designing a semiconductor integrated circuit capable of inspecting the operation of an internal circuit by a computer. The design program includes a first storage element having a control terminal, a second storage element having a data input terminal, and a first partial circuit for generating data to be supplied to a data input terminal of the second storage element. Inputting a netlist of a semiconductor integrated circuit including: a second partial circuit that generates a signal to be supplied to a control terminal of the first storage element; and an output signal of the first partial circuit and the second A selection circuit for selecting one of the output signals of the second partial circuit and supplying the selected signal to a data input terminal of the second storage element; Adding a selection signal output circuit that outputs a selection signal instructing a selection operation to the selection circuit to the semiconductor integrated circuit; and configuring the first and second storage elements with scan flip-flops, respectively. Inserting a scan path including these scan flip-flops into the semiconductor integrated circuit.

The invention according to claim 24 is the invention according to claim 23.
In a recording medium on which a design program for a semiconductor integrated circuit described above is recorded, the control terminal is a clock signal input terminal, and the second partial circuit is a clock signal generation circuit that generates a clock signal. .

The invention according to claim 25 is the invention according to claim 24.
In a recording medium on which a design program for a semiconductor integrated circuit according to the present invention is recorded, one of an output signal of the second partial circuit and a clock signal given from a source other than the second partial circuit is selected and selected. A step of adding another selection circuit for providing a signal to the control terminal of the first storage element to the semiconductor integrated circuit.

According to the twenty-sixth aspect of the present invention, the twentieth aspect is provided.
24. The recording medium according to claim 23, wherein the control terminal is a reset signal input terminal, and the second partial circuit is a reset signal generation circuit that generates a reset signal. And

According to a twenty-seventh aspect of the present invention, there is provided the twentieth aspect.
24. The recording medium according to claim 23, wherein the control terminal is a set signal input terminal, and the second partial circuit is a set signal generation circuit that generates a set signal. And

According to the twenty-eighth aspect of the present invention, the twenty-second aspect is provided.
Or a recording medium recording a design program for a semiconductor integrated circuit according to 23, wherein in the design program,
In the step of inserting the scan path into the semiconductor integrated circuit, the selection signal output circuit is configured by a scan flip-flop, and the scan flip-flop is inserted into the scan path.

With the above configuration, in the semiconductor integrated circuit according to the first to tenth aspects of the present invention, the selection operation of the selection circuit can be easily switched by the selection signal output circuit at the time of the test, so that the memory constituting the scan path is stored. Any one of the output of the first partial circuit constituting the combinational circuit and the output of the second partial circuit such as a clock signal or reset signal generation circuit is arbitrarily input to the data input terminal of the element. As a result, the output of the second partial circuit can be externally output by a scanning operation and observed.

Here, since the output of the second partial circuit can be externally output by a scanning operation and can be observed, an external output terminal dedicated to a test for observing an output signal of a clock signal generation circuit or the like as in the prior art is provided. This is unnecessary, and an increase in the number of terminals can be prevented. Further, since it is not necessary to provide a signal line for connecting an arbitrary partial circuit such as a clock signal generation circuit to the test-dedicated external output terminal, an increase in circuit scale can be prevented. In addition, since the selection operation of the selection circuit can be easily switched by the selection signal output circuit,
Testing can be performed easily.

In particular, in the semiconductor integrated circuit according to the ninth and tenth aspects, at the time of a test, when one of the output of the first partial circuit and the output of the second partial circuit such as a clock signal generation circuit is selected. Since the selection signal is input to the selection circuit via the scan path, either one of the two signals can be easily selected, and the test can be performed more easily.

In the method for designing a semiconductor integrated circuit according to claims 11 to 19 and the recording medium on which the program for designing a semiconductor integrated circuit according to claims 20 to 28 is recorded, the semiconductor integrated circuit which can achieve the above-described operation can be simply implemented. Can be designed.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1 shows a semiconductor integrated circuit according to a first embodiment of the present invention.

In the figure, 1 is a semiconductor integrated circuit, 3 is a scan-in terminal (scan data input terminal), 4 is a system reset signal input terminal, 5 is a system clock signal input during normal operation, and a scan clock is input during a test. A clock signal input terminal for inputting a signal, 6 is a scan enable signal input terminal, 7 is a test mode signal input terminal, and 8 is a scan out terminal.

In the semiconductor integrated circuit 1, 2
Is a partial circuit (first partial circuit) composed of a combinational circuit that generates data by performing operations such as arithmetic operations during normal operation, and 9 is a clock signal generation circuit (second partial circuit) that generates a clock signal during normal operation , 11 are scan flip-flops (storage elements), 12 is a selector (selection circuit), 13
Is also a selector (another selection circuit).

In the scan flip-flop 11, SI is a scan data input terminal, SE is a scan enable input terminal, D is a normal data input terminal, and Q is a data output terminal (output terminal) connected to the scan out terminal 8. When the input value of the SE terminal is “0”,
When the data at the terminal is fetched, the data at the SI terminal is fetched when the input value at the SE terminal is "1", and the fetched data is output from the data output terminal Q in synchronization with the clock signal. In the scan flip-flop 11, a symbol> indicates a clock signal input terminal (control terminal).

The selector 12 has a selection signal input terminal 1
2a, the output of the partial circuit 2 is selected when the selection signal input to the input terminal 12a is "0", and the clock signal of the clock signal generation circuit 9 is selected when the selection signal is "1". Select The selector 12 uses the selected signal as data as the scan flip-flop 11
To the D terminal.

The other selector 13 has a selection signal input terminal 13a connected to the test mode signal input terminal 7. When the test mode signal of the test mode signal input terminal 7 is "0", the clock signal is output. The clock signal of the generation circuit 9 is selected, and when the test mode signal is “1”, a clock signal (a clock signal other than the clock signal generation circuit 9) externally input to the clock signal input terminal 5 is selected.

Further, reference numeral 10 denotes a selection signal output circuit. The selection signal output circuit 10 outputs a selection signal to the selector 12 to control the selection operation of the selector 12, and includes a scan flip-flop (another storage element).
Consisting of This scan flip-flop has an SI terminal, an SE terminal, a D terminal, a Q terminal, a clock signal input terminal and a reset input terminal (R terminal), like the scan flip-flop 11. Functions the same as 11. The scan-in terminal 3 is connected to the SI terminal of the scan flip-flop 10, the Q terminal is connected to the SI terminal of the scan flip-flop 11, and a select signal output circuit (scan flip-flop A) a scan path 20 extending to the scan-out terminal 8 via the scan flip-flop 11;

In the scan flip-flop constituting the selection signal output circuit 10, the D terminal is always grounded, the R terminal is connected to the system reset signal input terminal 4, and the Q terminal is the selection signal input terminal of the selector 12. 12a. A scan enable signal input from the outside to the scan enable signal input terminal 6 is input to the SE terminal. Therefore, when the reset signal input to the R terminal is a “0” value, or when the scan enable signal at the SE terminal is a “0” value (in other words,
Is not input) and a clock signal is input, the selector 12 uses the signal “0” of the D terminal as a selection signal.
And the selector 12 is operated to select the output of the partial circuit 2 at all times. On the other hand, when the scan enable signal of the SE terminal is “1” and a clock signal is input, and if a selection signal is input from the outside to the scan-in terminal 3, the selection signal is transmitted via the scan path 20 to the SI. Terminal, and this input selection signal is
The signal is output from the terminal to the selector 12, and the selector 12 is controlled according to the “0” value or “1” value of the selection signal to select the output of the partial circuit 2 or the clock signal of the clock signal generation circuit 9.

Hereinafter, the operation of the semiconductor integrated circuit of this embodiment will be described with reference to FIG.

First, during normal operation, the signal values of the scan enable signal input terminal 6 and the test mode signal input terminal 7 are fixed to "0". Therefore, the scan flip-flops (selection signal output circuits) 10 and 11 take in the signal input to the D terminal and operate as a normal flip-flop, and the selector 13 selects the clock signal from the clock signal generation circuit 9. . Since the scan flip-flop 10 has the D terminal connected to the ground, a reset signal (= 0) is input from the system reset signal input terminal 4 or a system clock signal is input from the clock signal input terminal 5. Then, the value of the Q terminal of the scan flip-flop 10 becomes “0” value,
Thereafter, during normal operation, the value always remains at "0". Therefore, the selector 12 always selects the signal from the partial circuit 2.

At the time of a test, the test mode signal at the test mode signal input terminal 7 is fixed at “1”, and a scan clock signal is input from the clock signal input terminal 5. As a result, the selector 13 selects a signal from the clock signal input terminal 5 and outputs the signal to the scan flip-flop 11.
Scan operation becomes possible. The scan-in terminal 3 → the scan flip-flop 10 → the scan flip-flop 11 → the scan-out terminal 8 forms a scan path 20. When the scan enable signal of the scan enable signal input terminal 6 is set to “1”, the scan flip-flop 10 Numeral 11 operates as a shift register and can perform scan-in / scan-out operations.

When a signal from the partial circuit 2 is tested, a selection signal of "0" value is input from the scan-in terminal 3 to the scan flip-flop 10 via the scan path 20 by a scan-in operation. set.
As a result, the selector 12 selects a signal from the partial circuit 2. Next, the scan enable signal of the scan enable signal input terminal 6 is set to “0” value, and the signal from the partial circuit 2 selected by the selector 12 is taken in from the D terminal of the scan flip-flop 11. Subsequently, the scan enable signal of the scan enable signal input terminal 6 is set to “1” value, and the signal of the partial circuit 2 taken into the scan flip-flop 11 is transmitted from the scan out terminal 8 via the scan path 20 by the scan out operation. Output to external. Therefore, the output signal of the partial circuit 2 can be observed at the scan-out terminal 8 during the test.

To test the clock signal generation circuit 9, a selection signal of "1" value is input from the scan-in terminal 3 to the scan flip-flop 10 and set. Thus, the selector 12 selects the clock signal of the clock signal generation circuit 9. Hereinafter, in the same manner as described above, the clock signal of the clock signal generation circuit 9 is fetched from the D terminal of the scan flip-flop 11 and is externally output from the scan-out terminal 8 by the scan-out operation. Therefore, at the time of the test, the clock signal of the clock signal generation circuit 9 can be observed at the scan-out terminal 8, so that the clock signal can be observed by the scan operation without adding a dedicated observation terminal.

Next, a method of designing the semiconductor integrated circuit shown in FIG. 1 by a computer will be described with reference to the flowchart of FIG. This flowchart is actually configured by a computer-readable program, and is stored in a storage medium such as a floppy disk or a CD-ROM.

In FIG. 2, in step S1, the netlist of the semiconductor integrated circuit shown in FIG. 3 to be tested is input. As shown in FIG. 3, the semiconductor integrated circuit to be tested basically includes a partial circuit 2, a clock signal generation circuit 9, a flip-flop 22 corresponding to the scan flip-flop, a system reset input terminal 4, and a clock signal input. The terminal 5 is provided.

Next, in step S2, as shown in FIG. 4, a flip-flop 23 corresponding to the selection signal output circuit 10 is inserted, and
3, the data input terminal D, the reset terminal R, and the clock terminal are connected to the ground, the system reset signal input terminal 4, and the clock signal input terminal 5, respectively.

Subsequently, in step S3, the clock signal generation circuit 9 searches for a flip-flop (memory element) to which the clock signal is supplied. In the semiconductor integrated circuit of FIG. 3, the flip-flop 22 is searched. Next step S
In 4, a two-input type selector 12 is arranged on the data input terminal D side of the searched flip-flop 22, and the output terminal of the selector 12 is connected to the data input terminal D of the flip-flop 22. Further, this selector 12
The output terminal Q of the flip-flop 23 corresponding to the selection signal output circuit 10 is connected to the select terminal 12a, and the two input terminals of the selector are respectively connected to the signal during normal operation from the partial circuit 2 , And the clock signal of the clock signal generation circuit 9. In the selector 12, when the value of the signal input to the select terminal 12a is "0", the signal of the partial circuit 2 is selected, and when the value of the signal input to the select terminal 12a is "1", the clock is selected. The clock signal of the signal generation circuit 9 is selected.

Further, in step S5, a two-input selector 13 is arranged on the clock terminal side of all the searched flip-flops (one flip-flop 22 in this embodiment), and the output of the selector 13 is output. The terminal is connected to the clock terminal of the flip-flop 22. Further, a test mode signal input terminal 7 is provided, and the test mode signal input terminal 7 is connected to the select terminal 13a of the selector 13. Further, a clock signal generation circuit 9 and a clock signal input terminal 5 are connected to two data input terminals of the selector 13, respectively. When the value of the signal input to the select terminal 13a is "0", the selector 13 selects the clock signal of the clock signal generation circuit 9, and the value of the signal input to the select terminal 13a is "1". In this case, the clock signal of the clock signal input terminal 5 is selected. At this point, the configuration shown in FIG. 4 is designed.

Finally, in step S6, a scan path is inserted into the semiconductor integrated circuit shown in FIG. In particular,
As shown in FIG. 1, the two flip-flops 22 and 23 are replaced with scan flip-flops 11 and 10, and a scan path is formed including both flip-flops 11 and 10. More specifically, a scan-in terminal 3, a scan enable signal input terminal 6, and a scan-out terminal 8 are added, and the scan enable terminals SE of the scan flip-flops 11, 10 are connected to the scan enable signal input terminal 6. Along with
The scan-in terminal 3 is connected to the scan-in terminal SI of the scan flip-flop (selection signal output circuit) 10.
The output terminal Q of the scan flip-flop 10 is connected to the scan-in terminal SI of the scan flip-flop 11.
And the output terminal Q of the scan flip-flop 11 is connected to the scan-out terminal 8. As a result, the semiconductor integrated circuit of FIG. 1 is completed.

(Second Embodiment) FIG. 5 shows a second embodiment of the present invention.
1 shows a semiconductor integrated circuit according to an embodiment. In the first embodiment, the clock signal generation circuit 9 is connected to both the D terminal and the clock signal terminal of the scan flip-flop 11.
When the static timing analysis device statically analyzes the timing using the static timing analysis device, the static flip-flop 1
1 may report a setup error or a hold error. The present embodiment solves this.

In FIG. 5, a clock signal externally input from a clock signal input terminal (control terminal) 5 is supplied to a scan flip-flop (second storage element) 14 to a clock signal input terminal (control terminal). The clock signal of the clock signal generation circuit 9 is not input to the clock signal input terminal. The clock signal of the clock signal generation circuit 9 is supplied to only the D terminal of the scan flip-flop 14 via the selector (selection circuit) 12 with respect to the scan flip-flop 14.

11 is the scan flip-flop 14
A scan flip-flop (first storage element) having the same internal configuration as
4 together with the scan path 20. The scan flip-flop 11 has a clock signal input terminal (control terminal) connected to a clock signal of the clock signal generation circuit 9 via a selector (another selection circuit) 13 and an external clock signal from the clock signal input terminal 5. , One of the selected clock signals is input. The selector 13 selects the clock signal of the clock signal generation circuit 9 when the test mode signal from the test mode signal input terminal 7 has a “0” value, that is, during a normal operation, and sets the test mode signal to a “1” value. In this case, that is, at the time of testing, the external clock signal from the clock signal input terminal 5 is selected.

Since other structures are the same as those of the first embodiment, the same portions are denoted by the same reference numerals and description thereof will be omitted.

Hereinafter, the operation of the semiconductor integrated circuit according to the present embodiment will be described with reference to FIG.

First, during normal operation, each signal of the scan enable signal input terminal 6 and the test mode signal input terminal 7 is fixed to the value "0". Therefore, the scan flip-flops 10, 11, and 14 receive an input signal from the D terminal and operate as a normal flip-flop, and the selector 13 selects a signal from the clock signal generation circuit 9. Since the scan flip-flop 10 has the D terminal connected to the ground, a reset signal of “0” value is input from the system reset signal input terminal, or a system clock signal is input from the clock signal input terminal 5. Then, the value of the Q terminal of the scan flip-flop 10 becomes the “0” value, and thereafter, the value of the Q terminal always remains at the “0” value during the normal operation. Therefore,
The selector 12 always selects a signal from the partial circuit 2.

At the time of the test, the signal at the test mode signal input terminal 7 is fixed at "1". Thereby, the selector 13 selects the scan clock signal from the clock signal input terminal 5 and the scan operation of the scan flip-flop 11 becomes possible. Scan-in terminal 3 → scan flip-flop 10 → scan flip-flop 1
1 → scan flip-flop 14 → scan-out terminal 8 constitutes a scan path 20. When a scan enable signal of “1” value is input to scan enable signal input terminal 6, each scan flip-flop 10, 1
1, 14 operate as shift registers and can perform scan-in / scan-out operations.

Here, when testing the signal from the partial circuit 2, a selection signal of "0" is set to the scan flip-flop 10 by a scan-in operation. Thereby, the selector 12 selects a signal from the partial circuit 2. The signal from the partial circuit 2 is taken in from the D terminal of the scan flip-flop 14, and is externally output from the scan-out terminal 8 by a scan-out operation. Therefore, the signal of the partial circuit 2 can be observed at the scan-out terminal 8.

When testing the clock signal generation circuit 9, a "1" value selection signal is set to the scan flip-flop 10 by a scan-in operation. As a result, the selector 12 selects the clock signal of the clock signal generation circuit 9, so that the clock signal of the clock signal generation circuit 9 is fetched from the D terminal of the scan flip-flop 14 and scanned out by the scan-out operation as described above. It is externally output from the terminal 8. Accordingly, since the clock signal of the clock signal generation circuit 9 can be observed at the scan-out terminal 8, it is not necessary to add an external terminal for observing the clock signal.

In the semiconductor integrated circuit shown in FIG. 1, when the static timing analyzer statically analyzes the timing using the static timing analyzer, the static timing analyzer applies a setup error or a hold error to the scan flip-flop 11. However, in the semiconductor integrated circuit of the present embodiment, since the clock signal of the clock signal generation circuit 9 does not reach the clock signal input terminal and the D terminal of the same scan flip-flop, , During static timing analysis using a static timing analyzer,
There is no possibility of causing a setup error or a hold error due to the signal input of the clock signal generation circuit 9, and the efficiency of the design process can be further improved.

Further, a storage element (not shown) in the partial circuit 2 for supplying data to the data input terminal D of the scan flip-flop (storage element) 14 has a clock signal input terminal as in the case of the scan flip-flop 14. Even if it operates with the clock signal from 5,
Since the selector 12 is arranged between the two storage elements, during normal operation, data from the storage element in the partial circuit 2 reaches the data input terminal D of the scan flip-flop 14 with a slight delay by the selector 12. I do. As a result, in the scan flip-flop 14, a timing difference occurs between the arrival of data at the data input terminal D and the arrival of the clock signal at the clock signal terminal.
4 can be prevented from being lost by the selector 12, and a malfunction caused by this loss can be avoided.

Next, a method of designing the semiconductor integrated circuit shown in FIG. 5 by a computer will be described with reference to the flowchart of FIG. This flowchart is actually configured by a computer-readable program, and is stored in a storage medium such as a floppy disk or a CD-ROM.

In FIG. 6, in step S1, a netlist of the semiconductor integrated circuit shown in FIG. 7 to be tested is input. The semiconductor integrated circuit to be tested basically includes a partial circuit 2, a clock signal generation circuit 9, and the two scan flip-flops 1 as shown in FIG.
1 and 14 corresponding to flip-flops 22, 24, a system reset input terminal 4, and a clock signal input terminal 5.

Next, in step S2, as shown in FIG. 8, a flip-flop 23 corresponding to the selection signal output circuit 10 is inserted, and
3 at step S2 in the flowchart of FIG.
The connection is made in the same manner as described above. Step S3 is the same as step S3 in the flowchart of FIG.
The clock signal generation circuit 9 searches for the flip-flop (memory element) to which the clock signal is supplied, that is, the flip-flop 22 in the semiconductor integrated circuit of FIG.

Next, in step S4, a flip-flop to which a clock signal different from the clock signal of the clock signal generation circuit 9 is supplied (a flip-flop having a different clock system), that is, a clock signal input terminal in the semiconductor integrated circuit of FIG. 5 is searched for a flip-flop 24 receiving a clock signal.

Subsequently, in step S5, a two-input type selector 12 is arranged on the data input terminal D side of the flip-flops 24 having different clock systems, and the output terminal of the selector 12 is connected to the flip-flop 24. Connect to data input terminal D. Further, this selector 12
The output terminal Q of the flip-flop 23 corresponding to the selection signal output circuit 10 is connected to the select terminal 12a, and the two input terminals of the selector are respectively connected to the signal during normal operation from the partial circuit 2 , And the clock signal of the clock signal generation circuit 9. As described above, the arrangement of the selector 12 has an effect of preventing the data transmission from the storage element (not shown) in the partial circuit 2 to the flip-flop 24 from being lost.

Further, in step S6, a two-input type selector 13 is arranged on the clock terminal side of all the flip-flops that receive the clock signal from the clock signal generation circuit 9, that is, one flip-flop 22, and this selector 13 Is connected to the clock terminal of the flip-flop 22. Further, the test mode signal input terminal 7
And the test mode signal input terminal 7 is connected to the select terminal 13a of the selector 13. Further, a clock signal generation circuit 9 and a clock signal input terminal 5 are connected to two data input terminals of the selector 13, respectively. At this point, the configuration shown in FIG. 8 is designed.

Finally, in step S7, a scan path is inserted into the semiconductor integrated circuit shown in FIG. In particular,
The three flip-flops 22, 23 and 24 are connected to the scan flip-flops 11, 10 and 1 as shown in FIG.
4 and these flip-flops 11,
A scan path is constituted by including 10 and 14. More specifically, a scan-in terminal 3, a scan enable signal input terminal 6, and a scan-out terminal 8 are added, and the scan enable terminals SE of the scan flip-flops 11, 10, and 14 are connected to the scan enable signal input terminal 6. At the same time, the scan-in terminal 3 is connected to the scan-in terminal SI of the scan flip-flop (selection signal output circuit) 10, and the output terminal Q of the scan flip-flop 10 is connected to the scan flip-flop 1.
Similarly, the output terminal Q of the scan flip-flop 11 is connected to the scan-in terminal SI of the scan flip-flop 14, and the output terminal Q of the scan flip-flop 14 is connected to the scan-out terminal 8. I do. As a result, the semiconductor integrated circuit of FIG. 5 is completed.

(Third Embodiment) FIG. 9 shows a third embodiment of the present invention.
1 shows a semiconductor integrated circuit according to an embodiment.

In FIG. 16, reference numeral 16 denotes a scan flip-flop constituting a scan path, which has the same internal configuration as the scan flip-flop 11 of the first embodiment and has the same function. Reference numeral 15 denotes a reset signal generation circuit (second partial circuit) for generating a reset signal during normal operation. Reference numeral 17 denotes an OR gate. The reset signal of the reset signal generation circuit 15 and the test mode of the test mode signal input terminal 7 While receiving the signal, the output signal is input to the R terminal of the scan flip-flop 16.

The other structure is the same as that of the first embodiment, and therefore, the same portions are denoted by the same reference characters and description thereof will be omitted.

Hereinafter, the operation of the semiconductor integrated circuit according to the present embodiment will be described with reference to FIG.

First, during a normal operation, the signal values of the scan enable signal input terminal 6 and the test mode signal input terminal 7 are fixed to "0" values. Therefore, the scan flip-flops 10 and 16 take in the input signal from the D terminal and operate as normal flip-flops.
The R gate 17 supplies the reset signal of the reset signal generation circuit 15 to the scan flip-flop 16 as it is. Since the scan flip-flop 10 has the D terminal connected to the ground, a reset signal of “0” value is input from the system reset signal input terminal 4 or a system clock signal is input from the clock signal input terminal 5. Then, the value of the Q terminal of the scan flip-flop 10 becomes the “0” value, and thereafter, the value of the Q terminal always remains at the “0” value during the normal operation. Therefore, selector 1
2 always selects the signal of the partial circuit 2.

At the time of testing, since the signal value of test mode signal input terminal 7 is fixed at "1", OR gate 1
The output of the scan flip-flop 16 is fixed to the value "1", the reset signal of the scan flip-flop 16 is always disabled, and the scan operation of the scan flip-flop 16 is enabled. The scan-in terminal 3 → scan flip-flop 10 → scan flip-flop 16 → scan-out terminal 8 constitutes a scan path 20. When a scan enable signal of “1” value is input to the scan enable input terminal 6, each scan flip-flop 10,
16 operates as a shift register and can perform scan-in / scan-out operations.

Here, when testing the signal from the partial circuit 2, a selection signal of "0" value is set in the scan flip-flop 10 by a scan-in operation. As a result, the selector 12 selects the signal from the partial circuit 2, and as described above, the signal from the partial circuit 2 is fetched from the D terminal of the scan flip-flop 16 and observed at the scan-out terminal 8 by the scan-out operation. Is done.

When testing the reset signal generation circuit 15, a selection signal having a value of "1" is set in the scan flip-flop 10 by a scan-in operation. As a result, the selector 12 selects the reset signal of the reset signal generation circuit 15, and as described above, the reset signal of the reset signal generation circuit 15 is fetched from the D terminal of the scan flip-flop 16 and is scanned out by the scan-out operation. Observed at terminal 8.

Therefore, the reset signal of the reset signal generation circuit 15 can be observed by a scan test without adding an external terminal for observation.

The method of designing a semiconductor integrated circuit shown in FIG. 9 is the same as the method of designing a semiconductor integrated circuit described in the first embodiment, and a description thereof will not be repeated.

Further, in the present embodiment, the second partial circuit is constituted by the reset signal generation circuit 15,
As a matter of course, a set signal generating circuit 21 for generating a set signal may be used as a matter of course. In this case, as shown in FIG.
6 'has a set terminal (S terminal) instead of the R terminal.

(Fourth Embodiment) FIG. 10 shows a semiconductor integrated circuit according to a fourth embodiment of the present invention. In the third embodiment, since the reset signal of the reset signal generation circuit 15 reaches both the R terminal and the D terminal of the scan flip-flop 16, the static timing analysis is performed using the static timing analyzer. , The static timing analyzer may report a setup error or a hold error to the scan flip-flop 16. The present embodiment solves this.

In FIG. 10, the scan flip-flop 16 ″ is not provided with an R terminal. The reset signal of the reset signal generation circuit 15 is supplied to only the D terminal of the scan flip-flop 16 '' via the selector 12. The clock signal input terminal of the scan flip-flop 16 ″ is supplied with a clock signal externally input from the clock signal input terminal 5.

Reference numeral 18 denotes a scan flip-flop (another storage element) having an R terminal similarly to the scan flip-flop 16 of the third embodiment. Constitute. The reset signal of the reset signal generation circuit 15 and the test mode signal from the test mode signal input terminal 7 are input to the R terminal of the scan flip-flop 18 via the OR gate 17.

Since the other structure is the same as that of the third embodiment, the same portions are denoted by the same reference numerals and description thereof will be omitted.

Hereinafter, the operation of the semiconductor integrated circuit according to the present embodiment will be described with reference to FIG.

First, during a normal operation, the signal values of the scan enable signal input terminal 6 and the test mode signal input terminal 7 are fixed to "0" values. Therefore, the scan flip-flops 10, 16 '' and 18 take in the input signal from the D terminal and operate as a normal flip-flop, and the OR gate 17 is connected to the reset signal generation circuit 15
Scan flip-flop 1
8 Since the scan flip-flop 10 has the D terminal connected to the ground, a reset signal of “0” value is input from the system reset signal input terminal 4 or a system clock signal is input from the clock signal input terminal 5. Then, the value of the Q terminal of the scan flip-flop 10 becomes “0”, and thereafter, the value of the Q terminal becomes
During normal operation, the value always remains at "0". Therefore, the selector 12 always selects the signal from the partial circuit 2.

At the time of a test, the signal value of test mode signal input terminal 7 is fixed at "1", so that OR gate 1
7, the output of the scan flip-flop 18 is fixed to "1", the reset signal of the scan flip-flop 18 is always disabled, and the scan flip-flop 18 can perform a scan operation. The scan-in terminal 3 → the scan flip-flop 10 → the scan flip-flop 18 → the scan flip-flop 16 ″ → the scan-out terminal 8 constitutes a scan path 20, and a “1” value scan enable signal is input to the scan enable signal input terminal 6. When input, each scan flip-flop 10, 18, 16 ''
Can operate as a shift register and perform scan-in / scan-out operations.

Here, when testing the signal from the partial circuit 2, a selection signal of "0" value is set in the scan flip-flop 10 by a scan-in operation. As a result, the selector 12 selects the signal from the partial circuit 2, and as described above, the signal from the partial circuit 2 is fetched from the D terminal of the scan flip-flop 16 ″, and the scan-out operation is performed. Observed at

When the reset signal generation circuit 15 is tested, a "1" value selection signal is set in the scan flip-flop 10 by a scan-in operation. As a result, the selector 12 selects the reset signal of the reset signal generation circuit 15, and as described above, the reset signal of the reset signal generation circuit 15 is fetched from the D terminal of the scan flip-flop 16 '', and Observed at scan-out terminal 8.

Therefore, the reset signal of the reset signal generation circuit 15 can be observed by the scan test without adding an external observation terminal.

In the semiconductor integrated circuit shown in FIG. 9, when static timing is analyzed using the static timing analyzer, the static timing analyzer applies a setup error or hold to the scan flip-flop 16. Although an error may be reported, in the semiconductor integrated circuit according to the present embodiment, the reset signal of the reset signal generation circuit 15 is set to the R terminal and the D terminal of the same scan flip-flop.
Since the signal does not reach the terminal, there is no possibility that a setup error or a hold error due to the input of the reset signal of the reset signal generating circuit 15 occurs even during static timing analysis using the static timing analyzer. Further, it is possible to further improve the efficiency of the design process.

The method of designing a semiconductor integrated circuit according to the present embodiment shown in FIG. 10 is the same as the method of designing a semiconductor integrated circuit described in the second embodiment, and a description thereof will be omitted. .

In the present embodiment, the second partial circuit is constituted by the reset signal generating circuit 15,
As shown in (1), a set signal generation circuit 21 may be used. In this case, as shown in the figure, the scan flip-flop 18 has an S terminal instead of the R terminal.

In the above description, the clock signal generation circuit 9, the reset signal generation circuit 15, and the set signal generation circuit 21 are given as examples of the second partial circuit, but the present invention is not limited to these. Alternatively, for example, a part of a combinational circuit having a complicated configuration may be a second partial circuit, or a sequential circuit may be a second partial circuit.

[0103]

As described above, according to the semiconductor integrated circuit of the first to tenth aspects of the present invention, at the time of testing, the output of an arbitrary sub-circuit under test such as a clock signal or reset signal generation circuit. A select signal output circuit that can easily extract the output of the partial circuit under test by the select signal output circuit.
Since this output can be input to a storage element constituting a scan path, the output of the partial circuit under test can be externally output from a scan-out terminal by a simple and arbitrary scan operation and observed. . Therefore, an external output terminal dedicated to a test for observing a clock signal or the like can be eliminated, and an increase in the number of terminals can be prevented. It is possible to eliminate the need to provide a signal line connected to the circuit and prevent an increase in circuit scale.

In particular, according to the semiconductor integrated circuit of the present invention, at the time of a test, when selecting an output of a partial circuit to be tested such as a clock signal generation circuit, the selection signal is passed through a scan path to the selection circuit. , The output of the partial circuit under test can be easily selected, and the test can be easily performed.

According to the semiconductor integrated circuit designing method of the present invention and the recording medium on which the semiconductor integrated circuit designing program of the present invention is recorded, the semiconductor integrated circuit having the above-mentioned effects can be easily obtained. Can be designed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a method of designing the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing an initial circuit configuration of a semiconductor integrated circuit under test corresponding to a netlist input first in the design method of FIG. 2;

FIG. 4 is a diagram showing a circuit configuration of a semiconductor integrated circuit under test at the time when a procedure up to arranging a selection signal output circuit and a selector in the design method is completed.

FIG. 5 is a diagram illustrating a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention;

FIG. 6 is a flowchart illustrating a method of designing a semiconductor integrated circuit according to a second embodiment of the present invention.

7 is a diagram showing an initial circuit configuration of a semiconductor integrated circuit under test corresponding to a netlist input first in the design method of FIG. 6;

FIG. 8 is a diagram showing a circuit configuration of a semiconductor integrated circuit under test at the time when a procedure up to arranging a selection signal output circuit and a selector in the design method is completed.

FIG. 9 is a diagram illustrating a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 10 is a diagram illustrating a configuration of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 11 is a diagram showing a modification of the semiconductor integrated circuit according to the third embodiment of the present invention.

FIG. 12 is a diagram showing a modification of the semiconductor integrated circuit according to the fourth embodiment of the present invention.

[Explanation of symbols]

2 partial circuit (first partial circuit) 9 clock signal generation circuit (second partial circuit) 10 selection signal output circuit (another storage element) D data input terminal SI scan-in terminal (scan data input terminal) Q data output Terminal (output terminal) 11 scan flip-flop (storage element, first storage element) 12 selector (selection circuit) 13 selector (other selection circuit) 14 scan flip-flop (second storage element) 15 reset signal generation circuit ( (Second partial circuit) 18 set signal generation circuit (second partial circuit) 20 scan path 21 set signal generation circuit (second partial circuit)

Claims (28)

[Claims] A storage element having a data input terminal and a control terminal and constituting a part of a scan path; a first partial circuit for generating data to be supplied to a data input terminal of the storage element during a normal operation; And a second partial circuit for generating a signal to be supplied to a control terminal of the storage element during a normal operation. A semiconductor integrated circuit, comprising: an output signal of the first partial circuit and an output signal of the second partial circuit. A selection circuit that selects one of them and supplies the selected signal to a data input terminal of the storage element; and a selection signal output circuit that outputs a selection signal instructing a selection operation of the selection circuit to the selection circuit. The selection signal output circuit is configured such that the selection circuit selects the output signal of the first partial circuit during the normal operation, and the selection circuit outputs the first signal during a test of the semiconductor integrated circuit. A semiconductor integrated circuit which outputs a selection signal so as to arbitrarily select one of the output signal of the partial circuit and the output signal of the second partial circuit. 2. The semiconductor integrated circuit according to claim 1, wherein said control terminal is a clock signal input terminal, and said second partial circuit is a clock signal generation circuit for generating a clock signal. 3. The semiconductor device according to claim 1, further comprising another selection circuit, wherein the other selection circuit selects an output signal of the second partial circuit during a normal operation, and the second partial circuit during a test of the semiconductor integrated circuit. 3. The semiconductor integrated circuit according to claim 2, wherein a clock signal provided from a circuit other than the circuit is selected, and the selected signal is input to a control terminal of the storage element. A first storage element having a control terminal and forming part of a scan path; a second storage element having a data input terminal and forming part of the scan path; A first partial circuit that generates data to be supplied to a data input terminal of the second storage element during operation; and a second partial circuit that generates a signal to be supplied to a control terminal of the first storage element during normal operation. In the semiconductor integrated circuit provided, one of an output signal of the first partial circuit and an output signal of the second partial circuit is selected, and the selected signal is used as a data input terminal of the second storage element. And a selection signal output circuit that outputs a selection signal instructing a selection operation of the selection circuit to the selection circuit. The selection signal output circuit is configured so that the selection circuit is configured to output the selection signal during the normal operation. One While selecting the output signal of the branch circuit, the test circuit arbitrarily selects one of the output signal of the first partial circuit and the output signal of the second partial circuit when testing the semiconductor integrated circuit. A semiconductor integrated circuit that outputs a selection signal. 5. The semiconductor integrated circuit according to claim 4, wherein said control terminal is a clock signal input terminal, and said second partial circuit is a clock signal generation circuit for generating a clock signal. 6. The semiconductor device according to claim 6, further comprising another selection circuit, wherein the other selection circuit selects an output signal of the second partial circuit during a normal operation, and the second partial circuit during a test of the semiconductor integrated circuit. 6. The semiconductor integrated circuit according to claim 5, wherein a clock signal supplied from a circuit other than the circuit is selected, and the selected signal is input to a control terminal of the first storage element. 7. The control circuit according to claim 1, wherein the control terminal is a reset signal input terminal, and the second partial circuit is a reset signal generation circuit for generating a reset signal.
A semiconductor integrated circuit as described in the above. 8. The semiconductor integrated circuit according to claim 1, wherein said control terminal is a set signal input terminal, and said second partial circuit is a set signal generation circuit for generating a set signal. . 9. The selection signal output circuit has another storage element forming the scan path, the another storage element receiving the selection signal from the outside via the scan path, and receiving the selection signal. 5. The semiconductor integrated circuit according to claim 1, wherein a signal is output to said selection circuit. 10. The another storage element, further comprising: a data input terminal to which a selection signal for causing the selection circuit to select an output signal of the first partial circuit is always input; and a selection signal from the outside via the scan path. A scan data input terminal that receives a scan enable signal that is input from the outside and an output terminal that outputs a selection signal to the selection circuit.
A selection signal for the data input terminal is output from the output terminal, and when the scan enable signal is input, a selection signal input to the scan data input terminal is output from the output terminal. 9
A semiconductor integrated circuit as described in the above. 11. A method for designing a semiconductor integrated circuit capable of inspecting the operation of an internal circuit, comprising: a storage element having a data input terminal and a control terminal; and a first element for generating data to be supplied to the data input terminal of the storage element. Inputting a netlist of a semiconductor integrated circuit including a partial circuit and a second partial circuit that generates a signal to be supplied to a control terminal of the storage element; an output signal of the first partial circuit and the second A selection circuit that selects one of the output signals of the partial circuits and supplies the selected signal to the data input terminal of the storage element; and a selection signal instructing a selection operation of the selection circuit to the selection circuit. Adding a selection signal output circuit to be output to the semiconductor integrated circuit; and configuring the storage element with a scan flip-flop, Inserting a scan path including a flop into the semiconductor integrated circuit. 12. The design of a semiconductor integrated circuit according to claim 11, wherein said control terminal is a clock signal input terminal, and said second partial circuit is a clock signal generation circuit for generating a clock signal. Method. 13. A method of selecting one of an output signal of the second partial circuit and a clock signal supplied from a source other than the second partial circuit, and applying the selected signal to a control terminal of the storage element. 13. The method for designing a semiconductor integrated circuit according to claim 12, further comprising a step of adding another selection circuit to the semiconductor integrated circuit. 14. A method for designing a semiconductor integrated circuit capable of inspecting the operation of an internal circuit, comprising: a first storage element having a control terminal, a second storage element having a data input terminal, and the second storage element. A first partial circuit for generating data to be supplied to a data input terminal of the element;
Inputting a netlist of a semiconductor integrated circuit including a second partial circuit that generates a signal to be supplied to a control terminal of the first storage element; and an output signal of the first partial circuit and the second A selection circuit that selects one of the output signals of the partial circuits and supplies the selected signal to a data input terminal of the second storage element; and a selection signal that instructs a selection operation of the selection circuit. Adding a selection signal output circuit to be output to the circuit to the semiconductor integrated circuit; and configuring the first and second storage elements with scan flip-flops, respectively, and a scan path including these scan flip-flops. Inserting the semiconductor integrated circuit into the semiconductor integrated circuit. 15. The design of a semiconductor integrated circuit according to claim 14, wherein said control terminal is a clock signal input terminal, and said second partial circuit is a clock signal generation circuit for generating a clock signal. Method. 16. A method for selecting one of an output signal of the second partial circuit and a clock signal supplied from a source other than the second partial circuit, and controlling the selected signal to control the first storage element. The method of designing a semiconductor integrated circuit according to claim 15, further comprising a step of adding another selection circuit to be applied to a terminal to the semiconductor integrated circuit. 17. The semiconductor integrated circuit according to claim 11, wherein the control terminal is a reset signal input terminal, and the second partial circuit is a reset signal generation circuit that generates a reset signal. Design method. 18. The control circuit according to claim 11, wherein the control terminal is a set signal input terminal, and the second partial circuit is a set signal generation circuit for generating a set signal.
The method for designing a semiconductor integrated circuit according to the above. 19. The method according to claim 11, wherein in the step of inserting a scan path into the semiconductor integrated circuit, the selection signal output circuit is constituted by a scan flip-flop, and the scan flip-flop is inserted into the scan path. 15. The method for designing a semiconductor integrated circuit according to 14. 20. A recording medium recording a design program for designing a semiconductor integrated circuit capable of inspecting the operation of an internal circuit by a computer, the design program comprising: a storage element having a data input terminal and a control terminal; A netlist of a semiconductor integrated circuit including a first partial circuit for generating data to be supplied to a data input terminal of the storage element and a second partial circuit for generating a signal to be supplied to a control terminal of the storage element is input. A step of selecting one of an output signal of the first partial circuit and an output signal of the second partial circuit, and supplying the selected signal to a data input terminal of the storage element; Adding, to the semiconductor integrated circuit, a selection signal output circuit that outputs a selection signal instructing a selection operation of the selection circuit to the selection circuit; A step of inserting the scan path including the scan flip-flop into the semiconductor integrated circuit, wherein the storage element is constituted by a scan flip-flop, and a design program for the semiconductor integrated circuit is recorded. 21. The semiconductor integrated circuit design according to claim 20, wherein said control terminal is a clock signal input terminal, and said second partial circuit is a clock signal generation circuit for generating a clock signal. A recording medium on which a program is recorded. 22. One of an output signal of the second partial circuit and a clock signal supplied from a source other than the second partial circuit, and the selected signal is supplied to a control terminal of the storage element. 22. The recording medium according to claim 21, further comprising a step of adding another selection circuit to said semiconductor integrated circuit. 23. A recording medium storing a design program for designing a semiconductor integrated circuit capable of inspecting the operation of an internal circuit by a computer, the design program comprising: a first storage element having a control terminal; A second storage element having an input terminal, a first partial circuit for generating data to be provided to a data input terminal of the second storage element,
Inputting a netlist of a semiconductor integrated circuit including a second partial circuit that generates a signal to be supplied to a control terminal of the first storage element; and an output signal of the first partial circuit and the second A selection circuit that selects one of the output signals of the partial circuits and supplies the selected signal to a data input terminal of the second storage element; and a selection signal that instructs a selection operation of the selection circuit. Adding a selection signal output circuit to be output to the circuit to the semiconductor integrated circuit; and configuring the first and second storage elements with scan flip-flops, respectively, and a scan path including these scan flip-flops. Inserting the program into the semiconductor integrated circuit. 24. The semiconductor integrated circuit design according to claim 23, wherein said control terminal is a clock signal input terminal, and said second partial circuit is a clock signal generation circuit for generating a clock signal. A recording medium on which a program is recorded. 25. A method for selecting one of an output signal of the second partial circuit and a clock signal supplied from a source other than the second partial circuit, and controlling the selected signal to control the first storage element. 25. The recording medium according to claim 24, further comprising a step of adding another selection circuit to be applied to a terminal to said semiconductor integrated circuit. 26. The semiconductor integrated circuit according to claim 20, wherein the control terminal is a reset signal input terminal, and the second partial circuit is a reset signal generation circuit that generates a reset signal. Recording medium that records the design program of the computer. 27. The control circuit according to claim 20, wherein the control terminal is a set signal input terminal, and the second partial circuit is a set signal generation circuit for generating a set signal.
A recording medium on which the design program for a semiconductor integrated circuit described above is recorded. 28. In the design program, in the step of inserting a scan path into a semiconductor integrated circuit, the selection signal output circuit is configured by a scan flip-flop, and the scan flip-flop is inserted into the scan path. A recording medium storing a semiconductor integrated circuit design program according to claim 20.