JPH1188911A - Three-dimensional video signal generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent production of flicker and to reduce the cost by applying interpolation and interleaving to a received 2-dimensional video signal for each field in a vertical direction, storing the resulting signal for a prescribed field from the newest field to the past, reading two video signals having a relative time difference and using the one for a left eye video signal and the other for a right eye video signal. SOLUTION: An integrated circuit 10 interleaves to a received 2-dimensional video signal while interpolating signal Y and color differences R-Y, B-Y of the 2-dimensional video signal in a vertical direction for each field by 1/2. The integrated circuit 10 stores the video signals obtained by above processing by a prescribed fields from the newest to the past to field memories 21-24. The integrated circuit 10 reads two video signals having a relative time difference from the field memories 21-24 and provides an output of a luminance signal and color difference signals of a left eye and a right eye video signal. Thus, the 3-dimensional video signal generator is obtained at a low cost without flicker.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-dimensional video signal generator.

[0002]

2. Description of the Related Art As a three-dimensional video signal generator, there is a two-dimensional / three-dimensional video converter for converting a two-dimensional video into a three-dimensional video signal. In a two-dimensional / three-dimensional video converter, for example, a two-dimensional video is converted into a first video signal serving as a reference
A second video signal delayed with respect to the first video signal is generated. One of these is used as a left-eye video signal, and the other is used as a right-eye video signal.

As the first video signal, an original two-dimensional video signal is generally used as it is. The amount of delay of the second video signal with respect to the first video signal is determined according to the speed of the video motion of the two-dimensional video signal. The second video signal is generated as follows.

That is, a predetermined number of past fields from the latest field of a two-dimensional video signal input to a two-dimensional / three-dimensional video converter are stored in a plurality of delay field memories in field units. Then, from the two-dimensional video signals stored in each of the delay field memories, a two-dimensional video signal corresponding to the delay amount determined according to the speed of the video motion of the two-dimensional video signal is read. The two-dimensional video signal read from the delay field memory is the second video signal.

When the left-eye video signal and the right-eye video signal obtained in this manner are alternately displayed on a display device, each of the left-eye video signal and the right-eye video signal is normally output per unit time. Since only 1/2 of the number of fields is displayed, flicker occurs.

Therefore, the occurrence of flicker is prevented by converting the field frequency to twice the normal frequency.
As a method of converting the field frequency to twice the normal frequency (double-speed conversion), for example, a separate double-speed conversion field memory for storing the left-eye video signal and the right-eye video signal obtained as described above is provided. The frequency of the read clock of the double-speed conversion field memory may be set to twice the frequency of the write clock of the double-speed conversion field memory.

In such a method, a double speed conversion field memory is required in addition to the delay field memory. Therefore, the present applicant has developed the following method.
That is, two video signals having a relative time difference are respectively read from the plurality of delay field memories,
One is output as a left-eye video signal, and the other is output as a right-eye video signal. The frequency of the read clock of each delay field memory is set to twice the frequency of the write clock of each delay field memory.

[0008]

In the above-mentioned double speed conversion method, not only the vertical frequency of the video signal but also the horizontal frequency is two.
Since the conversion is performed twice, a special deflection system for the display device must be used, which causes a problem that the cost is increased.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a three-dimensional video signal generating apparatus capable of preventing flicker and reducing the cost.

[0010]

According to a first aspect of the present invention, there is provided:
The two-dimensional video signal generating apparatus includes: a thinning unit that thins out the input two-dimensional video signal by し な が ら in the vertical direction while interpolating in the vertical direction for each field; and a video signal obtained by the thinning unit for each field. From a plurality of field memories for storing a predetermined number of past fields from the latest field, and from a plurality of field memories,
There is provided a means for reading out two video signals having a relative time difference, outputting one as a left-eye video signal, and outputting the other as a right-eye video signal.

In the decimation means, an interpolation coefficient used for an odd field and an interpolation coefficient used for an even field are set between an image obtained for an odd field and an image obtained for an even field. In the above, it is preferable to set the distance between adjacent horizontal lines between fields so as to be constant.

[0012] A second three-dimensional video signal generating apparatus according to the present invention is a thinning-out means for thinning out an input time-division three-dimensional image in a vertical direction for each field while reducing the vertical direction by a factor of two. A field memory for sequentially storing the video signals obtained by the means, and a means for sequentially reading and outputting the video signals from the field memory.

In the above-mentioned decimation means, an interpolation coefficient used for an odd field and an interpolation coefficient used for an even field are set between an image obtained for an odd field and an image obtained for an even field. In the above, it is preferable to set the distance between adjacent horizontal lines between fields so as to be constant.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

[1] Description of Configuration of 2D / 3D Video Converter FIG. 1 shows the configuration of a 2D / 3D video converter.

The two-dimensional / three-dimensional video converter comprises an integrated circuit (LSI) 10, a plurality of field memories 21 to 24 connected to the integrated circuit 10, and a CPU 30.

The integrated circuit 10 receives a luminance signal (Y signal) and a color difference signal (RY signal, BY signal) constituting a two-dimensional video signal or a time-division three-dimensional signal.
The integrated circuit 10 outputs a right-eye video signal and a left-eye video signal having a relative time difference. The right-eye video signal includes a right-eye luminance signal Y (R) and a right-eye color difference signal R-R.
Y (R) and BY (R). The left-eye video signal includes a left-eye luminance signal Y (L) and a left-eye color difference signal RY.
(L) and BY (L).

A circuit for the luminance signal Y and a color difference signal R-
Since the circuit for Y and BY is the same, the circuit for the color difference signal RY signal and the BY signal is omitted in FIG.

The integrated circuit 10 includes a field double speed conversion circuit 11, a motion vector detection circuit 12, a first inter-field interpolation circuit 13, a second inter-field interpolation circuit 14, a first blanking addition circuit 15, and a second blanking addition circuit. 1
6, a first synchronization signal addition circuit 17, a second synchronization signal addition circuit 18, a timing control circuit 19, a CPU interface 20, and a clock selection circuit 21.

This two-dimensional / three-dimensional video converter has the following four operation modes.

(1) First Mode (Normal Speed 2D / 3D Conversion Mode) The first mode is a mode for converting a two-dimensional video signal into a three-dimensional video signal, and has a horizontal and vertical frequency of two-dimensional video signal. This is a mode for generating the same three-dimensional video signal as the horizontal and vertical frequencies.

(2) Second Mode (HV Double Speed 2D / 3D Conversion Mode) The second mode is a mode for converting a two-dimensional video signal into a three-dimensional video signal, and has a horizontal and vertical frequency of two-dimensional video signal. This is a mode for generating a three-dimensional video signal whose frequency is twice the horizontal and vertical frequencies.

(3) Third Mode (V Double Speed 2D / 3D Conversion Mode) The third mode is a mode for converting a two-dimensional video signal into a three-dimensional video signal, and the horizontal frequency is the horizontal frequency of the two-dimensional video signal. This is a mode for generating a three-dimensional video signal whose vertical frequency is twice as high as the vertical frequency of the two-dimensional video signal.

(4) Fourth Mode (V Double Speed Conversion Mode) In the fourth mode, a time-division three-dimensional video signal is converted into a three-dimensional video signal having a double vertical frequency while keeping the horizontal frequency unchanged. It is.

From the field double speed conversion circuit 11, the first
In the mode or the second mode, the input video signal Y is output as it is. In the third mode or the fourth mode, the field double speed conversion circuit 11 outputs a video signal obtained by interpolating the input video signal Y in the vertical direction.

The motion vector detection circuit 12 detects a motion vector for each field from the input video signal Y. The motion vector detected by the motion vector detection circuit 12 is sent to the CPU interface 20 via the CP.
It is sent to U30.

The CPU 30 calculates the number of delay fields based on the horizontal component of the motion vector. The number of delay fields indicates the time difference between the two-dimensional video signal and the number of fields when two video signals having a time difference are generated. In this example, the number of delay fields can be expressed to a unit smaller than the field unit. That is, the number of delay fields is represented by an integer part and a decimal part. The number of delay fields is determined to be smaller as the horizontal component of the motion vector is larger. Then, based on the determined number of delay fields, a field memory from which the video signal is to be read is determined.

When the CPU 30 generates two video signals having a relative time difference from the two-dimensional video signal, the CPU 30 converts any of the video signals into a right-eye video signal and converts any of the video signals into a left-eye video signal. Is determined by the direction (left or right) of the horizontal component of the motion vector. Based on this determination, the video signal sent to the first inter-field interpolation circuit 13 and the second inter-field interpolation circuit 14 is determined.

The first inter-field interpolation circuit 13 and the second
The inter-field interpolation circuit 14 is for generating a video signal corresponding to a field delay number of a unit equal to or smaller than a field unit. That is, the first inter-field interpolation circuit 13
The second inter-field interpolation circuit 14 has a function of generating a video signal according to the field delay number of a unit equal to or less than a field unit by performing an interpolation process between video signals of two continuous fields. . As such an interpolation circuit, an interpolation circuit disclosed in Japanese Patent Application Laid-Open No. Hei 9-116930 can be used.

The timing control circuit 19 outputs timing signals for writing and reading data to and from the field memory. WCLK is a write clock signal. This clock signal is generated based on a first reference clock signal CLK1 having a frequency of fo. WRST is a write reset signal for controlling write start timing. WE is a write enable signal indicating a write period.

RCLK is a read clock signal. This clock signal is generated based on the clock signal selected by the clock selection circuit 21 from the first reference clock signal CLK1 whose frequency is fo or the second reference clock signal CLK2 whose frequency is twice fo. . RRST is a read reset signal for controlling read start timing. RE is a read enable signal indicating a read period.

[2] Description of Configuration of Field Double Speed Conversion Circuit 11 FIG. 2 shows a configuration of the field double speed conversion circuit 11.

The field double speed conversion circuit 11 includes a line memory 41, a first selection circuit 42, a second selection circuit 43,
A bit shift calculator 44, a first adder 45, a second adder 46, a second bit shift calculator 47, and a third selector 48 are provided.

The first bit shift calculator 44 shifts the input signal by one bit to the left. The second bit shift calculator 47 is a calculator that shifts the input signal rightward by two bits.

The video signal Y input to the field double speed conversion circuit 11 is sent to the line memory 41 and stored therein. The line memory 41 outputs a video signal Y (1HDL) one horizontal line before the video signal Y currently input to the field double speed conversion circuit 11.

The video signal Y input to the field double speed conversion circuit 11 is supplied to the first input terminal (E) of the first selection circuit 42, the second input terminal (O) of the second selection circuit 43, and the third selection terminal. The signal is sent to the first input terminal (I1) of the circuit 48.

The second input terminal (O) of the first selection circuit 42 and the first input terminal (E) of the second selection circuit 43 are connected to the video signal Y (1 HD
L) is sent.

The output of the first selection circuit 42 is sent to a first bit shift calculator 44 and to a first adder 45. The output of the first bit shift calculator 44 is also sent to the first adder 45. Therefore, in the first adder 45,
The output of the first selection circuit 42 and the first bit shift calculator 44
Is added to the output.

The output of the first adder 45 and the second selection circuit 4
The output of 3 is sent to the second adder 46 and added.
The output of the second adder 46 is a second bit shift operation unit 47
Sent to The output of the second bit shift calculator 47 is sent to the second input terminal (I2) of the third selector 48.

As the operation mode, the first mode or the second mode
When the mode is set, the third selection circuit 48
Selects and outputs the video signal input to the first input terminal (I1) of the third selection circuit 48. That is, in the first mode or the second mode, the video signal Y input to the field double speed conversion circuit 11 is output from the field double speed conversion circuit 11 as it is.

In the third mode and the fourth mode, the third selection circuit 48 selects and outputs the video signal input to the second input terminal (I2) of the third selection circuit 48. The video signal input to the second input terminal (I2) of the third selection circuit 48 will be described.

First, the case where the field of the video signal Y input to the field double speed conversion circuit 11 is an odd field (ODD field) will be described.

When the field of the input signal (Y) is an odd field, the first selection circuit 42 and the second selection circuit 43 select the signals input to their second input terminals (O). Output. Therefore, from the first selection circuit 42, the video signal Y (1) one line before the video signal Y currently input to the field double speed conversion circuit 11 is output.
HDL) is output from the second selection circuit 43 to the video signal Y currently input to the field double speed conversion circuit 11.
Is output.

The video signal Y (1HDL) output from the first selection circuit 42 is sent to a first bit shift calculator 44 and to a first adder 45. Since the input signal Y (1HDL) is shifted leftward by one bit in the first bit shift operator 44, the first bit shift operator 4
4, the signal {Y (1HDL) × 2} which is twice the input signal
Is output.

In the first adder 45, the signal Y (1HDL)
And the signal {Y (1HDL) × 2} are added, so that the first adder 45 outputs the signal {Y (1H)
DL) + Y (1HDL) × 2} is output.

Since the output of the first adder 45 and the output of the second selection circuit 43 are added in the second adder 46, the signal ΔY + Y (1HD
L) + Y (1HDL) × 2} is output.

The output of the second adder 46 is sent to a second bit shift calculator 47. In the second bit shift calculator 47, the input signal is shifted rightward by two bits, so that the second
A signal [ビ ッ ト Y + Y (1HDL) + Y (1HDL) × 2} / １
4] is output. That is, when the field of the input signal (Y) is an odd field, the third selection circuit 48
Is input to the signal {0.25Y + 0.
75Y (1HDL)} is sent.

That is, if the field of the input signal (Y) is an odd field, the video signal Y input to the field double speed conversion circuit 11 is multiplied by a coefficient of 0.25, A signal corresponding to the sum of the output video signal Y (1HDL) one horizontal line before and the video signal multiplied by the coefficient 0.75 is sent to the second input terminal (I2) of the third selection circuit 48.

Next, the case where the field of the signal (Y) input to the field double speed conversion circuit 11 is an even field (EVEN field) will be described.

When the field of the input signal (Y) is an even field, the first selection circuit 42 and the second selection circuit 43 select the video signal input to their first input terminals (E). And output. Therefore, the signal Y currently input to the field double speed conversion circuit 11 is output from the first selection circuit 42, and the signal Y currently input to the field double speed conversion circuit 11 is output from the second selection circuit 43. The signal Y (1HDL) one line before is output.

The signal Y output from the first selection circuit 42
Is sent to the first bit shift calculator 44 and to the first adder 45. First bit shift calculator 44
Since the input signal Y is shifted one bit to the left,
The first bit shift calculator 44 outputs a signal Y × 2 which is twice the input signal.

In the first adder 45, the signal Y and the signal Y × 2
Are added, the first adder 45 outputs a signal {Y + Y × 2} obtained by adding them.

In the second adder 46, the output of the first adder 45 and the output of the second selection circuit 43 are added, so that the second adder 46 adds the signal ｛Y (1HDL)
+ Y + Y × 2} is output.

The output of the second adder 46 is sent to a second bit shift calculator 47. In the second bit shift calculator 47, the input signal is shifted rightward by two bits, so that the second
From the bit shift calculator 47, a signal [{Y (1HDL) + Y + Y × 2} / 4] that is 1/4 times the input signal is output. That is, when the field of the input signal (Y) is an even field, the signal {0.25Y (1HDL) +0.7} is applied to the second input terminal (I2) of the third selection circuit 48.
5Y} is sent.

That is, if the field of the input signal (Y) is an even field, the video signal Y input to the field double speed conversion circuit 11 is multiplied by a coefficient of 0.75, A signal corresponding to the sum of the output video signal Y (1HDL) one horizontal line before and the video signal multiplied by the coefficient 0.25 is sent to the second input terminal (I2) of the third selection circuit 48.

When an odd field is input, of the video signals output from the third selection circuit 48,
As shown by the solid line in FIG. 3, the video signal obtained by multiplying the video signal of the odd-numbered horizontal line in the odd field by the coefficient 0.75 and the video signal of the next even-numbered horizontal line have the coefficient 0.25. Only the signal corresponding to the sum of the multiplied video signal is written to the field memory. That is, of the video signals output from the third selection circuit 48, the video signal obtained by multiplying the video signal of the even-numbered horizontal line by the coefficient 0.75 and the video signal of the next odd-numbered horizontal line have the coefficient 0 The video signal multiplied by .25 is not written to the field memory.

When an even-numbered field is input, the video signal of the odd-numbered horizontal line in the even-numbered field is output from the video signal output from the third selection circuit 48, as shown by the broken line in FIG. Only the signal corresponding to the sum of the video signal obtained by multiplying the signal by the coefficient 0.25 and the video signal obtained by multiplying the video signal of the next even-numbered horizontal line by the coefficient 0.75 is written into the field memory. That is,
Of the video signals output from the third selection circuit 48, the video signal obtained by multiplying the video signal of the even-numbered horizontal line by the coefficient 0.25 and the video signal of the next odd-numbered horizontal line by the coefficient 0.75 Is not written into the field memory.

Therefore, in the third mode and the fourth mode, the video signal of each field written in the field memory is the same as the signal obtained by thinning the video signal of each original field in half in the vertical direction. Become.

Also, from FIG. 3, the interpolation coefficients used in the odd field and the even field are adjacent to each other between the video obtained for the odd field and the video obtained for the even field. It will be appreciated that the horizontal line distance is set to be constant.

[3] Description of Operation in Each Mode [3-1] Description of Operation in First Mode In the first mode, the field double speed conversion circuit 11
, The signal Y input to the integrated circuit 10 is output as it is. The signal Y output from the field double speed conversion circuit 11 is sent to the first inter-field interpolation circuit 13 and the second inter-field interpolation circuit 14 as a through signal.
The signal Y output from the field double speed conversion circuit 11 is written into each field memory in a predetermined order on a field basis.

On the other hand, among the video signals for the past four fields stored in the field memories 21 to 24, in order to generate a delayed video delayed from the through video by the number of delay fields determined by the CPU 30,
Video signals of two consecutive fields corresponding to the number of delay fields determined by 30 are read from the field memory.

In the first mode, write clock signal WCLK and read clock signal RCLK
Are generated based on the first reference clock signal CLK1, and both have the same frequency.

As described above, which of the through image and the delayed image is used as the right-eye image and which is used as the left-eye image depends on the direction of the horizontal component of the motion vector detected by the motion vector detection circuit 12 (as described above). Left or right). Here, a case will be described where the through image is the right-eye image and the delayed image is the left-eye image.

In such a case, the video signals of two consecutive fields read from the field memory are sent to the second inter-field interpolation circuit 14. The second inter-field interpolation circuit 14 generates a delayed image delayed by the number of delay fields with respect to the through image by interpolating the video signals of two consecutive fields sent. After the blanking is added to the delayed video signal output from the second inter-field interpolation circuit 14 by the blanking addition circuit 16 and the synchronization signal is added by the synchronization signal addition circuit 18, the left-eye video signal Y ( L).

The through video signal is output from the first inter-field interpolation circuit 13 as it is. After the blanking is added to the through video signal output from the first inter-field interpolation circuit 13 by the blanking addition circuit 15 and the synchronization signal is added by the synchronization signal addition circuit 17, the right-eye video signal Y ( R).

[3-2] Description of Operation in Second Mode In the second mode, the field double speed conversion circuit 11
, The signal Y input to the integrated circuit 10 is output as it is. The signal Y output from the field double speed conversion circuit 11 is written into each field memory in a predetermined order on a field basis.

In the second mode, two video signals having a time difference from each other are generated from the video read from the field memory. That is, the reference video signal is read from the field memory in which the latest video signal (hereinafter, referred to as a reference video signal) is stored. In addition, in order to generate a delayed video signal delayed by the number of delay fields determined by the CPU 30 with respect to the reference video signal, video signals of two consecutive fields corresponding to the number of delayed fields are read from the field memory.

In the second mode, write clock signal WCLK is generated based on first reference clock signal CLK1, and read clock signal RCLK is generated based on second reference clock signal CLK2. Therefore, the frequency of read clock signal RCLK is twice the frequency of write clock signal WCLK. Therefore, the video signal read from the field memory is a signal whose horizontal and vertical frequencies are twice those of the original two-dimensional video signal.

When the reference image is the right-eye image and the delayed image is the left-eye image, the reference image signal read from the predetermined field memory is sent to the first inter-field interpolation circuit 13. In addition, 2 corresponding to the number of delay fields read from the predetermined two field memories.
The video signals of two consecutive fields are sent to the second inter-field interpolation circuit 14.

The first inter-field interpolation circuit 13 outputs the reference video signal as it is. After blanking is added to the through video signal output from the first inter-field interpolation circuit 13 by the blanking addition circuit 15, the right-eye video signal Y ( R).

The second inter-field interpolation circuit 14 generates a delayed image delayed by the number of delayed fields with respect to the through image by interpolating the video signals of the two continuous fields sent. After the blanking is added to the delayed video signal output from the second inter-field interpolation circuit 14 by the blanking addition circuit 16, the left-eye video signal Y ( L).

In the second mode, the three-dimensional video signal output from the integrated circuit 10 is a signal whose horizontal and vertical frequencies are twice those of the original two-dimensional video signal.

[3-3] Description of Operation in Third Mode In the third mode, the field double speed conversion circuit 11
Are written into the field memory in a predetermined order by the above-described writing method. Therefore, the field memory stores a video signal in which the input video Y is thinned out in the vertical direction by ２.

However, the data amount of the video signal written in each field memory is half. Writing to the field memory is always written from the beginning.

In the third mode, two video signals having a relative time difference are both generated from the video read from the field memory. That is, the reference video signal is read from the field memory in which the latest video signal (hereinafter, referred to as a reference video signal) is stored. In addition, in order to generate a delayed video signal delayed by the number of delay fields determined by the CPU 30 with respect to the reference video signal, video signals of two consecutive fields corresponding to the number of delayed fields are read from the field memory.

In the third mode, write clock signal WCLK and read clock signal RCLK
Are generated based on the first reference clock signal CLK1, and both have the same frequency.

When the reference image is the right-eye image and the delayed image is the left-eye image, the reference image signal read from the predetermined field memory is sent to the first inter-field interpolation circuit 13. In addition, 2 corresponding to the number of delay fields read from the predetermined two field memories.
The video signals of two consecutive fields are sent to the second inter-field interpolation circuit 14.

The first inter-field interpolation circuit 13 outputs the reference video signal as it is. After blanking is added to the through video signal output from the first inter-field interpolation circuit 13 by the blanking addition circuit 15, the right-eye video signal Y ( R).

The second inter-field interpolation circuit 14 generates a delayed image delayed by the number of delay fields with respect to the through image by interpolating the video signals of the two continuous fields sent. After the blanking is added to the delayed video signal output from the second inter-field interpolation circuit 14 by the blanking addition circuit 16, the left-eye video signal Y ( L).

FIG. 4 shows the control timing of the field memories 21 to 24 when the number of delay fields is 3.0. As can be seen from this figure, one of the two-dimensional video signals
The read clock signal RCL having the same frequency as the write clock signal WCLK is provided every half of the field period.
Since a video signal corresponding to one field (a video signal decimated by に in the vertical direction) is read by K, the three-dimensional video signal output from the integrated circuit 10 is:
The horizontal frequency is the same as the original two-dimensional video signal, and the vertical frequency is twice as high.

That is, if the vertical frequency of the original two-dimensional video signal is 60 Hz and the horizontal frequency is 15.75 KHz, the vertical frequency of the three-dimensional video signal is 120 Hz.
And the horizontal frequency is 15.75 KHz.

[3-4] Description of Operation in Fourth Mode In the fourth mode, the video signal obtained by thinning out the time-division three-dimensional video signal Y by に in the vertical direction is stored in the first field memory 21. Is stored.

In the fourth mode, write clock signal WCLK and read clock signal RCLK
Are generated based on the first reference clock signal CLK1, and both have the same frequency.

As shown in FIG. 5, when an input video signal (a time-division three-dimensional video signal) is represented by L1, R1, L2, R2,... The signal is applied to the field memory 21 during the first field period T1.
Is written into the first half of the field memory 21 in the second field period T2. In the second field period T2, a video signal in which the video signal L1 has been decimated by に in the vertical direction is read from the field memory 21, and the video signal R1 is output in the vertical direction by 1
The video signal decimated to / 2 is read. Thereafter, the same operation is repeated.

In the fourth mode, the three-dimensional video signal output from the integrated circuit 10 has the same horizontal frequency and twice the vertical frequency as the original three-dimensional video signal.

[0086]

According to the present invention, the occurrence of flicker can be prevented and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a 2D / 3D video conversion device.

FIG. 2 is a circuit diagram showing a configuration of a field double speed conversion circuit.

FIG. 3 is an explanatory diagram for explaining an interpolation method and a thinning method by a field double speed conversion circuit.

FIG. 4 is a time chart showing control timing of a field memory in a third mode.

FIG. 5 is a time chart showing a control timing of a field memory in a fourth mode.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Integrated circuit 11 Field double speed conversion circuit 12 Motion vector detection circuit 13, 14 Inter-field interpolation circuit 15, 16 Blanking addition circuit 17, 18 Synchronization signal addition circuit 19 Timing control circuit 20 CPU interface 21 Clock selection circuit 21-24 Field memory 30 CPU 41 Line memory 42, 43, 48 Selection circuit 44, 47 Bit shift calculator 45, 46 Adder

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Haruhiko Murata 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd.

Claims (4)

[Claims] 1. A thinning means for thinning an input two-dimensional video signal by １ ／ in a vertical direction while interpolating in a vertical direction for each field, a video signal obtained by the thinning means is converted for each field by A plurality of field memories for storing a predetermined number of past fields from the latest field, and two video signals having a relative time difference are read from the plurality of field memories, and one is output as a left-eye video signal, and the other is output. Means for outputting a right-eye image signal as a right-eye image signal. 2. An interpolating coefficient used for an odd field and an interpolating coefficient used for an even field in the decimation means are obtained by comparing a video obtained for an odd field with a video obtained for an even field. 2. The three-dimensional video signal generating apparatus according to claim 1, wherein the distance between adjacent horizontal lines between the fields is set to be constant. 3. A thinning-out means for thinning out an input time-division three-dimensional image by フ ィ ー ル ド in the vertical direction while interpolating in the vertical direction for each field, and video signals obtained by the thinning-out means are sequentially stored. A three-dimensional video signal generating apparatus, comprising: a field memory; and means for sequentially reading and outputting video signals from the field memory. 4. An interpolation coefficient used for an odd field and an interpolation coefficient used for an even field in the decimation means, wherein an interpolation coefficient between an image obtained for an odd field and an image obtained for an even field is determined. 4. The three-dimensional video signal generating apparatus according to claim 3, wherein the distance between adjacent horizontal lines between the fields is set to be constant.