JPH1188199A - Interleave circuit and de-interleave circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a circuit to use one memory so as to effectively execute data arrangement without imposing a load on a control section. SOLUTION: A memory 100 includes a 1st buffer area and a 2nd buffer area, and for each address a data area A to which data to be rearranged are written and an address area B to which respective succeeding write destination addresses are written in advance are formed. A next address setting section 106 sets an address from an address area corresponding to an address of data in the case of writing the data sequentially to a write control section 104. The write control section 104 accesses each address sequentially according to each set address and writes data in a prescribed sequence. A read control section 108 accesses sequentially the 2nd buffer area while the write control section 104 accesses the 1st buffer area and accesses sequentially the 1st buffer area while the write control section 104 accesses the 2nd buffer area to read data in the arrangement different from the data arrangement to be received.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interleave circuit and a deinterleave circuit, and more particularly to an interleave circuit and a deinterleave circuit applied to, for example, an encoding circuit or a decoding circuit used in a digital cellular phone or car phone. It relates to an interleave circuit.

[0002]

2. Description of the Related Art For example, when an audio signal or the like is digitized and transmitted, a CR is used to correct a transmission error.
Various error correction codes such as block codes such as C (cyclic redundancy check) or convolutional codes are used. These error correction codes have high detection and correction capabilities for random errors. However, the capability of detecting and correcting continuous burst errors caused by fading or the like is not so high. Therefore, the rearrangement of the encoded signal sequence is transmitted, and the receiving side rearranges the signal to the original sequence, so that interleaving technology that disperses burst errors occurring in the communication path and improves error correction capability is also used. Is done.

More specifically, as described in, for example, Hideki Imai, "Code Theory," Institute of Electronics, Information and Communication Engineers, pp. 220-221, a signal C is encoded into a code having a code length n and an error correction capability L. To form m codewords, which are m × n
M so that each code is arranged in the row direction in the memory of the array of
Accumulate. As a result, data in an array of m rows and n columns is formed, and when the data is read out in the column direction, that is, orthogonally to the row direction written in the memory, the respective codes are read out after being interlaced m times. The result of the interlacing is a sequence of length mn. Even if a burst error of length mL occurs, if this is rearranged into the original arrangement, the length L of each code is obtained.
This results in the following error: As a result, effective error correction is enabled for each code, and coding with a code length mn and burst error correction capability mL is realized by interleaving.

Conventionally, as a circuit for realizing the above-described interleaving, a memory having an m.times.n array and addresses in the row direction of the array are sequentially calculated, and input data is stored in the memory in the row direction of the data array. And a read control unit for sequentially calculating addresses in the column direction of the data array in the memory and reading out the written data sequentially in the column direction of the array. In this case, the reading must be performed after the data has been completely written to the memory. Therefore, in practice, at least two or more memories are prepared, and data is read from the other memory while data is written to one memory. Therefore,
A switching control unit that sequentially switches memories in cooperation with each of the write control unit and the read control unit is included.

A deinterleave circuit for rearranging interleaved data into data of an original array prepares two or more m × n arrays of memories in the same manner as described above, and calculates addresses in the column direction. A write control unit for sequentially writing received data to the memory in the column direction, a read control unit for calculating the address in the row direction and sequentially reading the written data in the row direction, and a switching control for switching these memories in cooperation with each other Parts. As a result, the data received in each memory is sequentially written in the row direction, and is read out in the column direction, whereby the data interleaved by the interleave circuit is rearranged into the original arrangement.

[0006]

However, in the above-mentioned prior art, two or more m.times.n arrays of memories must be prepared, and these memories must be sequentially switched to control the writing and reading of data. However, as the number of memories increases, the switching control becomes more complicated, and there is a problem that a load is placed on the switching controller.

In view of this, for example, two or more m × n buffer areas are prepared in one memory, and control is performed such that while data is sequentially written in one area, data is read in the other area. And then perform interleaving. Thereby, the switching control of the memory can be omitted. However, in this case, when moving from one buffer area to the other buffer area, the calculation of the address is different from the address calculation in the buffer area, so that the program of the write control unit or the read control unit becomes complicated. There was a problem.

Further, in the above-mentioned conventional technique, a crossing method of rearranging rows and columns of a data array is used. However, depending on interleaving, various patterns such as oblique rearrangement of a data array or random rearrangement may be employed. In these cases, there is a problem that the program of the write control unit or the read control unit is further complicated.

In a memory such as a RAM, each address is often accessed in a byte unit or a word unit. In an interleave circuit and a deinterleave circuit for rearranging in a bit unit or a several bit unit, Data having a smaller number of bits than the capacity must be stored in an address indicating each byte or word of the memory and rearrangement is performed, resulting in a problem that the efficiency of use of the memory is low.

The present invention solves such disadvantages of the prior art, and efficiently executes at least one type of memory and effectively executes various types of interleaving without burdening each control unit accessing the memory. It is an object of the present invention to provide an interleave circuit and a deinterleave circuit that can perform the operations.

[0011]

SUMMARY OF THE INVENTION An interleave circuit and a deinterleave circuit according to the present invention, in order to solve the above-mentioned problems, provide an interleave circuit which inputs data of a predetermined array, rearranges the array and outputs the data. In deinterleaving for rearranging the rearranged data into the original array, a storage means having a buffer area of at least n times (n is an integer of 2 or more) the period of the data array to be rearranged. A storage unit in which a data area to which data is written and an address area in which an address value indicating the next data write destination is written in advance, and data to be sequentially accessed and input to the data area of each address of the storage unit Data writing means for writing data, and the data writing means for writing data by the data writing means. The next address setting means for reading the address value written in the address area of the accessed address and setting the address value in the data writing means, and the order of writing the data written in the storage means in the data writing means Data reading means for reading data in a different order, wherein the data reading means reads data by sequentially accessing at least a buffer area different from a buffer area accessed by the data writing means.

In this case, the address value previously written in the address area is such that the address value indicating the address next to the address accessed last in each buffer area is accessed first in the next buffer area. The address value of the address indicates the address value, all the remaining address values are address values indicating addresses in the buffer area, and the data writing means initializes the address value of the address accessed first in the arbitrary buffer area. It is advantageous to sequentially access the addresses of the respective buffer areas in response to the address values from the storage means which are set in advance as addresses and subsequently set by the next address setting means.

In this case, the address value indicating the address in the buffer area may be an address value indicating the address in the column direction of the data array in the buffer area.

The address value indicating an address in the buffer area may be an address value indicating an arbitrary different address of a data array in the buffer area.

In these cases, the data reading means sets the address in the buffer area at least as the minimum address value of a buffer area different from the buffer area in which the initial address accessed by the data writing means is set. It is preferable to include an address calculation means for sequentially accessing each address of the storage means by sequentially increasing.

Further, the next address setting means includes reading means for reading out the stored contents of the address in response to a write pointer used for designating a predetermined address by the data writing means. After reading out the stored contents by the address setting means, it is preferable to write data in the data area of the address.

Further, the next address setting means may include address extraction means for extracting only an address value corresponding to the number of bits of the address area from the stored contents read from each address.

Further, the interleave circuit or the deinterleave circuit according to the present invention may include data input means for adding mask bits corresponding to the number of bits of the address area to each input data and supplying the data to the storage means.

On the other hand, the interleave circuit or the deinterleave circuit according to the present invention is an interleave circuit for inputting data of a predetermined array and rearranging the array and outputting the data, or a deinterleave circuit for rearranging the rearranged data to the original array. In a circuit, a storage means having a buffer area at least n times (n is an integer of 2 or more) of a cycle of a data array to be rearranged,
Storage means in which a data area in which data is written and an address area in which an address value indicating an address at which data to be read next when data written in the data area is written are previously written are formed; Data writing means for sequentially accessing respective addresses for each buffer area and writing data to be sequentially input to the data area, and reading data written in the storage means in a different order from the writing order in the data writing means. Data reading means for sequentially accessing at least a buffer area different from the buffer area accessed by the data writing means to read data; and a data reading means for storing data at an address accessed by the data reading means. Detects the address value in the address area and Characterized in that it comprises a next address setting means for setting a value in the data reading means as the next address.

In this case, the address value written in advance in the address area is such that the address value indicating the address next to the address accessed last in each buffer area is accessed first in the next buffer area. Indicates the address, the remaining address values are the address values indicating the addresses in the buffer area, and in the data reading means, the address value of the address accessed first in an arbitrary buffer area is preset as an initial address. It is advantageous to have

In this case, the address value indicating the address in the buffer area may be an address value indicating the address in the column direction of the data array in the buffer area.

The address value indicating an address in the buffer area may be an address value indicating an arbitrary different address of a data array in the buffer area.

In these cases, the data writing means uses the minimum address value of a buffer area different from the buffer area in which at least the initial address accessed by the data reading means is set as an initial address, and sequentially addresses in the buffer area. To write data sequentially in the row direction of the data array.

Further, the interleave circuit or the deinterleave circuit according to the present invention receives the storage contents of the respective addresses read by the data reading means, extracts the data from the contents, and outputs the data as the original number of bits. It is preferable to include data output means.

[0025]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of an interleave circuit and a deinterleave circuit according to the present invention; FIG. 1 shows an embodiment of an interleave circuit according to the present invention. The interleave circuit in the present embodiment is applied to, for example, a transmission circuit of a digital cellular phone and transmits coded data such as an audio signal coded by a predetermined coding method including an error correction code. In addition, a crossing circuit for rearranging the data array to increase the error correction capability is provided. For example, a code having an error correction capability L and a code length n is interlaced m times (L, m, n are natural numbers) to obtain a code length mn. , An encoding circuit that generates a code sequence having an error correction capability mL.

In particular, the interleave circuit of the present embodiment has a memory in which at least two buffer areas in which m data of code length n are arranged are formed, and the data is rearranged in the memory. Then, an address value indicating an address to which data is to be written next is stored in a predetermined area of each address of each buffer area in advance, and data is written by following each address value and writing data. The point of rearrangement is the main feature point.

More specifically, as shown in FIG. 1, the interleave circuit in the present embodiment includes a memory 100, a data input unit 102, a write control unit 104, and a next address setting unit 106.
And a read control unit 108 and a data output unit 110.
The memory 100 is a storage circuit such as a random access memory (RAM) that can write and read data at an arbitrary address. In this embodiment, at least two or more buffer areas capable of storing (n × m) data are formed. Storage circuit having the required capacity. Specifically, the memory 102 according to the present embodiment
Has, for example, 2N (N is m × n) addresses, and a first buffer area for rearranging an m × n data array is formed at addresses 0 to (N−1); A second buffer area for rearranging the data of the same array is formed at addresses (.about. (2N-1)).

Each address is assigned to a data area A having a predetermined number of bits to which data is written, and an address area B to which an address value of an address to which data is to be written next is written in advance. Specifically, in the memory 100 of the present embodiment, each address is formed, for example, in word units, 6 bits are assigned to the data area A, and the address area B
Are assigned 10 bits.

In this embodiment, each address value written to the address area B is sequentially stored in the buffer area except for the address value written to the last accessed address in each buffer area. This is a value indicating the address in the column direction of the array. At the last accessed address of the first buffer area, an address value indicating the first accessed address of the second buffer area is written, and at the last accessed address of the second buffer area, Is written with an address value indicating the first accessed address of the first buffer area. More specifically, when data of an 8 × 10 array is written to the memory 100 in a write order of 1 to 80 as shown in FIG. 2, for example, as shown in FIG. Is written with an address value indicating the next write destination address. For example, the first buffer area C
Then, "8" indicating the address value of the next write destination address is written at address 0 in the first row and first column, "16" indicating the address of the next row is written at address 8, and so on. The address values of "24", "32", "40", ... are written in the column direction, and the start address of the next column is located at the last row of the first column, that is, at address 72 in the tenth row. "1" is written to indicate that 2
Similarly, an address value “9”, “17”, “25”... Indicating the next address is written in the column direction, and an address indicating the start address of the third column at the end of the column. The value "2" has been written. Similarly, in the third to eighth columns, 36 in the fifth column
Except for the address value written at the address, the address value indicating the address in the column direction is written in each column, and the address value indicating the start address of the next column is written at the end address of each column. . However, "0" indicating the address of address 0 is written in the last row of the last column, that is, address 80, and is accessed at the end of the first buffer area C.
At address 36 in the fifth row of the column, "124" indicating the address accessed first in the second buffer area D is written. Similarly, an address value indicating the next address in the column direction is written to each address of the second buffer area D, and the first buffer area is accessed at address 116 in the fifth column, 15th row. "44" indicating the address accessed at the beginning of C is written.

Returning to FIG. 1, the data input unit 102 is an input circuit that serially inputs data encoded by a predetermined encoding method and sequentially supplies the data to the memory 100. In this embodiment, the data input unit 102 receives the input data. It includes a register 112 of a predetermined number of bits for temporarily storing and outputting. More specifically, the register 112 according to the present embodiment includes a latch circuit formed in word units similarly to the respective addresses of the memory 100, and includes a first area E into which input data is written as shown in FIG. And a second area F for masking each bit of the area.
This is a data supply circuit that supplies 0. Specifically, the second
In the area F, for example, a value of all "1" is written in advance in a binary number, and the value is multiplied by the address value read from each address of the memory 100 to obtain the first value. Memory with data written in area E
Supply 100.

The write control section 104 is a control signal generating circuit for generating a write pointer 114 for writing data from the data input section 102 to each address of the memory 100. In this embodiment, the write control section 104 has a first address as an initial address. A predetermined address value of the buffer area is set in advance,
Hereinafter, the access circuit accesses each address of the memory 100 in accordance with the address value set by the next address setting means 106. Incidentally, in the data array shown in FIG. 3, the address value of address 44 in the sixth row and the fifth column accessed first is previously set as the initial address. More specifically, the write pointer 114 includes a first enable signal for reading an address area and a second enable signal for writing data. When the first enable signal is supplied to the memory 100, the write pointer 114 receives the address. Is read out by the next address setting unit 106, and the second
, The data from the data input unit 102 is written to the address. At this time, the write control unit
104 supplies a timing signal to the data input unit 102.

The next address setting unit 106 includes the write control unit 10
4 is an address detection circuit that receives the content value from the address accessed in step 4 and extracts the address value of that address area. In this embodiment, for example, the content value from each address is temporarily stored and the data area is It includes a register 116 for reading out the upper few bits corresponding to A by masking. The read address value is supplied to the data input unit 102 and the write control unit 104, respectively.

On the other hand, the read control unit 108 is a control signal generation circuit for generating a read pointer 118 for sequentially reading data written at each address of the memory 100. In this embodiment, the read control unit 108 is set in the write control unit 104. And an address operation circuit for setting an initial address indicating a minimum address of a buffer area different from the buffer area including the set initial address and sequentially incrementing the address value. Incidentally, in the data array shown in FIG.
The address at address 80 in the column is set as the initial address, and a read pointer for reading data sequentially from the address in the row direction is generated. When the data at the final address is read, the read pointer returns to address 0 and a read pointer for sequentially reading the data in the first buffer area in the row direction as described above is generated.

The data output unit 110 is a data extraction circuit for extracting data from the content values read from the address accessed by the read control unit 108.
In the present embodiment, a register for temporarily storing the read content value and reading the upper several bits back to the original number of bits
Including 120.

In the above configuration, the operation of the interleave circuit according to the present embodiment will be described. First, data to be rearranged is sequentially supplied to the data input section 102.
When the first data is accumulated in the first area E of the register 112, the write control unit 104 generates a write pointer 114 according to a preset initial address and accesses the memory 100. For example, by accessing address 44 of the first buffer area C shown in FIG. 3, first, a first enable signal is supplied to the address. As a result, the content value of the address 44 is read, and the value is temporarily written to the register 116 of the next address setting unit 106.

Next, the register 11 of the next address setting unit 106
6 is read from the address area F
, In this case, the value "52" is extracted and supplied to the data input unit 102 and the write control unit 104, respectively. As a result, in the data input unit 102, the register 112
Are multiplied by the address value and the mask bit in the second area F to form 16-bit data to be supplied to the memory 100 together with the data in the first area E.

Next, the write control section 104 is connected to the data input section 10.
2 and a second enable signal to an address at address 44. As a result, the data from the data input unit 102 is sequentially written to the address 44. As a result, data to be rearranged in the data area A is effectively written while the address value of the address area B at address 44 remains unchanged.

Next, when the writing of the data to the address 44 is completed, the write control unit 104 generates the next write pointer 114 in the same manner as described above in accordance with the address value "52" from the next address setting unit 106 and stores it in the memory. Supply 100. As a result, address 52 is accessed in response to the first enable signal, and its contents are sequentially read out to the next address setting unit 106. Next, similarly to the above, the next address setting unit 106 extracts an address value indicating the next address extracted from the read content values, in this case, the value “60”, and outputs the address value to the data input unit 102 and the write It is sequentially supplied to the control unit 104. As a result, masked data is formed in the data input unit 102 in the same manner as described above, and the data is written in the write control unit 10.
4 is supplied to the memory 100 in response to the timing signal, and the data is written to the address by the second enable signal for accessing the address 52 in the same manner as described above.

When the writing of data to the address 52 is completed, the write pointer is written in accordance with the address value "60" written in the address area B of that address in the same manner as described above.
114 is generated, the address at address 60 is accessed, and the address value "68" in the address area is read out in the same manner as described above, and then data is sequentially written to the address at address 60.

Similarly, according to the address value written in the address area of the previous address where the data was written, for example, in the column direction, addresses 68, 76, and then, from address 5 in the next column to 13,21 , 29..., Data is written while reading the address value indicating the next write destination address. Then, when the address reaches 80 in the last column and last row of the first buffer area C, the process returns to the first column and first row of the first buffer area C according to the address value “0” of the address area, and further, 16,24 ・ ・ ・
The data input in the same manner as described above are sequentially written to the respective addresses.

As a result, when the data is written to all the addresses in the first buffer area C and the writing of the data to the address before the initial address, for example, address 36 is completed, the data is written to the address area of that address. Data writing to the first address of the second buffer area D is started in accordance with the address value indicating the address accessed first of the second buffer area D, in this case, "124".

In the second buffer area D, similarly to the first buffer area C, data is sequentially written in the column direction in the area according to the address value written in the address area of the previous address. Go.

On the other hand, in the read control unit 108, when the write control unit 104 is activated and starts writing to the first buffer area C in accordance with the initial address "44", a preset initial address, In this case, a read pointer 118 for accessing the address of the first column and the 11th row of the second buffer area D, that is, address 80, is generated and stored in the memory.
Supply 100. To be precise, 44 from the write control unit 104
After the data writing to the address is completed, an enable signal for accessing the address is supplied to the address 80.
As a result, the content value at the address 80 is read and supplied to the register 120 of the data output unit 110.

Next, in the data output section 110, the register 120
The data is extracted from the content value stored in and output. In this case, since the data has not been written yet, the idle reading is performed. Next, when the reading of the address 80 is completed, the read control unit 108 increments the initial address, generates a read pointer 116 for accessing the address 81, and generates a read pointer 116.
Feed to 0. At this time, the data is written to the second address by the write controller 104 in the same manner as described above, and then the address at the address 81 is accessed to read the content value. Also in this case, the data output unit 110 is supplied with a content value in which no data is written, and the data is read in the same manner as described above.

Hereinafter, the read control unit 108 sequentially increments the address value to 82, 83, 84,..., Accesses each address of the memory 100 in the row direction, and reads the content value. In these cases as well, the data output unit 110 continues to perform idle reading. Then, the second buffer area D
When the reading of the last address of address 159, that is, address 159, is completed, the read control unit 108 further increments the address value, and as a result, returns to the first address "0" of the first buffer area C and returns to the first buffer area C. Of the data is started.

In the first buffer area C, the read control unit 10
8 accesses the respective addresses in the row direction by sequentially incrementing the address value similarly to the second buffer area D. As a result, in the first buffer area C, the input data has already been written in the data areas of all addresses as described above, and the read data is read in response to the write pointer 118 from the read control unit 108 in the same manner as described above. The output content values of the respective addresses are successively supplied to the data output unit 110, from which the data of the data area is sequentially taken out, returned to the original number of bits, and output. As a result, the data sequentially written in the column direction in the first buffer area C is read out in the row direction, and the data array is rearranged.

On the other hand, in the second buffer area D, writing is sequentially continued in the column direction under the control of the writing control unit 104, and when writing is completed for all addresses, reading is performed at the last accessed address. In accordance with the address value, in this case, the address value “44” written at the address of the fifth column and the 15th row, the process returns to the first buffer area C again, and the respective addresses of the first buffer area C are similarly Writing of data to is continued.

At this point, the read control unit 108
After the reading of the final address of the buffer area C, that is, address 79, is completed, the address is incremented,
The data written as described above is read out at address 80, that is, in the second buffer area D again.

Similarly, the write control unit 104 sequentially accesses each address in the column direction of the data array in the buffer area in accordance with the address value written to the previously accessed address to write and read data. At 108, the address value is sequentially incremented in the other buffer area different from the buffer area accessed by the write control unit 104, and each address is accessed in the row direction of the data array to read data. As a result, the data input through the data input unit 102 is rearranged in the memory 100 in the data array, and is sequentially output from the data output unit 110.

As described above, according to the interleave circuit of the present embodiment, the data area A to which data is written and the address value indicating the write destination address of the next data are written in advance to each address of the memory 100 to which data is written. When writing data, the address value of the address area B is read out to the next address setting section 106, and the next address is sequentially set in the write control section 104 according to the address value. So
The write control unit 104 can sequentially access each address of the memory 100 without executing complicated address calculation.

In particular, when moving from the first buffer area to the second buffer area, and when moving from the second buffer area to the first buffer area,
When moving to the buffer area of the other buffer area, only the address value indicating the first accessed address is written to the last accessed address of the other buffer area in advance. And the continuous writing of data over the two areas can be performed.

In the read control unit 108 of this embodiment,
Since the write control unit 104 sequentially reads data by incrementing the address value from the initial address of the buffer area different from the buffer area of the address accessed first by the initial address, the address value is simply incremented. Only the buffer area and complicated address calculation between the buffer areas are not required.

Therefore, writing and reading of a continuous data array in two buffer areas formed in one memory 100 can be performed smoothly without imposing a load on the respective control units.

FIG. 5 shows an example in which the interleave circuit according to the above embodiment is applied, for example, CDMA (code division multip
An example of a transmission unit of a mobile phone of the le access type is shown. In this figure, the interleave circuit is mounted on an encoding circuit 10 as an interleave unit 14, and an audio signal or the like encoded by a predetermined encoding method including an error correction code in a frame configuration unit 12 at the preceding stage. Receiving the coded data, rearranging the data array, and
Supply 16 In this case, the interleave circuit 14 rearranges and arranges the arrangement of each bit of the encoded data. The spread modulation unit 16 performs convolutional coding on the data sequence rearranged by the interleave circuit 14, further performs spread modulation using a spread code or the like, and supplies the result to a radio frequency (RF) unit 18. The high-frequency unit 18 converts the spread-modulated signal into a high-frequency signal and transmits the signal from the antenna 20.

FIG. 6 shows an embodiment of the deinterleave circuit according to the present invention. The deinterleave circuit according to the present embodiment is, for example, a reverse crossover circuit that rearranges the data sequence rearranged by the interleave circuit of the above-described embodiment into the original arrangement. For example, like the interleave circuit 14 of FIG. This is applied to the decoding circuit 26 of the receiving section of the mobile phone shown in FIG. In FIG. 6, the same parts as those in the above embodiment are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 6 is different from the above embodiment in that
A point at which the write control unit 200 sequentially accesses the respective addresses of the memory 100 to sequentially write data from the data input unit 102 in the row direction of the data array in the memory 100, and at that time, An address value extraction unit 20 that reads an address value and returns it to the data input unit 102 so that the content value of the address area does not change.
2 and the next address setting unit 204 is provided on the read side of the memory 100, and the read control unit 206 writes the next address from the next address setting unit 204 to the address area of each address of the memory 100 in advance. In that each address of the memory 100 is sequentially accessed in accordance with the address value indicating the address of the memory 100.

More specifically, the write control unit 200
This is a control signal generation circuit that generates a write pointer 210 for sequentially accessing each address of 0. In the present embodiment, the start address of the first buffer area, that is, address 0, is set as the initial address, and the address is set to 0. Includes an address operation unit that increments sequentially.

The address value extraction unit 202
A circuit for reading the contents of the address accessed at 0, extracting an address value previously written in the address area from the contents, and supplying it to the data input unit 102.

The next address setting unit 204 is provided with the read control unit 20
Reference numeral 6 denotes an address extraction circuit for extracting an address value from the content value of the accessed address. In this embodiment, the extracted address value is set in the read control unit 206 as a read destination address of the next data.

The read control unit 206 includes the next address setting unit 20
4 is a control signal generating circuit for generating a read pointer 212 for accessing each address of the memory 100 in accordance with the address value from the address 4. In the present embodiment, an address initially accessed in the second buffer area as an initial address, For example, in the example shown in FIG. 3, "144" indicating the address of the fifth column and the 16th row is set in advance.

In such a configuration, first, when the first data is supplied to the data input unit 102, the write control unit
200 generates a write pointer 210 according to a preset initial address and accesses the memory 100. Thereby, for example, in the example shown in FIG. 3, address 0 of the first buffer area C is accessed, and the first data is written to the data area. To be more precise, similarly to the above embodiment, first, the first enable signal is supplied to the address by the write pointer 210, the content value is read out to the address value extracting section 202, and the address value is read from the content value. The value is extracted and supplied to the data input unit 102. As a result, the data input unit 102 forms 16-bit data masked by the address value in the same manner as in the above-described embodiment, and supplies the data formed by the timing signal in response to the second enable signal to the memory 100.

Next, the write controller 200 increments the initial address and supplies the memory 100 with a write pointer 210 for accessing address 1, for example. As a result, the data from the data input unit 102 is written to address 1.

Similarly, the write control unit 200 sequentially increments the address value, sequentially accesses the addresses 2, 3, 4,... In the memory 100, and sequentially arranges the data from the data input unit 102 into a data array. Is written in the row direction.

On the other hand, in the read control unit 206, after the write control unit 200 writes data to the initial address 0, the address 124 specified by the initial address accessed first in the second buffer area D is used. Is supplied to the memory 100. This allows
The content value of the address is read and the data output unit 11
0 and supplied to the next address setting unit 204. In the data output unit 110, the idle reading is performed as in the above embodiment. The next address setting unit 204 extracts an address value, in this case, "132" from the read content values, and sets the value in the read control unit 206.

Next, when the reading of the data at the address of address 124 is completed, the read control unit 206 sets
A read pointer for accessing the address at address 132 is generated and supplied to the memory 100. As a result, the content value of the address is supplied to the data output unit 110 and the next address setting unit 204 in the same manner as described above, and the output of data and the setting of the next address are executed. However, the output of data is a value "0" output or discarded by blank reading.

Similarly, according to the address value previously written in the address area of the accessed address,
Reading is sequentially performed in the column direction. When the reading of all data in the second buffer area D is completed, the process proceeds to reading data in the first buffer area C according to, for example, the address value “44” written in the last accessed address. At this time, in the first buffer area C, each data is written to all the addresses, for example, in the same arrangement as the data arrangement rearranged by the interleave circuit as shown in FIG. That is, the 36th data of the original array is written at address 0, and the 46th, 56th, 66th,... Data are sequentially written in the row direction.

Therefore, the read control unit 206 first accesses the address "44" in accordance with the address value read from the previous address and reads its content value.
The second data is read. As a result, the content value at address 44 including the data is supplied to the data output unit 110, and the original data is extracted from the content value and output.

On the other hand, the next address setting section 204 extracts the next address value "52" from the content value of the address 44 and sets it in the read control section 206 in the same manner as described above. Accordingly, when the read control unit 206 accesses the address and reads the content value, the second data of the original array is read.

Similarly, the read control unit 206 sequentially accesses the respective addresses in the column direction according to the address values read by the next address setting unit 204, and returns the order of the original array rearranged by the interleave circuit. The content value including the data is read out from the memory 100 and supplied to the data output unit 110. As a result, the data of the original array is output from the data output unit 110 and supplied to, for example, the next-stage frame reconstructing unit 30 shown in FIG.

In FIG. 7, a data sequence in a convolutionally coded state is supplied to the deinterleave circuit 28 of this embodiment. More specifically, for example, a high-frequency signal transmitted from the transmission unit of the mobile phone shown in FIG.
Is received by the high-frequency unit 22 via the. The high frequency section 22 converts the high frequency signal into a baseband signal and supplies the baseband signal to the despreading section 24. The despreading unit 24 despreads the baseband signal from the high-frequency unit 22 with the same spreading code as the spreading code spread by the spreading modulation unit 16 of the transmitting unit, and converts the original convolutionally encoded data sequence. The extracted data is supplied to the deinterleave circuit 28. For example, if the rate of the convolutional code is 1/2, each bit from the interleave circuit 14 of the transmission unit becomes 2-bit 1-symbol data, and if the rate is 1/3, 3-bit 1-symbol data It is affiliated. Therefore, the data supplied from the despreading unit 24 to the deinterleave circuit 28 is a plurality of bits of data. In this embodiment, for example, 3-bit data is stored in the first area of the data input unit 102. Is written to the 6-bit data area A of the memory 100,
Further, the data is read out together with the value of the address area and supplied to the data output unit 110. Thereby, the data output unit 110
Extracts the original 3-bit data from the 16-bit content value and supplies it to the frame reconstruction unit 30. Frame reconstruction unit
At 30, for example, 1-bit data is decoded from 3-bit data by Viterbi decoding, and error correction is performed to reconstruct the original frame.

As described above, according to the deinterleave circuit of this embodiment, when the data of each address of the memory 100 sequentially written by the write control unit 200 is read out, the same as the interleave circuit of the above embodiment. Since the data is read in accordance with the previously written address value, the data can be rearranged into the original array and read effectively without performing a complicated address operation in the read control unit 206.

In particular, by accessing each address in accordance with the previously written address value in the same manner as in the above-described embodiment, continuous access is made over two areas between the first buffer area and the second buffer area. Data can be smoothly read out. At the same time, since the write control section 200 merely increments the address value, complicated address calculation is not required in each buffer area and between buffer areas.
Therefore, writing and reading of a continuous data array in two buffer areas formed in one memory 100 can be smoothly performed without imposing a burden on the respective control units.

In each of the above embodiments, an interleave circuit for writing input data in the column direction of the data array in the memory 100 and reading it out in the row direction and a deinterleave circuit for writing data in the row direction of the data array and reading it out in the column direction are provided. Although each example has been described, in the present invention, the deinterleave circuit of the above embodiment may be an interleave circuit, and the interleave circuit may be a deinterleave circuit.

Further, in each of the above embodiments, the case where the present invention is applied to a CDMA mobile phone has been described as an example. However, in the present invention, any data for transmitting data via a communication path in which a burst error may occur is provided in the present invention. The present invention may be applied to a digital transceiver.

Furthermore, in each of the above embodiments, an interleave circuit and a deinterleave circuit for rearranging and interlacing data in the column direction have been described as an example. However, in the present invention, any arbitrary interleaving method may be used. . For example, it includes one that is rearranged in the oblique direction of the data array, or one that is rearranged randomly at different positions. In this case, in the prior art, access to the memory is further complicated, and the program of the write control unit or the read control unit is complicated. However, according to the present invention, the next address according to the array is previously stored in the memory. Are written, so that there is almost no burden on the respective write control unit and read control unit.

In the deinterleave circuit of the above embodiment, the content value read from each address is directly
The next address is supplied to the next address setting unit 204 to set the next address. For example, an address value indicating the next address is extracted from the content value of each address read out to the data input unit 102 and the read control unit 206 You may make it set.

Further, in each of the above embodiments, each address is configured in word units. However, if the data sequence has a small number of bits and a small data arrangement, another access configuration such as byte unit may be used.

[0078]

As described above, according to the present invention, the address value of the address to be accessed next is written in advance to each address of the memory, and data writing or reading is sequentially performed according to the address value.
The predetermined data array can be effectively rearranged without imposing a load on the write control means or the read control means for accessing each address of the memory.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of an interleave circuit according to the present invention.

FIG. 2 is a diagram showing an example of a data array rearrangement order applied to the interleave circuit according to the embodiment of FIG. 1;

FIG. 3 is a diagram showing an example of an array of address values previously written in a memory applied to the interleave circuit according to the embodiment of FIG. 1;

FIG. 4 is a diagram illustrating an example of a register configuration of a data input unit applied to the interleave circuit according to the embodiment of FIG. 1;

FIG. 5 is a block diagram illustrating an example of a transmission unit of a mobile phone to which the interleave circuit according to the embodiment of FIG. 1 is applied;

FIG. 6 is a block diagram showing one embodiment of a deinterleave circuit according to the present invention.

7 is a block diagram illustrating an example of a receiving unit of a mobile phone to which the deinterleave circuit according to the embodiment of FIG. 6 is applied;

[Explanation of symbols]

 100 Memory 102 Data input unit 104,200 Write control unit 106,204 Next address setting unit 108,206 Read control unit 110 Data output unit

Claims (16)

[Claims] 1. An interleave circuit for inputting data of a predetermined array, rearranging the array, and outputting the rearranged data, the circuit includes at least n times (n times the period of a data array to be rearranged).
Is an integer greater than or equal to 2) buffer area, and for each address, a data area in which data is written and an address area in which an address value indicating the destination of the next data is written in advance are formed. Data writing means for writing data to be sequentially input to the data area of each address of the storage means, and when writing data by the data writing means, the data is written to the address area of the accessed address. A next address setting means for reading an address value stored in the memory and sequentially setting the address value in the data writing means; and reading data written in the storage means in an order different from a writing order in the data writing means. Data reading means, wherein at least the data writing means has access Interleaving circuit, characterized in that it comprises a data reading means for reading the data sequentially accessing different buffer region and the buffer region has. 2. The interleave circuit according to claim 1, wherein the address value previously written in the address area is an address value indicating an address next to an address accessed last in each buffer area. Indicates an address value of an address accessed first in the buffer area, and all remaining address values are address values indicating addresses in the buffer area. The address value of the address to be accessed is previously set as an initial address, and the addresses of the respective buffer areas are sequentially accessed in response to the address value from the storage means set by the next address setting means thereafter. An interleave circuit. 3. The interleave circuit according to claim 2, wherein the address value indicating an address in the buffer area is an address value indicating an address in a column direction of a data array in the buffer area. Interleave circuit. 4. The interleave circuit according to claim 2, wherein the address value indicating an address in the buffer area is an address value indicating an arbitrary different address of a data array in the buffer area. Characteristic interleave circuit. 5. The interleave circuit according to claim 3, wherein said data read means sets a minimum address value of a buffer area different from a buffer area in which at least an initial address accessed by said data write means is set. An interleave circuit comprising address calculation means for sequentially accessing each address of said storage means by sequentially increasing an address in said buffer area as an initial address. 6. The interleave circuit according to claim 1, wherein said next address setting means responds to a write pointer used when designating a predetermined address by said data writing means, and stores contents of the address. An interleave circuit including read means for reading, wherein the data writing means writes data to a data area of the address after reading the stored content by the next address setting means. 7. The interleave circuit according to claim 6, wherein said next address setting means includes an address extracting means for extracting only an address value corresponding to the number of bits of an address area from stored contents read from each address. An interleave circuit characterized by including. 8. The interleave circuit according to claim 1, wherein the circuit includes a data input unit that adds a mask bit corresponding to the number of bits of an address area to each input data and supplies the data to the storage unit. An interleave circuit characterized by including. 9. An interleave circuit for inputting data of a predetermined array, rearranging the array, and outputting the rearranged data, the circuit comprises at least n times (n times the period of the data array to be rearranged)
Is an integer of 2 or more). The storage means has a data area to which data is written and data to be read next after reading data written in the data area for each address. Means for forming an address area in which an address value indicating the assigned address is previously written, and data for sequentially accessing each address for each buffer area of the storage means and writing data to be sequentially input to the data area Writing means; and data reading means for reading data written in the storage means in an order different from the writing order in the data writing means, which is different from at least a buffer area accessed by the data writing means. Data reading means for sequentially accessing a buffer area and reading data And a next address setting means for detecting an address value of an address area from the stored contents of the address accessed by the data reading means, and setting the value as the next address in the data reading means. Interleave circuit. 10. The interleave circuit according to claim 9, wherein the address value previously written in the address area is an address value indicating an address next to an address accessed last in each buffer area. Indicates an address to be accessed first in the buffer area, and the remaining address value is an address value indicating an address in the buffer area. The data reading means is accessed first in an arbitrary buffer area. A deinterleave circuit characterized in that an address value of an address is preset as an initial address. 11. The interleave circuit according to claim 10, wherein the address value indicating an address in the buffer area is an address value indicating an address in a column direction of a data array in the buffer area. And an interleave circuit. 12. The interleave circuit according to claim 10, wherein the address value indicating an address in the buffer area is an address value indicating a different arbitrary address of a data array in the buffer area. Characteristic interleave circuit. 13. The interleave circuit according to claim 11, wherein said data writing means sets a minimum address value of a buffer area different from a buffer area in which an initial address accessed by said data reading means is set. An interleave circuit characterized by sequentially accessing addresses in a buffer area as an initial address and sequentially writing data in a row direction of a data array. 14. The interleave circuit according to claim 9, wherein said circuit receives the storage contents of each address read by said data reading means, extracts data from them, and calculates the original number of bits. An interleave circuit including data output means for outputting as data. 15. A deinterleave circuit for rearranging data rearranged by the interleave circuit according to any one of claims 1 to 8 into an original array.
15. A deinterleave circuit, which is the circuit according to claim 9. 16. A deinterleave circuit for rearranging data rearranged by the interleave circuit according to any one of claims 9 to 14 into an original array, wherein said circuit is any one of claims 1 to 8. A deinterleave circuit, which is a circuit according to any one of claims 1 to 3.