JPH1188117A - Filter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit scale and also to save power consumption by adding the input signals of the same multiplier by means of a capacitance coupled adding circuit and multiplying the multiplier by means of plural multiplying input capacitors which are selectively connected to the output of the addition result. SOLUTION: The input signals X((N+1)T) are inputted to plural sample-and- hold circuits SHO-SHN which are serially connected in a filter circuit. The respective sample-and-hold circuits hold the input signals sequentially and data of X((N-i)T) is held in the (i+1)-th sample-and-hold circuit SHi . When N is an odd number, X(iT) and X((N-i)T) are multiplied by the same multiplier. When N is an odd number, a multiplying circuit Mi is provided in accordance with SHi and SH( N-i) , data of the same multiplier is inputted to the same multiplying circuit, the total sum of the outputs is calculated by an adding circuit Σ and a level is adjusted by a scaler circuit SC.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a linear phase FIR filter circuit.

[0002]

2. Description of the Related Art Digital technology in computer science has been remarkably developed with the advance of microfabrication technology, but the amount of capital investment is increasing at an accelerating rate, and at present analog technology and analog / digital mixed technology are being developed. Is attracting attention. Therefore, the applicant has proposed a filter circuit that uses an analog voltage as an input signal and filters the analog voltage as it is (Japanese Patent Laid-Open No. 06-1643).
No. 21, etc.), and good results were obtained with respect to the circuit scale and power consumption.

However, there is a high demand for such a filter circuit to be further downsized and to save power.

[0004]

SUMMARY OF THE INVENTION The present invention has been made under such a background, and an object of the present invention is to provide a linear phase FIR filter circuit having a smaller circuit size and lower power consumption. .

[0005]

The filter circuit according to the present invention focuses on the symmetry of the multiplier of the linear phase FIR filter,
A configuration in which an input signal having the same multiplier is added by an adder circuit composed of capacitive coupling, an output of the addition result is multiplied by a multiplier by a plurality of multiplication input capacitances selectively connected, and a multiplier of the multiplication input capacitance is multiplied. Is a simplified version of (Reference: Hiroshi Ochi, “Digital
Introduction to Filter Design ", CQ Publishing, January 20, 1991
Second edition issued)

[0006]

Next, a linear phase FIR according to the present invention will be described.
An embodiment of the filter circuit will be described with reference to the drawings.

[0007]

FIG. 1 is a circuit diagram showing an embodiment of a filter circuit according to the present invention, in which an input signal X ((N + 1) T) comprising an analog input voltage is supplied to a plurality of sample-and-hold circuits SH0 connected in series. To SHN. Each sample and hold circuit holds the input signal in time series, and (i
In the (+1) th sample hold circuit SHi, X
The data of ((N−i) T) is held. According to the characteristic of the linear phase FIR filter, when N is an odd number, X
(IT) and X ((N−i) T) are multiplied by the same multiplier. When N is an even number, only X (N / 2) is a single multiplier, and the other cases are the same as in the case of an even number. FIG. 1 shows a case where N is an odd number. Multiplication circuits Mi are provided corresponding to SHi and SH (N−i), and data of the same multiplier is input to the same multiplication circuit. The sum of the outputs of these multiplication circuits is calculated by the addition circuit Σ, and the level is adjusted by the scaler circuit SC.

In FIG. 3, the sample and hold circuit SH0 includes a switch S31 connected to an input voltage Vi3.
, The sample hold timing is set, and the output timing of the voltage held in the subsequent switch S32 is set. The switch 31 is connected to a first input capacitance C31. The switch C31 is connected to an inverter circuit INV31 shown in detail in FIG.
1 are connected by a feedback capacitance Co31. C31 and Co31 are set to the same capacity, and when S31 is closed, INV31 produces the output Vo3 'of equation (1). As shown in the equation, the output is V
equal to the inverse of i3. These Vo3 ′ and Vi3 are V
The voltage is based on dd / 2.

(Equation 1) The output of INV31 is input to a second input capacitance C32 via a switch S32, and the output of C32 is INV31.
31 is connected to the same inverter circuit INV32 as
The input and output of the NV32 are connected by a feedback capacitance Co32. If C32 = Co32, then S
In the closed state of No. 32, the output of INV32, that is, the output of the sample-and-hold circuit SH0, is as shown in equation (2).

(Equation 2)

The sample-and-hold circuit SH0 is configured so that S31 is closed for a sufficient time so that the charge corresponding to Vi3 becomes C3.
1. When S31 is held at Co31, S31 is opened, then S32 is closed, and the charge corresponding to Vo3 'is transferred to C32,
It is held by Co32. By transferring the charge in this manner, a change in Vi3 is prevented from affecting Vo3, and Vi3 can be held and output with good accuracy. Note that the other sample and hold circuits are configured in the same manner as SH0, and thus description thereof is omitted.

FIG. 2 shows inverter circuits INV31 and INV.
32 (indicated by the reference numeral INV). The inverter circuit INV includes a three-stage CMOS inverter I2
1, I22 and I23 are connected in series, and a phase compensation circuit composed of a series circuit of a resistance RP and a capacitance CP is connected to the input and output of I22. The inverter circuit outputs the inverted input with good linear characteristics due to the effect of the high gain by the product of the gain of each CMOS inverter and the feedback capacitance. Further, the phase compensation circuit prevents oscillation in a high-gain feedback system.

In FIG. 4, a multiplication circuit M1 includes an adder ADD to which a pair of input voltages Vi41 and Vi42 are input,
Assuming that the output of the ADD is composed of the input multiplier MUL and the multiplier in the multiplier is m, MUL is (Vi41 + V
i42) × m is output. As described above, the addition of data to be multiplied by the same multiplier is performed in advance, thereby simplifying the configuration of the multiplication unit, and reducing the circuit scale and power consumption of the entire filter circuit. Note that the other multiplication circuits are configured in the same manner as M1, and thus description thereof is omitted.

In FIG. 5, an adder ADD has an input voltage V
i51 and Vi52 (corresponding to the above-mentioned Vi41 and Vi42) are connected to each other and the input capacitance C51 for addition,
C52, and outputs of these capacitances are connected to the inverter circuit INV5 while being integrated. INV
5 is connected to its input by the addition feedback capacitance Co5, and the capacitance of each capacitance is C51 =
C52 = Co5 / 2 is set. INV5 is shown in FIG.
And the output V of INV5
o5 is as in equation (3).

(Equation 3) From equation (3), the output of the adder is the average of both input voltages,
The addition result is normalized.

In FIG. 6, a multiplying unit MUL has an input voltage V
i6 (corresponding to the output of the adder ADD) has a plurality of switches S61 to S68 that can be connected, and the outputs of S61 to S68 are connected to the input capacitances C61 to C68 for multiplication, respectively. The input side of the switches S61 to S68 is Vi
6 or a reference voltage Vref, and an input voltage or a reference voltage is applied to C61 to C68. C61 to C68 each have a capacity corresponding to a power of 2, and each of the switches S61 to S68 is controlled by a control signal corresponding to the multiplier m. The outputs of C61 to C68 are connected to the inverter circuit INV6 while being integrated,
The output of INV6 is connected to its input via multiplication feedback capacitance Co6. Here, each bit of the binary number corresponding to the multiplier m is represented by bm0 to bm7 (bm7 is MSB
And ), And the capacity of C61 to C68 is

[Outside 1] And Co6 becomes

[Outside 2] , The multiplier output Vo6 is as shown in Expression (4).

(Equation 4)

In FIG. 7, the adder circuit Σ includes positive multiplier input capacitances C7p1 to C7pN / 2-1 and negative multiplier input capacitances C7m1 to C7mN / 2-1 corresponding to the multiplier circuits M1 to MN / 2-1. The outputs of the multiplication circuits M1 to MN / 2-1 are input to these input capacitances. Here, when the multiplier of the multiplier Mi is positive, the output of the multiplier is input to the input capacitor C7pi for the positive multiplier, and the reference voltage is input to C7mi. Therefore, a switch (not shown) that is switched by the sign bit of the multiplier is connected to each input capacitance.

The capacitances C7p1 to C7pN / 2-1 have the same inverter circuit INV as described above while their outputs are integrated.
The output of INV71 is connected to its input by a feedback capacitance Co71. The capacitances C7m1 to C7mN / 2-1 are connected to the same inverter circuit INV72 as described above while the outputs are integrated.
The output of NV72 is connected to its input by feedback capacitance Co72. Where C7p1 = C7p2
=. . . = C7pN / 2-1 = C7m1 = C7m2 =. . .
= C7mN / 2-1 = CC / (N / 2-1) = Co71, C
o72 = 2CC, and the output Vo7 of the adder circuit Σ is as shown in Expression (5).

(Equation 5) Here, if the input capacitance such as C7p1 is simply represented by C, equation (5) is simplified as equation (6).

(Equation 6)

As is apparent from the above, the addition circuit of FIG. 7 has a problem that CC and Co72 increase as N increases, but the configuration of FIG. 8 can suppress this increase in capacity. 8 is connected to the inverter circuit INV81 while integrating the outputs of the positive multiplier input capacitances C8p1 to C8pN / 2-1, and is connected to the inverter circuit INV81 while integrating the negative multiplier input capacitances C8m1 to C8mN / 2-1. It is connected to INV82, and the outputs of INV81 and INV82 are connected to its inputs via feedback capacitances Co81 and Co82. The output of INV81 is input to the inverter circuit INV83 via the capacitance CC1, and the output of INV83 is connected to the input via the feedback capacitance Co83. INV82, INV
The outputs of 83 are connected to the capacitances CC3 and CC2, respectively, and the outputs of these capacitances are input to the inverter circuit INV84 while being integrated. INV8
4 is connected to its input via a feedback capacitance Co84.

Here, C8p1 = C8p2 =. . . = C8
pN / 2-1 = C8m1 = C8m2 =. . . = C8mN / 2-1 =
Co81 / (N / 2-1) = Co82 / (N / 2−
1), Co83 = CC1, CC2 = CC3, Co84 =
CC2 + CC3, and the output Vo8 of the adder circuit な る is as shown in equation (7).

(Equation 7)

In equations (6) and (7), the output is normalized so as not to exceed a predetermined level. However, the output level is adjusted by the scaler circuit SC, and the level of other data is adjusted. Matching and other operations are performed.

In FIG. 9, the scaler circuit SC has switches S911 to S91n to which an input voltage Vi9 (corresponding to the output of the adder circuit Σ) can be connected. ing. The input sides of the switches S911 to S91n can be connected to Vi9 or the reference voltage Vref, and the input voltage or the reference voltage is applied to C911 to C91n. The outputs of C911 to C91n are connected to an inverter circuit INV9 while being integrated, and INV9
Can be connected to a plurality of switches S921 to S92n. The outputs of the switches S921 to S92n are connected to the INV9 output or the reference voltage Vref, and the inputs thereof are
INV9 via the capacitances C921 to C92n.
Connected to the input. C911-C91n, C92
1 to C92n have a capacity corresponding to a power of 2, and S9
11 to S91n and S921 to S92n are controlled by control signals A and B, respectively. The control signals A, B comprise a corresponding binary number of capacitance values, each bit of which is a1, a2,. . . , An, b1, b
2,. . . , Bn. Each switch is closed when the corresponding bit is "1" and opened when the corresponding bit is "0". Here, assuming that the output of the scaler circuit SC is Vo9,
Vo9 is expressed as in equation (7).

(Equation 8)

The reference voltage Vref is set to Vdd / 2 when the power supply voltage of the CMOS inverter is Vdd, and a maximum dynamic range is secured in both the positive and negative directions around this reference voltage.

As described above, since all of the sample-and-hold circuit, the multiplication circuit, the addition circuit, and the scaler circuit are constituted by voltage-driven analog circuits, the overall circuit configuration is simple and small, and the power consumption is small. . And
By simplifying the multiplication circuit, further miniaturization and power saving are achieved.

[0022]

As described above, the filter circuit according to the present invention pays attention to the symmetry of the multiplier of the linear phase FIR filter,
A configuration in which an input signal having the same multiplier is added by an adder circuit composed of capacitive coupling, an output of the addition result is multiplied by a multiplier by a plurality of multiplication input capacitances selectively connected, and a multiplier of the multiplication input capacitance is multiplied. Is simplified, so that there is an excellent effect that the circuit scale is smaller than before and the power consumption is small.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a filter circuit according to the present invention.

FIG. 2 is a circuit diagram showing an inverter circuit in the embodiment.

FIG. 3 is a circuit diagram showing a sample and hold circuit in the embodiment.

FIG. 4 is a block diagram illustrating a multiplication circuit according to the embodiment.

FIG. 5 is a circuit diagram showing an addition unit in the multiplication circuit of the embodiment.

FIG. 6 is a circuit diagram showing a multiplication unit in the multiplication circuit of the embodiment.

FIG. 7 is a circuit diagram showing an adding circuit of the embodiment.

FIG. 8 is a circuit diagram showing a modification of the adding circuit.

FIG. 9 is a circuit diagram showing a scaler circuit of the same embodiment.

[Explanation of symbols]

SH0 to SHN. . . Sample hold circuit M0 to MN / 2-1. . . Multiplication circuit II. . . Adder circuit SC. . . Scaler circuit INV, INV31, INV32, INV5, INV
6, INV71, INV72, INV81 to INV84, INV9. . . Inverter circuit RP. . . Resistance CC, CP. . . Capacitance C31, C32, C61-C68, C7p1-C7pN /
2-1, C7m1 to C7mN / 2-1, C8p1 to C8pn, C
8m1 to C8mn. . . Input capacitance Co31, Co32, Co5, Co6, Co71, Co
72, C81-C84, C911-C91n, C921
~ C92n. . . Feedback capacitance ADD. . . Adder MUL. . . Multiplication unit S31, S32, S61 to S68, S911 to S91
n, S921 to S92n. . . switch. 1 Reference number = YZ19707029A

Claims (1)

[Claims] 1. A plurality of sample-and-hold circuits for holding an input signal in the form of an analog input voltage in time series; a plurality of multiplication circuits for multiplying the input signal held by these sample-and-hold circuits by a predetermined multiplier; An adder circuit for calculating the sum of the outputs of the circuits, wherein each of the multipliers receives an input signal to be multiplied by a symmetric multiplier. A pair of input capacitances for addition having the same capacity; an addition inverter circuit composed of odd-numbered series CMOS inverters connected in an integrated manner with outputs of these input capacitances; and an output of the inverter circuit connected to its input. An addition unit having a feedback capacitance for addition; and a plurality of multiplications of a capacity corresponding to the weight of each bit of a binary number An input capacitance for multiplication; an inverter circuit for multiplication composed of CMOS inverters in odd-numbered stages connected together while integrating the outputs of the input capacitance for multiplier; and an input of the input capacitance for multiplication to the output of the adder or a reference voltage. A multiplier with a plurality of switches to be connected;
A filter circuit comprising: