JPH1187698A - Semiconductor device having high breakdown strength and power converter employing the same - Google Patents

Semiconductor device having high breakdown strength and power converter employing the same

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Publication number
JPH1187698A
JPH1187698A JP9237511A JP23751197A JPH1187698A JP H1187698 A JPH1187698 A JP H1187698A JP 9237511 A JP9237511 A JP 9237511A JP 23751197 A JP23751197 A JP 23751197A JP H1187698 A JPH1187698 A JP H1187698A
Authority
JP
Japan
Prior art keywords
semiconductor layer
layer
semiconductor
conductivity type
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9237511A
Other languages
Japanese (ja)
Inventor
Katsunori Asano
勝則 浅野
Yoshitaka Sugawara
良孝 菅原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kansai Electric Power Co Inc
Hitachi Ltd
Original Assignee
Kansai Electric Power Co Inc
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kansai Electric Power Co Inc, Hitachi Ltd filed Critical Kansai Electric Power Co Inc
Priority to JP9237511A priority Critical patent/JPH1187698A/en
Publication of JPH1187698A publication Critical patent/JPH1187698A/en
Pending legal-status Critical Current

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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    • H01L29/0692—Surface layout
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PROBLEM TO BE SOLVED: To enhance breakdown strength by making a plurality of trenches while surrounding a main junction and forming a termination part having a semiconductor layer of conductivity type different from that of a drift layer in the drift layer on the bottom of each trench thereby avoiding concentration of field to the vicinity of main junction. SOLUTION: An n<-> drift layer 6 is formed on an SIC substrate 7 and a source electrode 12, a trench gate 10, or the like, are formed in the n<-> drift layer 6. A main junction 1 is formed between a P<+> body layer 5 and the n<-> drift layer 6. A termination part 39 comprising trenches 9, or the like, is then formed while surrounding the main junction 1. A P<+> layer is formed on the bottom of the trench 9 by ion implantation. An n<-> layer 4 is formed on a P<+> layer 3 between trenches 9 adjacent to a P<+> layer 2. When a higher voltage is applied to a drain electrode 11 than the source electrode 12, a depletion layer 30 spreads into the n<-> layer 4 on the periphery of an active region 1A and the field of the main junction 1 is relaxed at the end of the active region 1A.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、高耐圧半導体装置
及びこれを用いた電力変換器に関する。The present invention relates to a high-voltage semiconductor device and a power converter using the same.

【０００２】[0002]

【従来の技術】大容量の電力変換を行うための高耐圧半
導体装置としては、シリコンを素子材料として用いた高
耐圧・大電流のための構造が採用されてきたが、高耐圧
半導体装置のさらなる小型化および低ロス化のために
は、シリコンの物性限界を越える新たな材料による半導
体装置の開発が望まれていた。シリコンの物性限界をは
るかに越える材料として、シリコンカーバイド（以下Ｓ
ｉＣと表記する）やダイヤモンドなどがあり、これら材
料の臨界電界は、シリコンのものの１０倍以上であり非
常に大きい。このため、半導体装置のドリフト層の厚み
を約１０分の１以下にすることができるとともに、キャ
リア濃度を１０倍以上にできる。その結果として電気抵
抗を約１００分の１以下にできるので、これらの材料を
用いた半導体装置は大幅な低ロス化が実現できるものと
して期待されている。しかし、ＳｉＣ等の高臨界電界材
料で形成した半導体装置では、オフ状態の半導体装置の
内部において、シリコンの半導体装置の１０倍以上の高
い電界が生じるため、電界集中による破壊が起きやす
い。そこで電界を効果的に緩和するために設けるターミ
ネーション部の構造が重要となる。「ターミネーション
部」とは、半導体装置の主接合部近傍の電界集中を緩和
するために主接合部の周囲に設けた種々の半導体層をい
う。2. Description of the Related Art A high-breakdown-voltage and large-current structure using silicon as an element material has been adopted as a high-breakdown-voltage semiconductor device for performing large-capacity power conversion. In order to reduce the size and reduce the loss, it has been desired to develop a semiconductor device using a new material that exceeds the physical properties of silicon. Silicon carbide (hereinafter referred to as S) is a material far exceeding the physical limit of silicon.
iC), diamond, and the like, and the critical electric field of these materials is 10 times or more that of silicon, which is very large. For this reason, the thickness of the drift layer of the semiconductor device can be reduced to about 1/10 or less, and the carrier concentration can be increased to 10 times or more. As a result, the electric resistance can be reduced to about 1/100 or less, so that a semiconductor device using these materials is expected to be able to realize a significant reduction in loss. However, in a semiconductor device formed of a high critical electric field material such as SiC, an electric field that is higher than that of a silicon semiconductor device by 10 times or more is generated inside a semiconductor device in an off state, and thus breakdown due to electric field concentration is likely to occur. Therefore, the structure of the termination portion provided to effectively reduce the electric field is important. “Termination section” refers to various semiconductor layers provided around the main junction to reduce electric field concentration near the main junction of the semiconductor device.

【０００３】一般にシリコンの半導体装置では、高耐圧
を得るために、ＪＴＥ（Junction Termination Extenti
on）、ＦＬＲ（Field Limitting Ring）やＦＭＲ（Floa
tingMetal Rings）等のターミネーション部を設けるタ
ーミネーション技術を用いている。これらのターミネー
ション部は半導体チップの周辺部に、主接合部を取り囲
むように形成されており、主接合端部の電界を緩和す
る。[0003] In general, in a silicon semiconductor device, in order to obtain a high breakdown voltage, a junction termination extension (JTE) is required.
on), FLR (Field Limiting Ring) and FMR (Floa
Termination technology for providing a termination portion such as tingMetal Rings) is used. These termination portions are formed in the peripheral portion of the semiconductor chip so as to surround the main junction, and reduce the electric field at the end of the main junction.

【０００４】[0004]

【発明が解決しようとする課題】ＳｉＣ等の高臨界電界
材料で高耐圧半導体装置を製作する場合、主接合端部の
電界を緩和する前記従来のターミネーション技術は適し
ていない。その理由は、上記のターミネーション技術で
はドリフト層に広がる空乏層の幅が小さく、十分に電界
を緩和できないためである。In the case of manufacturing a high breakdown voltage semiconductor device using a high critical electric field material such as SiC, the above-mentioned conventional termination technique for relaxing the electric field at the main junction end is not suitable. The reason is that the width of the depletion layer spreading over the drift layer is small in the above-mentioned termination technology, and the electric field cannot be sufficiently reduced.

【０００５】図１３はＪＴＥによるターミネーション部
を有する半導体装置の断面図である。この半導体装置の
場合、主接合部５の端部周辺にＪＴＥ領域１８を形成
し、高電圧印加時にはＪＴＥ領域１８内の全体に空乏層
１９を拡げることにより、主接合部５の外周方向におい
てもｎ-ドリフト層６の深さ方向に空乏層１９を拡げ、
主接合部５の端部の電界を緩和する。ＪＴＥ領域１８を
高濃度にすると、空乏層１９はｎ-ドリフト層６内に拡
がるがＪＴＥ領域の端部の空乏層１９の幅は小さくな
る。また、ＪＴＥ領域１８を低濃度にしすぎると、空乏
層１９は拡がらず、主接合部５の端部の電界が高くな
り、耐圧が低下する。このため、空乏層１９の幅をＪＴ
Ｅ領域１８一杯に拡げて高耐圧を達成しようとすると、
ＪＴＥ領域１８の濃度依存特性が急峻となり、高耐圧を
達成できる最適許容濃度の幅がきわめて狭く、イオン打
ち込み等の高精度な濃度制御技術を用いても製作できな
い。FIG. 13 is a cross-sectional view of a semiconductor device having a JTE termination unit. In the case of this semiconductor device, the JTE region 18 is formed around the end of the main junction 5, and the depletion layer 19 is spread over the entire JTE region 18 when a high voltage is applied. The depletion layer 19 is expanded in the depth direction of the n - drift layer 6,
The electric field at the end of the main junction 5 is reduced. When the JTE region 18 has a high concentration, the depletion layer 19 spreads in the n − drift layer 6, but the width of the depletion layer 19 at the end of the JTE region is reduced. If the concentration of the JTE region 18 is too low, the depletion layer 19 does not expand, the electric field at the end of the main junction 5 increases, and the breakdown voltage decreases. Therefore, the width of the depletion layer 19 is set to JT
When trying to achieve a high withstand voltage by expanding the E region 18 fully,
The JTE region 18 has a sharp concentration-dependent characteristic, and the width of the optimum allowable concentration for achieving a high withstand voltage is extremely narrow, so that it cannot be manufactured even by using a high-accuracy concentration control technique such as ion implantation.

【０００６】図１４はＦＬＲによるターミネーション部
を有する半導体装置の断面図である。この半導体装置で
はターミネーション部として複数のＦＬＲ層２０を用い
て空乏層２１をＦＬＲ層２０間のドリフト層６内に拡げ
ている。空乏層２１をＦＬＲ層２０内一杯には拡げなく
てすむので、ＦＬＲ層２０を一定濃度以上の高濃度にす
ればよく、実現しやすい。しかし、複数のターミネーシ
ョン用ＦＬＲ層２０を並列配置して用いるので、専有面
積が大きくなってしまう。すなわち複数のＦＬＲ層２０
を活性領域５の外周を取り囲むように形成するので、そ
の幅は狭くても大きな面積を占有する。そのため、半導
体装置の限られた面積において、ＦＬＲ層２０の面積に
相当する分だけ活性領域５の面積を減らさざるを得ず電
流容量の減少やオン抵抗の増大を招くという点で問題が
ある。FIG. 14 is a cross-sectional view of a semiconductor device having an FLR termination section. In this semiconductor device, the depletion layer 21 is extended into the drift layer 6 between the FLR layers 20 by using a plurality of FLR layers 20 as termination portions. Since the depletion layer 21 does not need to be fully extended in the FLR layer 20, the FLR layer 20 has only to have a high concentration of a certain concentration or more, which is easy to realize. However, since a plurality of termination FLR layers 20 are used in parallel, the occupied area increases. That is, the plurality of FLR layers 20
Is formed so as to surround the outer periphery of the active region 5, and therefore occupies a large area even if its width is small. Therefore, in a limited area of the semiconductor device, there is a problem in that the area of the active region 5 has to be reduced by an amount corresponding to the area of the FLR layer 20, which leads to a reduction in current capacity and an increase in on-resistance.

【０００７】上記のように高耐圧半導体装置を実現する
ためには、効果的に電界を緩和するターミネーション構
造が必要であるが、ＳｉＣなどの高臨界電界材料の半導
体装置では、ターミネーション部を形成するために超高
精度の濃度制御技術が必要であった。また、ターミネー
ション部のために大きな専有面積が必要である。In order to realize a high breakdown voltage semiconductor device as described above, a termination structure for effectively relaxing an electric field is required. In a semiconductor device made of a high critical electric field material such as SiC, a termination portion is formed. Therefore, ultra-high-precision concentration control technology was required. In addition, a large occupation area is required for the termination unit.

【０００８】本発明は超高精度の濃度制御技術を必要と
せず、かつ占有面積の少ないターミネーション構造を有
する高耐圧半導体装置を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a high breakdown voltage semiconductor device which does not require an ultra-high-precision concentration control technique and has a termination structure occupying a small area.

【０００９】[0009]

【課題を解決するための手段】上記課題を解決するため
に、本発明の第１モードの高耐圧半導体装置では、主接
合部の周囲を取り囲むように複数の溝（以下トレンチと
称する）を形成し、各トレンチ底部のドリフト層内に前
記ドリフト層の導電型と異なる導電型の半導体層を有す
るターミネーション部を形成している。これによってト
レンチ底部の半導体層とトレンチ間の半導体層の間に空
乏層が拡がって電界を緩和するため主接合部近傍の電界
集中が避けられ半導体装置の耐圧が向上する。In order to solve the above-mentioned problems, in the first mode high breakdown voltage semiconductor device of the present invention, a plurality of grooves (hereinafter referred to as trenches) are formed so as to surround the periphery of the main junction. Then, a termination portion having a semiconductor layer of a conductivity type different from the conductivity type of the drift layer is formed in the drift layer at the bottom of each trench. As a result, the depletion layer expands between the semiconductor layer at the bottom of the trench and the semiconductor layer between the trenches to reduce the electric field, so that electric field concentration near the main junction is avoided and the breakdown voltage of the semiconductor device is improved.

【００１０】本発明の第２モードの高耐圧半導体装置で
は、主接合部の周囲を取り囲むように複数のトレンチを
ドリフト層内に形成し、各トレンチの底部にショットキ
ー接合（以下ショットキーコンタクトと称する）を形成
させるための導電層を設けている。この導電層の電界効
果によってドリフト層内に空乏層が拡がり、電界を緩和
するので、主接合部近傍の電界集中が避けられ半導体装
置の耐圧が向上する。In the second mode high breakdown voltage semiconductor device of the present invention, a plurality of trenches are formed in the drift layer so as to surround the main junction, and a Schottky junction (hereinafter referred to as a Schottky contact) is formed at the bottom of each trench. ) Is formed. The depletion layer expands in the drift layer due to the electric field effect of the conductive layer, and the electric field is alleviated. Therefore, electric field concentration near the main junction is avoided, and the withstand voltage of the semiconductor device is improved.

【００１１】本発明の上記第１及び第２モードの半導体
装置では、オフ時に高電圧が印加された場合に、主にト
レンチ底部とトレンチ間のドリフト層に空乏層を拡げて
電界を緩和する。空乏層をトレンチ底部とトレンチ間の
ターミネーション用半導体層内にはほとんど拡げなくて
すむので、一定濃度以上の高濃度にしさえすればよく、
濃度制御に特別の高精度が必要でなく製造が容易であ
る。In the first and second mode semiconductor devices according to the present invention, when a high voltage is applied when the semiconductor device is turned off, the electric field is relaxed mainly by expanding the depletion layer in the drift layer between the trench bottom and the trench. Since the depletion layer hardly spreads in the semiconductor layer for termination between the bottom of the trench and the trench, it is sufficient to make the concentration higher than a certain level.
Special high precision is not required for density control, and manufacturing is easy.

【００１２】また、トレンチ間のドリフト層はトレンチ
壁に沿って半導体装置の深さ方向に形成されるので、半
導体装置の表面部分を占有することはなく、ターミネー
ション部による占有面積を最小限に抑えることができ
る。その結果半導体装置のオン時に負荷電流が流れる活
性領域の面積を大きくすることができ、電流容量の増大
とオン抵抗の低減を達成できる。Since the drift layer between the trenches is formed along the trench walls in the depth direction of the semiconductor device, the drift layer does not occupy the surface of the semiconductor device, and the area occupied by the termination portion is minimized. be able to. As a result, the area of the active region through which the load current flows when the semiconductor device is turned on can be increased, so that the current capacity can be increased and the on-resistance can be reduced.

【００１３】本発明の電力変換器は、スイッチング素子
として前記第１モード又は第２モードの高耐圧半導体装
置を用いた電力変換装置である。本発明の高耐圧半導体
装置の特徴の高い耐電圧、大きな電流容量、低いオン抵
抗により、高耐圧、大電流かつ低損失の電力変換器が実
現できる。A power converter according to the present invention is a power converter using the first mode or second mode high breakdown voltage semiconductor device as a switching element. The high withstand voltage, large current capacity, and low on-resistance characteristic of the high withstand voltage semiconductor device of the present invention can realize a high withstand voltage, large current, and low loss power converter.

【００１４】[0014]

【発明の実施の形態】以下、本発明の半導体装置の実施
例を図１ないし図１０を参照しながら詳細に説明する。 《第１実施例》本発明の第１実施例を図１ないし図３を
参照して説明する。図１は、本発明の第１の実施例の、
等間隔のトレンチ型ターミネーション部を設けたトレン
チ型ＭＯＳＦＥＴの平面図であり、図２は図１のII−II
断面図である。図１及び図２において、トレンチ型ター
ミネーション部３９は、主接合部１を取り囲むように環
状に形成されている。この半導体装置の具体例における
各部の寸法は以下のとおりである。ｎ-ドリフト層６の
厚さは５０μｍ、ｎ+ドレイン層７の厚さは３００μｍ
である。ｐ+ボディ層５の厚さは２．５μｍであり、ｐ+
ボディ層５に設けられているｎ+ソース層の接合深さは
０．５μｍである。各トレンチ９の深さおよび幅は４μ
ｍである。ゲート絶縁物層３５の厚さはトレンチ底部で
１μｍ、トレンチ側面で０．１μｍである。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the semiconductor device according to the present invention will be described below in detail with reference to FIGS. << First Embodiment >> A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a first embodiment of the present invention.
FIG. 2 is a plan view of a trench MOSFET provided with equally spaced trench termination portions, and FIG. 2 is a II-II of FIG.
It is sectional drawing. In FIGS. 1 and 2, the trench type termination portion 39 is formed in an annular shape so as to surround the main junction 1. The dimensions of each part in the specific example of this semiconductor device are as follows. The thickness of n − drift layer 6 is 50 μm, and the thickness of n + drain layer 7 is 300 μm
It is. The thickness of p + body layer 5 is 2.5 μm, and p +
The junction depth of the n + source layer provided in body layer 5 is 0.5 μm. Each trench 9 has a depth and width of 4 μm.
m. The thickness of the gate insulator layer 35 is 1 μm at the bottom of the trench and 0.1 μm at the side of the trench.

【００１５】ターミネーション部３９のトレンチ９の底
面および側面の絶縁物層３６の厚さは１μｍである。タ
ーミネーション部３９の隣り合うトレンチ９の間隔は４
μｍである。なお、トレンチゲート１０の底面および側
面の絶縁物層３５の厚さは、ともに０．４μｍ程度の厚
さでも良い。また、主接合部１の面とトレンチ９の底面
の距離は、４μｍ以下であればよいが、望ましくは１．
５μｍ以下がよい。本実施例では、ゲート電極１３はス
トライプ状であるが、その形状は例えば円形や四角形等
であってもかまわない。またゲート電極１３は、例えば
１０個以上のストライプ状のものでもかまわない。The thickness of the insulating layer 36 on the bottom and side surfaces of the trench 9 in the termination portion 39 is 1 μm. The interval between the adjacent trenches 9 of the termination portion 39 is 4
μm. The thickness of the insulator layer 35 on the bottom and side surfaces of the trench gate 10 may be about 0.4 μm. The distance between the surface of the main junction 1 and the bottom of the trench 9 may be 4 μm or less.
5 μm or less is preferred. In this embodiment, the gate electrode 13 has a stripe shape, but the shape may be, for example, a circle or a square. The gate electrode 13 may be, for example, 10 or more stripes.

【００１６】本実施例の半導体装置の製作工程は、次の
とおりである。最初にドレイン層７として機能する１０
18から１０20atm/cm3の不純物濃度のｎ+形ＳｉＣ（炭化
珪素）基板を用意し、この一方の表面に１０14から１０
16atm/cm3の不純物濃度のＳｉＣのｎ-ドリフト層６を気
相成長法等により形成する。次にｎ-ドリフト層６の上
に１０16から１０18atm/cm3程度の不純物濃度のＳｉＣ
のｐ+層を気相成長法等により形成する。そして、１０
18atm/cm3程度の不純物濃度のｎ+領域を窒素、りん等の
イオン打ち込み法等により所望の領域に選択的に形成す
る。次に、上記の工程を経た基板を異方性エッチングし
て、ｐ+層を貫通し底部がｎ-ドリフト層６内に所定距離
進入するトレンチゲート１０及びターミネーション部３
９用のトレンチ（溝）９を形成する。次にトレンチ９の
底から深さ０．５μmの範囲に、１０16から１０18atm/c
m3程度の不純物濃度のｐ+層２をホウ素、アルミニウム
等のイオン打ち込み等により形成する。続いて、トレン
チゲート１０の内壁およびターミネーション部３９用ト
レンチ９の内壁にＳｉＯ2の絶縁物層３５、３６を形成
する。トレンチゲート１０の内壁の絶縁物層３５は、厚
さ０．１μｍ程度であるが、ターミネーション部３９用
トレンチ９の内壁の絶縁物層の厚さは、０．５から１μ
ｍと厚くてもよい。その後トレンチ部９及びトレンチゲ
ート１０内には、りんを高濃度に含んだポリシリコンを
堆積して埋め込む。次に、トレンチゲート１０内のポリ
シリコンを残し、他の部分のポリシリコンを除去し、ゲ
ート電極１３を形成する。最後に、アルミニウム、ニッ
ケル等でｐ+層５の表面にソース電極１２を形成する。
また基板のドレイン層７の表面にドレイン電極１１を形
成して完成する。なお、ｐ+層３及び５はエピタキシャ
ル法で形成したが、イオン打ち込み法を用いても形成で
きる。The manufacturing process of the semiconductor device according to the present embodiment is as follows. First, 10 functioning as the drain layer 7
An n + -type SiC (silicon carbide) substrate having an impurity concentration of 18 to 10 20 atm / cm 3 is prepared, and 10 14 to 10 10
An n - drift layer 6 of SiC having an impurity concentration of 16 atm / cm 3 is formed by a vapor phase growth method or the like. Next, SiC having an impurity concentration of about 10 16 to 10 18 atm / cm 3 is formed on the n − drift layer 6.
A p + layer is formed by vapor deposition or the like. And 10
An n + region having an impurity concentration of about 18 atm / cm 3 is selectively formed in a desired region by ion implantation of nitrogen, phosphorus, or the like. Next, the substrate having undergone the above-described steps is subjected to anisotropic etching, so that the trench gate 10 and the termination portion 3 penetrate the p + layer and enter the n − drift layer 6 at a predetermined distance from the bottom.
A trench 9 for 9 is formed. Next, in the range of 0.5 μm in depth from the bottom of the trench 9, 10 16 to 10 18 atm / c
The p + layer 2 having an impurity concentration of about m 3 is formed by ion implantation of boron, aluminum, or the like. Subsequently, insulator layers 35 and 36 of SiO 2 are formed on the inner wall of the trench gate 10 and the inner wall of the trench 9 for the termination portion 39. The thickness of the insulating layer 35 on the inner wall of the trench gate 10 is about 0.1 μm, and the thickness of the insulating layer on the inner wall of the trench 9 for the termination portion 39 is 0.5 to 1 μm.
m. Thereafter, polysilicon containing a high concentration of phosphorus is deposited and buried in the trench portion 9 and the trench gate 10. Next, the polysilicon in the trench gate 10 is left, and the polysilicon in the other portions is removed to form the gate electrode 13. Finally, a source electrode 12 is formed on the surface of the p + layer 5 using aluminum, nickel, or the like.
The drain electrode 11 is formed on the surface of the drain layer 7 of the substrate to complete the process. Although the p + layers 3 and 5 are formed by an epitaxial method, they can be formed by an ion implantation method.

【００１７】本発明の特徴の構造と動作原理について以
下に詳細に述べる。構造の特徴の第一として、ＦＬＲと
して用いているｐ+層２がトレンチ９の底部にあり、か
つｐ+層３が隣接するトレンチ９の間にある。第二にト
レンチ９の底部のｐ+層２と隣接するトレンチ９の間の
ｐ+層３の間には一定の間隔があり、その間にトレンチ
間ｎ-層４がある。The structure and principle of operation of the features of the present invention will be described in detail below. The first of the structural features is that the p + layer 2 used as the FLR is at the bottom of the trench 9 and the p + layer 3 is between the adjacent trenches 9. Second, there is a certain distance between the p + layer 2 at the bottom of the trench 9 and the p + layer 3 between the adjacent trenches 9, between which there is an inter-trench n − layer 4.

【００１８】上記の構造を有する半導体装置のドレイン
電極１１に、ソース電極１２より高い電圧を印加する
と、点線で示す空乏層３０は、ｐ+ボディ層５とｎ-ドリ
フト層６の間の主接合部１からドレイン電極１１および
ソース電極１２の方向に広がり電圧を阻止する。活性領
域１Ａの周辺では、空乏層３０が主にトレンチ底部ｐ+
層２とトレンチ間ｐ+層３間のトレンチ間ｎ-層４に拡が
り、活性領域１Ａの端部の主接合部１の電界を緩和す
る。この時、空乏層３０をトレンチ底部ｐ+層２とトレ
ンチ間ｐ+層３内にはほとんど拡げなくてすむので、ト
レンチ底部ｐ+層２とトレンチ間ｐ+層３の不純物濃度を
１０16atm/cm3以上の高濃度にしさえすればよく、濃度
を精密に制御する必要はない。このように濃度制御技術
の精度が低くてよいので製造が容易であり実現しやす
い。また、トレンチ間ｎ-層４はトレンチ９の壁面に沿
ってドリフト層６の深さ方向（半導体装置の表面に垂直
な方向）の、トレンチ間ｐ+層３とトレンチ底部ｐ+層２
との間に形成されるので、表面積の増加に影響を与える
ことはない。従って半導体装置の限られた表面積におい
て、トレンチ間ｎ-層４の深さ方向の寸法に相当する分
だけ活性領域１Ａの面積を大きくでき、電流容量の増大
やオン抵抗の低減を達成できる。さらに、ＭＯＳＦＥＴ
の活性領域１Ａにトレンチゲート１０を形成する時、同
時にターミネーション部３９用のトレンチ９を形成でき
るので、プロセスを簡略化できる。さらに、トレンチ９
及びトレンチゲート１０の内部をポリシリコンやＳｉＯ
2等で埋めることにより、半導体装置の表面の汚染を防
止することができ高い信頼性を実現できる。When a voltage higher than that of the source electrode 12 is applied to the drain electrode 11 of the semiconductor device having the above structure, the depletion layer 30 indicated by a dotted line becomes a main junction between the p + body layer 5 and the n − drift layer 6. The voltage spreads from the portion 1 toward the drain electrode 11 and the source electrode 12 to prevent a voltage. In the vicinity of the active region 1A, the depletion layer 30 is mainly formed at the trench bottom p +
It extends to the n − layer 4 between the trenches between the layer 2 and the p + layer 3 between the trenches, and relaxes the electric field at the main junction 1 at the end of the active region 1A. At this time, since the depletion layer 30 need not almost spread on the trench bottom p + layer 2 and the trenches between p + layer 3, 10 16 atm impurity concentration of the trench bottom p + layer 2 and the trenches between p + layer 3 It is sufficient that the concentration be as high as / cm 3 or more, and there is no need to precisely control the concentration. As described above, since the accuracy of the concentration control technique may be low, manufacturing is easy and easy to realize. Moreover, inter-trench n - layer 4 is the depth direction of the drift layer 6 along the wall surface of the trench 9 (the direction perpendicular to the surface of the semiconductor device), a trench between p + layer 3 and the trench bottom p + layer 2
And does not affect the increase in surface area. Therefore, in the limited surface area of the semiconductor device, the area of active region 1A can be increased by an amount corresponding to the dimension in the depth direction of n − layer 4 between the trenches, and the current capacity can be increased and the on-resistance can be reduced. In addition, MOSFET
When the trench gate 10 is formed in the active region 1A, the trench 9 for the termination portion 39 can be formed at the same time, so that the process can be simplified. Furthermore, trench 9
And the inside of the trench gate 10 is made of polysilicon or SiO.
By filling with 2 or the like, contamination of the surface of the semiconductor device can be prevented, and high reliability can be realized.

【００１９】本実施例のトレンチ型ターミネーション部
３９の各部の寸法の一例を図３の（ａ）に示す。また、
この半導体装置と同程度の耐圧を持つ従来の半導体装置
のＦＬＲ付ＭＯＳＦＥＴのターミネーション部の寸法を
図３の（ｂ）に示す。図３の（ａ）においてトレンチ底
部ｐ+層２とトレンチ間ｐ+層３の水平方向の寸法はそれ
ぞれ２μｍであり、合計寸法は４μｍである。これに対
して図３の（ｂ）においては、２個のｐ+層２Ａ、２Ｂ
の水平方向の寸法はそれぞれ２μｍであり合計寸法は４
μｍである。２個のｐ+層２Ａと２Ｂの間のｎ-層４Ｂの
距離は１μｍであり、ｐ+層２Ａとｐ+ボディ層５との間
のｎ-層４Ａの距離は１μｍである。従って合計寸法は
６μｍである。本実施例のターミネーション部３９で
は、図３の（ｂ）におけるｎ-層４Ａ及び４Ｂに対応す
るトレンチ間ｎ-層４が、ドリフト層６の深さ方向のト
レンチ間ｐ+層３とトレンチ底部ｐ+層の間に形成される
ことになり、トレンチ間ｎ-層４がターミネーション部
３９の面積の増大に無関係となるので、その分従来のも
のに比べて表面積が減少する。その結果本実施例のター
ミネーション部３９の面積は、従来技術のＦＬＲの場合
に比べ、３分の２の面積になり、同一サイズの半導体装
置ではその分活性領域１Ａの面積を大きくできるので電
流容量の増大やオン抵抗の低減を達成できる。FIG. 3A shows an example of the dimensions of each part of the trench termination portion 39 of this embodiment. Also,
FIG. 3B shows the dimensions of the termination portion of the MOSFET with FLR of the conventional semiconductor device having the same breakdown voltage as this semiconductor device. In FIG. 3A, the horizontal dimension of each of the trench bottom p + layer 2 and the inter-trench p + layer 3 is 2 μm, and the total dimension is 4 μm. On the other hand, in FIG. 3B, two p + layers 2A, 2B
Have a horizontal dimension of 2 μm each and a total dimension of 4 μm.
μm. The distance of n − layer 4B between two p + layers 2A and 2B is 1 μm, and the distance of n − layer 4A between p + layer 2A and p + body layer 5 is 1 μm. Therefore, the total size is 6 μm. In the termination section 39 of this embodiment, the n − layer 4 between the trenches corresponding to the n − layers 4A and 4B in FIG. 3B is formed between the p + layer 3 between the trenches in the depth direction of the drift layer 6 and the bottom of the trench. would be formed between the p + layer, trench between n - because the layer 4 is irrelevant to the increase in the area of the termination section 39, the surface area is reduced as compared with the correspondingly conventional. As a result, the area of the termination portion 39 of this embodiment is two-third the area of the FLR of the prior art, and the semiconductor device of the same size can increase the area of the active region 1A by that much. And an on-resistance can be reduced.

【００２０】本実施例では、図１に示すように３個のト
レンチ型ターミネーション部３９を有する半導体装置を
例に挙げたが、さらに多数のトレンチ型ターミネーショ
ン部３９を設けることにより更なる高耐圧を実現でき
る。例えば、３個のトレンチを有するターミネーション
部３９を設けた場合の４８００Ｖの耐圧が、５個のトレ
ンチを有するターミネーション部３９を設けたものでは
５３００Ｖに上昇した。本実施例ではトレンチ底部ｐ+
層２とトレンチ間ｐ+層３とはほとんど同一不純物濃度
にしてプロセスを簡略化したが、これらの不純物濃度を
個々にかえることによりＭＯＳＦＥＴのオン特性と耐圧
をそれぞれ独立して改善できるので更なる高性能化が図
れる。また複数のトレンチ底部ｐ+層２の不純物濃度を
それぞれ所定の値にし、かつ複数のトレンチ間ｐ+層３
の不純物濃度をそれぞれ所定の値にすることにより、オ
ン特性と耐圧を更に改善することができる。例えば、ト
レンチ底部ｐ+層２の不純物濃度を３×１０17atm/cm3、
トレンチ間ｐ+層３の不純物濃度を１０18atm/cm3とした
場合には、耐圧は４８００Ｖと変わらないが、オン抵抗
を３５ｍΩｃｍ2から２８ｍΩｃｍ2に低減できた。さら
に、複数のトレンチ底部ｐ+層２及びトレンチ間ｐ+層３
の不純物濃度について、それぞれの最内周のものの不純
物濃度を最も高くし、それより外周にあるものは不純物
濃度が外周へ向かって順次漸減するように形成してもよ
い。例えば、ターミネーション部３９に１０個のトレン
チ９を設けた場合に、最内周のトレンチ９のトレンチ底
部ｐ+層２及びトレンチ間ｐ+層３の不純物濃度を１０19
atm/cm3とし、それより外周の９個のトレンチ９のトレ
ンチ底部ｐ+層２及びトレンチ間ｐ+層３を、不純物濃度
が５×１０18から１０16atm/cm3に順次漸減するように
形成した。 それに加えてｎ-ドリフト層６の厚さを１５
０μｍ、不純物濃度を１０14atm/cm3としたとき、耐圧
を２０ＫＶに上昇させることができた。In this embodiment, a semiconductor device having three trench-type termination portions 39 as shown in FIG. 1 has been described as an example. However, by providing a larger number of trench-type termination portions 39, a higher withstand voltage can be obtained. realizable. For example, the withstand voltage of 4800 V when the termination portion 39 having three trenches is provided increases to 5300 V in the case where the termination portion 39 having five trenches is provided. In this embodiment, the trench bottom part p +
Although the layer 2 and the p + layer 3 between the trenches have almost the same impurity concentration to simplify the process, the on-state characteristics and the breakdown voltage of the MOSFET can be independently improved by changing these impurity concentrations individually. High performance can be achieved. Further, the impurity concentration of the plurality of trench bottom p + layers 2 is set to a predetermined value, and the plurality of trench p + layers 3
The on-characteristics and breakdown voltage can be further improved by setting the impurity concentration of each of them to a predetermined value. For example, the impurity concentration of the trench bottom p + layer 2 is set to 3 × 10 17 atm / cm 3 ,
When the impurity concentration of the trenches between p + layer 3 and 10 18 atm / cm 3, the breakdown voltage does not change and 4800V, could reduce the on-resistance from 35Emuomegacm 2 to 28mΩcm 2. Furthermore, a plurality of trench bottom p + layers 2 and inter-trench p + layers 3
May be formed such that the impurity concentration at the innermost periphery is the highest, and those at the outer periphery are gradually reduced toward the outer periphery. For example, when ten trenches 9 are provided in the termination portion 39, the impurity concentration of the trench bottom p + layer 2 and the inter-trench p + layer 3 of the innermost trench 9 is set to 10 19
Atm / cm 3 , the impurity concentration of the trench bottom p + layer 2 and the inter-trench p + layer 3 of the nine trenches 9 therefrom is gradually reduced from 5 × 10 18 to 10 16 atm / cm 3. Formed. In addition, the thickness of n − drift layer 6 is set to 15
When the thickness was 0 μm and the impurity concentration was 10 14 atm / cm 3 , the breakdown voltage could be increased to 20 KV.

【００２１】 《第２実施例》図４は、本発明の第２の実
施例の半導体装置の断面図である。本実施例の半導体装
置は不等間隔のトレンチを有するターミネーション部３
９を有するトレンチ型ＭＯＳＦＥＴである。図４におい
て、活性領域１Ａに隣接する第１段目のトレンチ型ター
ミネーション部３９Ａのトレンチ９Ａの幅が他のトレン
チ９Ｂの幅より大きくなされている。またトレンチゲー
ト１０の底部にｐ+電界緩和層４０を形成している。そ
の他の構成は第１の実施例と同じであるので説明を省略
する。半導体装置が電圧を阻止する際に、第１段目の幅
の広いトレンチ９Ａの底部に形成したトレンチ底部ｐ+
層２Ａにより、空乏層を主接合部１より更に離れたとこ
ろまで拡げることができる。したがって主接合部１の端
部の電界は更に緩和され、高耐圧の半導体装置を実現で
きる。例えば、第１段目のトレンチ９Ａの幅を３０μｍ
にした時、耐圧を５８００Ｖにすることができた。その
結果、幅４μｍのトレンチ９を等間隔に形成したトレン
チ型ターミネーション部を有する半導体装置に比べ、２
５％程度耐圧を上げることができた。第１段目のトレン
チ９Ａの幅を更に拡げることにより、更なる高耐圧化が
できる。例えば、６０μｍにすると、耐圧は６０００Ｖ
と更に高耐圧化することができた。この場合のオン抵抗
は、３５ｍΩ／ｃｍ2と第１実施例のものと同等の値に
することができた。[0021] << Second Embodiment >> FIG. 4 shows a second embodiment of the present invention.
It is sectional drawing of the semiconductor device of an Example. The semiconductor device of the present embodiment
The termination part 3 having unequally spaced trenches
9 is a trench MOSFET. Figure 4
And the first trench type trench adjacent to the active region 1A.
The width of the trench 9A of the termination portion 39A is different from that of the other trenches.
The width is made larger than the width of the tip 9B. Also a trench game
P at the bottom of+An electric field relaxation layer 40 is formed. So
The other configuration is the same as that of the first embodiment, and the description is omitted.
I do. When the semiconductor device blocks the voltage, the width of the first stage
Trench bottom p formed at the bottom of wide trench 9A+
The layer 2A separates the depletion layer further from the main junction 1.
Can be extended to Therefore, the end of the main joint 1
The electric field in the part is further reduced, realizing a semiconductor device with high withstand voltage.
Wear. For example, the width of the first-stage trench 9A is 30 μm.
, The withstand voltage could be set to 5800V. That
As a result, a trench having 4 μm wide trenches 9 formed at equal intervals
2 compared to a semiconductor device having a
The withstand voltage was increased by about 5%. First stage train
By further expanding the width of the h 9A, a higher withstand voltage can be achieved.
it can. For example, when the thickness is 60 μm, the withstand voltage is 6000 V
And higher withstand voltage. ON resistance in this case
Is 35 mΩ / cmTwoAnd a value equivalent to that of the first embodiment
We were able to.

【００２２】≪第３実施例≫図５は、本発明の第３の実
施例の半導体装置の断面図である。本実施例の半導体装
置は、補助電極（フィールドプレート）１４を有する等
間隔のトレンチ型ターミネーション部を備えたトレンチ
型ＭＯＳＦＥＴである。まず、図１に示す第１実施例の
半導体装置と同様に、ターミネーション部３９のトレン
チ９の底部および側面にそれぞれＳｉＯ2等の絶縁物層
１５Ａ及び１５を形成する。次にトレンチ９の底面の絶
縁物層１５Ａに一端が接する補助電極１４を形成する。
補助電極１４の他端はトレンチ間ｐ+層３の頂部の接続
部３Ａに接触させる。補助電極１４を設けた結果、トレ
ンチ底部ｐ+層２およびトレンチ間ｐ+層３近傍の空乏層
３０が、ドレイン電極１１の方向に更に拡げられた。そ
れにつれて活性領域１Ａの外周部に空乏層が更に拡が
り、主接合部１近傍の電界が更に緩和される。その結果
第１実施例のものに比べて３５％以上耐圧が高くなっ
た。また、第１の実施例と同様に、従来のターミネーシ
ョン部に比べ、ターミネーション部の専有面積を約３分
の２に減らすことができた。Third Embodiment FIG. 5 is a sectional view of a semiconductor device according to a third embodiment of the present invention. The semiconductor device of the present embodiment is a trench MOSFET provided with equally spaced trench termination portions having auxiliary electrodes (field plates) 14. First, similarly to the semiconductor device of the first embodiment shown in FIG. 1, insulating layers 15A and 15 such as SiO 2 are formed on the bottom and side surfaces of the trench 9 of the termination portion 39, respectively. Next, an auxiliary electrode 14 having one end in contact with the insulator layer 15A on the bottom surface of the trench 9 is formed.
The other end of the auxiliary electrode 14 is brought into contact with the connection 3A at the top of the p + layer 3 between the trenches. As a result of providing the auxiliary electrode 14, the depletion layer 30 near the trench bottom p + layer 2 and the inter-trench p + layer 3 was further expanded in the direction of the drain electrode 11. As a result, the depletion layer further extends around the outer periphery of active region 1A, and the electric field near main junction 1 is further reduced. As a result, the breakdown voltage was 35% or more higher than that of the first embodiment. Also, as in the first embodiment, the area occupied by the termination portion can be reduced to about two thirds as compared with the conventional termination portion.

【００２３】≪第４実施例≫図６は、本発明の第４の実
施例の半導体装置の、補助電極１４（フィールドプレー
ト）と等間隔トレンチ型ターミネーション部３９を有す
るトレンチ型ＭＯＳＦＥＴの断面図を示す。第４の実施
例ではターミネーション部３９のトレンチ９の側面およ
びトレンチ間ｐ+層３の上面にＳｉＯ2等の絶縁物層１５
を形成する。第４の実施例は、トレンチ間ｐ+層３の上
面の絶縁物層１５に一端が接し、他端がトレンチ底部ｐ
+層２に接する補助電極１４Ａを形成した点が第３の実
施例と異なる。補助電極１４Ａをトレンチ底部ｐ+層に
接触させることにより、トレンチ９内の絶縁物層１５の
電界が緩和される。その結果第３の実施例の場合と同様
に主接合部１近傍の電界が緩和され、第１実施例のもの
に比べて３５％以上耐圧が高くなった。さらに、第１の
実施例と同様に、従来のターミネーション部と比べ、タ
ーミネーション部３９の専有面積を約３分の２に減らす
ことができた。Fourth Embodiment FIG. 6 is a sectional view of a trench MOSFET having an auxiliary electrode 14 (field plate) and an equally spaced trench termination section 39 of a semiconductor device according to a fourth embodiment of the present invention. Show. In the fourth embodiment, an insulating layer 15 such as SiO 2 is formed on the side surface of the trench 9 of the termination portion 39 and the upper surface of the p + layer 3 between the trenches.
To form In the fourth embodiment, one end is in contact with the insulator layer 15 on the upper surface of the inter-trench p + layer 3, and the other end is at the trench bottom p.
The difference from the third embodiment is that an auxiliary electrode 14A in contact with the + layer 2 is formed. By bringing the auxiliary electrode 14A into contact with the trench bottom p + layer, the electric field of the insulator layer 15 in the trench 9 is reduced. As a result, the electric field near the main junction 1 was reduced as in the case of the third embodiment, and the breakdown voltage was increased by 35% or more as compared with that of the first embodiment. Further, similarly to the first embodiment, the area occupied by the termination section 39 can be reduced to about two thirds as compared with the conventional termination section.

【００２４】《第５実施例》図７は、本発明の第５の実
施例の半導体装置の、浅い等間隔のトレンチ９を有する
ターミネーション部３９を備えるトレンチ型ＭＯＳＦＥ
Ｔの断面図である。図において、ターミネーション部３
９のトレンチ間ｎ-層４とトレンチ間ｐ+層３の接合部４
３の面の、活性領域１Ａの主表面４６からの距離が第１
の実施例のものより大きく、主接合部１の位置よりドレ
イン電極１１側に寄っている。またトレンチ間ｐ+層３
の厚さがトレンチ底部ｐ+層２より薄い点も、第１の実
施例と異なる。トレンチ間ｐ+層３が、ドレイン電極１
１に近づくことにより、空乏層３０がドレイン電極１１
の方向に向って拡がりやすくなり、その結果高耐圧の半
導体装置が実現できる。また、ターミネーション部３９
の専有面積も第１の実施例と同様に従来のものに比べて
３分の２に減らすことができる。<< Fifth Embodiment >> FIG. 7 shows a trench type MOSFE having a termination portion 39 having shallow, equally spaced trenches 9 in a semiconductor device according to a fifth embodiment of the present invention.
It is sectional drawing of T. In the figure, the termination unit 3
No. 9 junction 4 between n − layer 4 between trenches and p + layer 3 between trenches
The distance of the third surface from the main surface 46 of the active region 1A is the first.
And is closer to the drain electrode 11 side than the position of the main junction 1. In addition, p + layer 3 between trenches
Is thinner than the trench bottom p + layer 2 in the first embodiment. The p + layer 3 between the trenches is the drain electrode 1
1 so that the depletion layer 30 becomes closer to the drain electrode 11.
Therefore, a semiconductor device having a high withstand voltage can be realized. In addition, the termination section 39
Occupied area can be reduced to two thirds as compared with the conventional one as in the first embodiment.

【００２５】《第６実施例》図８は、本発明の第６の実
施例の半導体装置の、ショットキー接合（以下ショット
キーコンタクトと称する）を有するトレンチ型ターミネ
ーション部３９を備えるトレンチ型ＭＯＳＦＥＴの断面
図である。本実施例では、前記の各実施例のターミネー
ション部３９に設けたトレンチ底部ｐ+層２およびトレ
ンチ間ｐ+層３を形成せずに、金や白金等の薄膜でｎ-ド
リフト層６の表面にショットキーコンタクト１７Ａ、１
７Ｂ、１７Ｃ、１７Ｄ、１７Ｅ及び１７Ｆを形成する。
隣り合うショットキーコンタクト、例えばショットキー
コンタクト１７Ａ、１７Ｂは互いに段差を有するｎ-ド
リフト層６の上に設けられ、各ショットキーコンタクト
１７Ａないし１７Ｆは活性領域１Ａを囲むように環状に
なされている。ターミネーション部３９の最外周のフィ
ールドリミッタｎ+層１６の表面にも金や白金等でショ
ットキーコンタクト１７Ｇを形成し、ショットキーコン
タクト１７Ｇの内縁は前記フィールドリミッタｎ+層１
６の内縁よりも更に内側にくるようになされている。ト
レンチ底部のショットキーコンタクト１７Ａ、１７Ｃ、
１７Ｅおよびトレンチ間ショットキーコンタクト１７
Ｂ、１７Ｄ、１７Ｆ、１７Ｇにより、空乏層３０がドレ
イン電極１１の方向に拡がる。その結果主接合部１の近
傍の電界が緩和され、第１の実施例のものと同様の耐電
圧特性を示す。また、フィールドリミッタｎ+層１６
は、半導体装置の表面が汚染した場合でも、空乏層３０
がｎ-ドリフト層６の表面に沿って端部まで拡がること
を防ぎ、耐圧の低下を防ぐ。<< Sixth Embodiment >> FIG. 8 shows a semiconductor device according to a sixth embodiment of the present invention, which is a trench type MOSFET having a trench type termination portion 39 having a Schottky junction (hereinafter referred to as a Schottky contact). It is sectional drawing. In this embodiment, the surface of the n − drift layer 6 is formed of a thin film of gold or platinum without forming the trench bottom p + layer 2 and the inter-trench p + layer 3 provided in the termination portion 39 of each of the above embodiments. Schottky contacts 17A, 1
Form 7B, 17C, 17D, 17E and 17F.
Adjacent Schottky contacts, for example, Schottky contacts 17A and 17B are provided on n − drift layer 6 having a step, and each of Schottky contacts 17A to 17F is formed in an annular shape so as to surround active region 1A. A Schottky contact 17G is also formed of gold, platinum or the like on the surface of the field limiter n + layer 16 on the outermost periphery of the termination portion 39, and the inner edge of the Schottky contact 17G is connected to the field limiter n + layer
6 is located further inside than the inner edge. Schottky contacts 17A, 17C at the bottom of the trench,
17E and Schottky contact 17 between trenches
B, 17D, 17F, and 17G cause the depletion layer 30 to expand in the direction of the drain electrode 11. As a result, the electric field in the vicinity of the main junction 1 is alleviated, and a breakdown voltage characteristic similar to that of the first embodiment is exhibited. Also, the field limiter n + layer 16
Indicates that even if the surface of the semiconductor device is contaminated, the depletion layer 30
Does not spread along the surface of n − drift layer 6 to the end portion, thereby preventing a decrease in breakdown voltage.

【００２６】フィールドリミッタｎ+層１６の内側のシ
ョットキーコンタクト１７Ｇについては、表面に沿って
拡がってできた空乏層３０の延びをフィールドリミッタ
ｎ+層１６だけでなくショットキーコンタクト１７Ｇの
電界効果によっても抑える。これによって、フィールド
リミッタｎ+層１６で電界強度が高くなり、耐圧が低下
するのを防ぐことができる。Regarding the Schottky contact 17G inside the field limiter n + layer 16, the extension of the depletion layer 30 formed along the surface is increased by the electric field effect of the Schottky contact 17G as well as the field limiter n + layer 16. Also suppress. As a result, it is possible to prevent the electric field strength from increasing in the field limiter n + layer 16 and the breakdown voltage from lowering.

【００２７】例えば、第１の実施例と概略同じ構造諸元
の半導体装置において、表面汚染が存在した場合、耐圧
が４５００Ｖになったが、第６の実施例の半導体装置で
は４８００Ｖに保つことができた。なお、パッケイジン
グの工夫などにより、表面汚染が防止できる場合は、こ
のフィールドリミッタｎ+層１６のショットキーコンタ
クト１７Ｇを設けなくとも所期の効果を達成できること
はいうまでもない。For example, in the case of surface contamination in a semiconductor device having substantially the same structure as that of the first embodiment, the withstand voltage becomes 4500 V. However, in the semiconductor device of the sixth embodiment, the breakdown voltage is maintained at 4800 V. did it. If the surface contamination can be prevented by means of packaging, it is needless to say that the desired effect can be achieved without providing the Schottky contact 17G of the field limiter n + layer 16.

【００２８】《第７実施例》図９は、本発明の第７の実
施例の半導体装置の断面図である。第７の実施例では、
第６の実施例におけるトレンチ間ショットキーコンタク
ト１７Ｂ、１７Ｄ、１７Ｆの代わりに、イオン打ち込み
法によりトレンチ間ｐ+層５３を形成した点が、第６の
実施例と異なる。ターミネーション部３９の各トレンチ
９の側面とトレンチ間ｐ+層５３の表面には絶縁物層１
５が形成されている。トレンチ９の底面の絶縁物層１５
にはさまれた部分にそれぞれショットキーコンタクト１
７Ａ、１７Ｃ、１７Ｅが設けられている。第７の実施例
の半導体装置も第６の実施例のものと同様に、高耐圧性
を示し、ターミネーション部３９の専有面積も小さい。<< Seventh Embodiment >> FIG. 9 is a sectional view of a semiconductor device according to a seventh embodiment of the present invention. In the seventh embodiment,
The difference from the sixth embodiment is that an inter-trench p + layer 53 is formed by ion implantation instead of the inter-trench Schottky contacts 17B, 17D, 17F in the sixth embodiment. The insulator layer 1 is provided on the side surface of each trench 9 of the termination portion 39 and the surface of the p + layer 53 between the trenches.
5 are formed. Insulator layer 15 on bottom of trench 9
Schottky contacts 1 between the parts sandwiched between
7A, 17C and 17E are provided. Similarly to the semiconductor device of the sixth embodiment, the semiconductor device of the seventh embodiment also has high withstand voltage, and the area occupied by the termination portion 39 is small.

【００２９】《第８実施例》図１０は、本発明の第８の
実施例の半導体装置の断面図である。第８の実施例で
は、ターミネーション部３９のトレンチ９の底面の全面
にそれぞれショットキーコンタクト１７Ａ、１７Ｃ、１
７Ｅを形成した点が第７の実施例のものと異なる。ショ
ットキーコンタクト１７Ａ、１７Ｃ、１７Ｅをトレンチ
９の底面の全面に形成することにより、半導体装置がオ
フの時にターミネーション部３９のトレンチ９の底面端
部からも空乏層が拡がり、トレンチ９の底部の側面近傍
のトレンチ間ｎ-層４の電界がより緩和され、高耐圧化
が達成できる。<< Eighth Embodiment >> FIG. 10 is a sectional view of a semiconductor device according to an eighth embodiment of the present invention. In the eighth embodiment, the Schottky contacts 17A, 17C, 1
The point that 7E is formed is different from that of the seventh embodiment. By forming Schottky contacts 17A, 17C, and 17E on the entire bottom surface of trench 9, the depletion layer also extends from the bottom end of trench 9 in termination portion 39 when the semiconductor device is off, and the bottom side surface of trench 9 is formed. The electric field of the n − layer 4 between the adjacent trenches is further reduced, and a higher breakdown voltage can be achieved.

【００３０】本発明の前記各実施例の半導体装置におい
て、ゲートＧをソースＳに接続して、ソースＳとドレン
Ｄの２極の半導体装置すなわちダイオードとして機能さ
せることができる。このようにして構成されたダイオー
ドにおいても前記の各実施例で説明したＭＯＳＦＥＴと
同様に高耐圧化ができるとともに、低損失かつ大きな電
流容量のダイオードを得ることができる。In the semiconductor device of each of the above embodiments of the present invention, the gate G can be connected to the source S to function as a two-pole semiconductor device of the source S and the drain D, that is, a diode. Also in the diode configured in this way, a high breakdown voltage can be achieved similarly to the MOSFET described in each of the above embodiments, and a diode having low loss and large current capacity can be obtained.

【００３１】《インバータ装置》図１１は、本発明を適
用したＭＯＳＦＥＴおよびダイオードを用いて構成し
た、三相のインバータの例を示す回路図である。スイッ
チング素子としての６個のＭＯＳＦＥＴＳＷ１１、ＳＷ
１２、ＳＷ２１、ＳＷ２２、ＳＷ３１、ＳＷ３２および
ダイオードＤ１１、Ｄ１２、Ｄ２１、Ｄ２２、Ｄ３１、
Ｄ３２により直流を交流に変換する。ＭＯＳＦＥＴ Ｓ
Ｗ１１・・・ＳＷ３２は、スイッチング速度の大きなス
イッチング素子であり、このＭＯＳＦＥＴおよびダイオ
ードに本発明を適用することにより、スイッチング素子
の高耐圧化ができる。ＳｉＣを用いた従来のＭＯＳＦＥ
Ｔでは、５００Ｖ以上の高耐圧の半導体装置ではオン抵
抗が大きくなり、高耐圧インバータの高性能化が困難で
あった。本発明の各実施例による半導体装置を適用すれ
ば、高耐圧インバータ装置の高性能化、すなわちコンパ
クト化、低損失化、低雑音化を達成できる。その結果イ
ンバータ装置を用いたシステムの低コスト化、高効率化
が実現できる。<< Inverter Device >> FIG. 11 is a circuit diagram showing an example of a three-phase inverter formed by using MOSFETs and diodes to which the present invention is applied. Six MOSFETs SW11 and SW as switching elements
12, SW21, SW22, SW31, SW32 and diodes D11, D12, D21, D22, D31,
DC is converted to AC by D32. MOSFET S
SW11 are switching elements having a high switching speed. By applying the present invention to the MOSFET and the diode, the switching element can have a high withstand voltage. Conventional MOSFE using SiC
At T, the on-resistance is large in a semiconductor device having a high withstand voltage of 500 V or more, and it is difficult to improve the performance of a high withstand voltage inverter. By applying the semiconductor device according to each embodiment of the present invention, it is possible to achieve high performance of the high withstand voltage inverter device, that is, downsizing, low loss, and low noise. As a result, cost reduction and high efficiency of the system using the inverter device can be realized.

【００３２】《整流装置》図１０は、本発明を適用した
ＭＯＳＦＥＴおよびダイオードを用いて構成した、整流
装置の例を示す回路図である。ブリッジ接続した４個の
ＭＯＳＦＥＴＳＷ１１、ＳＷ１２、ＳＷ２１、ＳＷ２２
およびダイオードＤ１１、Ｄ１２、Ｄ２１、Ｄ２２によ
り交流を直流に変換する。ＭＯＳＦＥＴは、スイッチン
グ速度の大きな素子であり、この素子とダイオードに本
発明を適用することにより、高耐圧整流装置のコンパク
ト化、低損失化、低雑音化などの効果が得られる。した
がって、整流装置を用いたシステムの低コスト、高効率
化が達成できる。<< Rectifier >> FIG. 10 is a circuit diagram showing an example of a rectifier constructed using MOSFETs and diodes to which the present invention is applied. Four bridge-connected MOSFETs SW11, SW12, SW21, SW22
Further, the alternating current is converted into the direct current by the diodes D11, D12, D21 and D22. A MOSFET is an element having a high switching speed, and by applying the present invention to this element and a diode, effects such as compactness, low loss, and low noise of a high withstand voltage rectifier can be obtained. Therefore, low cost and high efficiency of the system using the rectifier can be achieved.

【００３３】以上、本発明の実施例を説明したが、本発
明はさらに多くの適用範囲あるいは派生構造をカバーす
るものである。前記の第２ないし第５、第７及び第８の
実施例において、複数のトレンチ底部ｐ+層２及びトレ
ンチ間ｐ+層３の不純物濃度について、それぞれの最内
周のものの不純物濃度を最も高くし、それより外周にあ
るものは不純物濃度が外周に向かって順次漸減するよう
に形成してもよい。また、両者の不純物濃度はそれぞれ
任意の値にしてもよい。前記の各実施例では、ＳｉＣ素
子の場合のみを述べたが、シリコン、ガリウムヒ素等の
他の半導体材料にも適用できる。特に、ダイヤモンド、
ガリウムナイトライドなどのワイドギャップ半導体材料
に有効である。前記各実施例の説明では、ドリフト層６
がｎ型の素子の場合のみを述べたが、ドリフト層６がｐ
型の素子の場合でも、ｎ型層をｐ型層に変え、ｐ型層を
ｎ型層に変えることにより、本発明の構造を適用でき
る。また、適用できる素子は、ＩＧＢＴ、ＧＴＯ、ＳＩ
トランジスタ、ＳＩサイリスタ、ダイオード、サイリス
タ等幅広く、活性領域あるいは主接合部の構造として
は、プレーナ型、トレンチ型、埋め込み型等いずれの場
合にも適用できる。Although the embodiments of the present invention have been described above, the present invention covers a wider range of applications or derivative structures. In the second to fifth, seventh and eighth embodiments, the impurity concentration of the innermost periphery of each of the plurality of trench bottom p + layers 2 and inter-trench p + layers 3 is set to be the highest. However, those located on the outer periphery may be formed so that the impurity concentration gradually decreases toward the outer periphery. In addition, the impurity concentrations of both may be set to arbitrary values. In each of the above embodiments, only the case of the SiC element has been described, but the present invention can be applied to other semiconductor materials such as silicon and gallium arsenide. In particular, diamonds,
It is effective for wide gap semiconductor materials such as gallium nitride. In the description of each of the above embodiments, the drift layer 6
Described above is only an n-type element, but the drift layer 6
Even in the case of a device of the type, the structure of the present invention can be applied by changing the n-type layer to the p-type layer and changing the p-type layer to the n-type layer. Applicable elements are IGBT, GTO, SI
Transistors, SI thyristors, diodes, thyristors, etc. are widely used, and the structure of the active region or the main junction can be applied to any type such as a planar type, a trench type, and a buried type.

【００３４】[0034]

【発明の効果】本発明によれば、半導体装置の主接合部
を囲むように複数のトレンチを設け、各トレンチ底部及
び隣り合うトレンチ間に、ドリフト層とは逆の導電型の
半導体層をそれぞれ形成する。これによって、逆電圧印
加時に空乏層がトレンチ底部とトレンチ間のドリフト層
に拡がり活性領域の端部の主接合部の電界を緩和する。
またトレンチ間ｎ-層がドリフト層の深さ方向のトレン
チ間ｐ+層とトレンチ底部ｐ+層の間に形成されることに
よりターミネーション部の面積が削減され、同一サイズ
の半導体装置では、その分活性領域の面積を大きくでき
るので電流容量を増加することができるとともにオン抵
抗を低減することができる。これによって超高精度濃度
制御技術を必要とせずに専有面積の少ないターミネーシ
ョン構造を有する高耐圧半導体装置が実現できる。According to the present invention, a plurality of trenches are provided so as to surround a main junction of a semiconductor device, and a semiconductor layer of a conductivity type opposite to that of a drift layer is provided between each trench bottom and adjacent trenches. Form. As a result, when a reverse voltage is applied, the depletion layer spreads to the drift layer between the bottom of the trench and the trench, and the electric field at the main junction at the end of the active region is reduced.
The trench between n - layer reduces the area of the termination portion by is formed between the depth of the trench between the p + layer and the trench bottom p + layer of the drift layer, the semiconductor device of the same size, the amount Since the area of the active region can be increased, the current capacity can be increased and the on-resistance can be reduced. As a result, a high breakdown voltage semiconductor device having a termination structure with a small occupied area can be realized without requiring an ultra-high-accuracy concentration control technique.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１実施例の半導体装置である等間隔
トレンチ型ターミネーション部を有するトレンチ型ＭＯ
ＳＦＥＴの平面図FIG. 1 is a semiconductor device according to a first embodiment of the present invention, which is a trench type MO having equally spaced trench type termination portions.
Plan view of SFET

【図２】図１のII−II断面図FIG. 2 is a sectional view taken along line II-II of FIG.

【図３】（ａ）は第１実施例の半導体装置の要部断面図 （ｂ）は従来のＦＬＲ（Field Limitting Ring）を有す
る半導体装置の要部断面図3A is a cross-sectional view of a main part of the semiconductor device according to the first embodiment, and FIG. 3B is a cross-sectional view of a main part of a semiconductor device having a conventional FLR (Field Limiting Ring).

【図４】本発明の第２実施例の半導体装置である不等間
隔のトレンチ型ターミネーション部を有するトレンチ型
ＭＯＳＦＥＴの断面図FIG. 4 is a cross-sectional view of a trench MOSFET having unequally spaced trench terminations, which is a semiconductor device according to a second embodiment of the present invention.

【図５】本発明の第３実施例の半導体装置である補助電
極（フィールドプレート）と等間隔トレンチ型ターミネ
ーション部を有するトレンチ型ＭＯＳＦＥＴの断面図FIG. 5 is a cross-sectional view of a trench MOSFET having an auxiliary electrode (field plate) and an equally spaced trench termination portion, which is a semiconductor device according to a third embodiment of the present invention.

【図６】本発明の第４実施例の半導体装置である補助電
極（フィールドプレート）と等間隔トレンチ型ターミネ
ーション部を有するトレンチ型ＭＯＳＦＥＴの断面図FIG. 6 is a cross-sectional view of a trench type MOSFET having an auxiliary electrode (field plate) and an equally spaced trench type termination portion as a semiconductor device according to a fourth embodiment of the present invention.

【図７】本発明の第５実施例の半導体装置である浅い等
間隔トレンチ型ターミネーション部を有するトレンチ型
ＭＯＳＦＥＴの断面図FIG. 7 is a cross-sectional view of a trench MOSFET having shallow equally-spaced trench terminations, which is a semiconductor device according to a fifth embodiment of the present invention.

【図８】本発明の第６実施例の半導体装置であるショッ
トキーコンタクトを有するトレンチ型ターミネーション
型部を有するＭＯＳＦＥＴの断面図FIG. 8 is a cross-sectional view of a MOSFET having a trench-type termination portion having a Schottky contact, which is a semiconductor device according to a sixth embodiment of the present invention.

【図９】本発明の第７実施例の半導体装置であるショッ
トキーコンタクトを有するトレンチ型ターミネーション
型部を有するＭＯＳＦＥＴの断面図FIG. 9 is a cross-sectional view of a MOSFET having a trench termination type portion having a Schottky contact, which is a semiconductor device according to a seventh embodiment of the present invention.

【図１０】本発明の第８実施例の半導体装置であるショ
ットキーコンタクトを有するトレンチ型ターミネーショ
ン型部を有するＭＯＳＦＥＴの断面図FIG. 10 is a cross-sectional view of a MOSFET having a trench termination type portion having a Schottky contact, which is a semiconductor device according to an eighth embodiment of the present invention.

【図１１】本発明の半導体装置を用いたインバータ装置
の回路図FIG. 11 is a circuit diagram of an inverter device using the semiconductor device of the present invention.

【図１２】本発明の半導体装置を用いた整流装置の回路
図FIG. 12 is a circuit diagram of a rectifier using the semiconductor device of the present invention.

【図１３】従来のＪＴＥ（Junction Termination Exten
tion）を有する半導体装置の断面図FIG. 13 shows a conventional JTE (Junction Termination Extension).
Sectional view of a semiconductor device having

【図１４】従来のＦＬＲ（Field Limitting Ring）を有
する半導体装置の断面図FIG. 14 is a cross-sectional view of a conventional semiconductor device having an FLR (Field Limiting Ring).

【符号の説明】[Explanation of symbols]

１：主接合部 １Ａ：活性領域 ２、２Ａ、２Ｂ：トレンチ底部ｐ+層 ３、３Ａ：トレンチ間ｐ+層 ４：トレンチ間ｎ-層 ４Ａ、４Ｂ：ｎ-層 ５：ｐ+ボディ層 ６：ｎ-ドリフト層 ７：ドレイン領域 ９、９Ａ、９Ｂ：ターミネーション用トレンチ １０：トレンチゲート １１：ドレイン電極 １２：ソース電極 １３：ゲート電極 １４、１４Ａ：補助電極 １５：ターミネーション用トレンチ絶縁物層 １６：フィールドリミッタ １７、１７Ａ、１７Ｂ、１７Ｃ、１７Ｄ、１７Ｅ、１７
Ｆ、１７Ｇ：ショットキーコンタクト １８：ＪＴＥ領域 １９：空乏層 ２０：ＦＬＲ層 ２１：空乏層 ３５、３６：絶縁物層 ３０：空乏層 ３９、３９Ａ：ターミネーション部 ４０：ｐ+電界緩和層 ４３：接合部 ４６：主表面 ５３：トレンチ間ｐ+層 ＭＯＳＦＥＴ：ＳＷ１１、ＳＷ１２、ＳＷ２１、ＳＷ２
２、ＳＷ３１、ＳＷ３２ ダイオード：Ｄ１１、Ｄ１２、Ｄ２１、Ｄ２２、Ｄ３
１、Ｄ３２1: Main junction 1A: Active region 2, 2A, 2B: Trench bottom p + layer 3, 3A: Trench p + layer 4: Trench n − layer 4A, 4B: n − layer 5: p + body layer 6 : N - drift layer 7: Drain region 9, 9A, 9B: Termination trench 10: Trench gate 11: Drain electrode 12: Source electrode 13: Gate electrode 14, 14A: Auxiliary electrode 15: Termination trench insulator layer 16: Field limiters 17, 17A, 17B, 17C, 17D, 17E, 17
F, 17G: Schottky contact 18: JTE region 19: Depletion layer 20: FLR layer 21: Depletion layer 35, 36: Insulator layer 30: Depletion layer 39, 39A: Termination part 40: p + field relaxation layer 43: Junction Part 46: Main surface 53: P + layer between trenches MOSFET: SW11, SW12, SW21, SW2
2, SW31, SW32 Diodes: D11, D12, D21, D22, D3
1, D32

─────────────────────────────────────────────────────
────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成１０年４月１７日[Submission date] April 17, 1998

【手続補正１】[Procedure amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】特許請求の範囲[Correction target item name] Claims

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【特許請求の範囲】[Claims]

【手続補正２】[Procedure amendment 2]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】００１６[Correction target item name] 0016

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【００１６】本実施例の半導体装置の製作工程は、次の
とおりである。最初に、完成後はドレイン層７として機
能する部分となる１０18から１０20atm/cm3の不純物濃
度のｎ+形ＳｉＣ（炭化珪素）の基板を用意し、この基
板の第１の主面となる一方の表面に１０14から１０16at
m/cm3の不純物濃度のＳｉＣのｎ-ドリフト層６を気相成
長法等により形成する。次にｎ-ドリフト層６の上に１
０16から１０18atm/cm3程度の不純物濃度のＳｉＣのｐ+
層を気相成長法等により形成する。そして、１０18atm/
cm3程度の不純物濃度のｎ+領域を窒素、りん等のイオン
打ち込み法等により所望の領域に選択的に形成する。次
に、上記の工程を経た基板を異方性エッチングして、ｐ
+層を貫通し底部がｎ-ドリフト層６内に所定距離進入す
るトレンチゲート１０及びターミネーション部３９用の
トレンチ（溝）９を形成する。次にトレンチ９の底から
深さ０．５μmの範囲に、１０16から１０18atm/cm3程度
の不純物濃度のｐ+層２をホウ素、アルミニウム等のイ
オン打ち込み等により形成する。続いて、トレンチゲー
ト１０の内壁およびターミネーション部３９用トレンチ
９の内壁にＳｉＯ2の絶縁物層３５、３６を形成する。
トレンチゲート１０の内壁の絶縁物層３５は、厚さ０．
１μｍ程度であるが、ターミネーション部３９用トレン
チ９の内壁の絶縁物層の厚さは、０．５から１μｍと厚
くてもよい。その後トレンチ部９及びトレンチゲート１
０内には、りんを高濃度に含んだポリシリコンを堆積し
て埋め込む。次に、トレンチゲート１０内のポリシリコ
ンを残し、他の部分のポリシリコンを除去し、ゲート電
極１３を形成する。最後に、アルミニウム、ニッケル等
でｐ+層５の表面にソース電極１２を形成する。また基
板であるドレイン層７の第２の主面の他方の表面（図１
ではドレイン層７の下面）にドレイン電極１１を形成し
て完成する。なお、ｐ+層３及び５はエピタキシャル法
で形成したが、イオン打ち込み法を用いても形成でき
る。The manufacturing process of the semiconductor device according to the present embodiment is as follows. First, preparing a substrate after the completion becomes part functioning as a drain layer 7 10 18 10 20 atm / cm impurity concentration of 3 n + form SiC (silicon carbide), the group
10 14 to 10 16 at on one surface to be the first main surface of the plate
An n − drift layer 6 of SiC having an impurity concentration of m / cm 3 is formed by a vapor phase growth method or the like. Next, 1 is placed on n − drift layer 6.
P + of SiC with an impurity concentration of about 0 16 to 10 18 atm / cm 3
The layer is formed by a vapor deposition method or the like. And 10 18 atm /
An n + region having an impurity concentration of about cm 3 is selectively formed in a desired region by ion implantation of nitrogen, phosphorus, or the like. Next, the substrate having undergone the above steps is subjected to anisotropic etching to obtain p
A trench gate 10 and a trench (groove) 9 for a termination portion 39 are formed so that the bottom portion of the trench layer 10 penetrates the n − drift layer 6 by a predetermined distance through the + layer. Next, ap + layer 2 having an impurity concentration of about 10 16 to 10 18 atm / cm 3 is formed in a range of a depth of 0.5 μm from the bottom of the trench 9 by ion implantation of boron, aluminum, or the like. Subsequently, insulator layers 35 and 36 of SiO 2 are formed on the inner wall of the trench gate 10 and the inner wall of the trench 9 for the termination portion 39.
The insulator layer 35 on the inner wall of the trench gate 10 has a thickness of 0.1 mm.
The thickness is about 1 μm, but the thickness of the insulating layer on the inner wall of the trench 9 for the termination portion 39 may be as thick as 0.5 to 1 μm. Then, the trench portion 9 and the trench gate 1
Polysilicon containing a high concentration of phosphorus is deposited and buried in 0. Next, the polysilicon in the trench gate 10 is left, and the polysilicon in the other portions is removed to form the gate electrode 13. Finally, a source electrode 12 is formed on the surface of the p + layer 5 using aluminum, nickel, or the like. Further, the other surface of the second main surface of the drain layer 7 as a substrate (FIG. 1)
Then, the drain electrode 11 is formed on the lower surface of the drain layer 7) to complete the process. Although the p + layers 3 and 5 are formed by an epitaxial method, they can be formed by an ion implantation method.

【手続補正３】[Procedure amendment 3]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】００３１[Correction target item name] 0031

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【００３１】《インバータ装置》図１１は、本発明を適
用したＭＯＳＦＥＴおよびダイオードを用いて構成し
た、三相のインバータの例を示す回路図である。スイッ
チング素子としての６個のＭＯＳＦＥＴＳＷ１１、ＳＷ
１２、ＳＷ２１、ＳＷ２２、ＳＷ３１、ＳＷ３２および
６個の各ＭＯＳＦＥＴＳＷ１１ないしＳＷ３２に、並列
で逆方向に接続したダイオードＤ１１、Ｄ１２、Ｄ２
１、Ｄ２２、Ｄ３１、Ｄ３２により直流を交流に変換す
る。ＭＯＳＦＥＴ ＳＷ１１・・・ＳＷ３２は、スイッ
チング速度の大きなスイッチング素子であり、このＭＯ
ＳＦＥＴおよびダイオードに本発明を適用することによ
り、スイッチング素子の高耐圧化ができる。ＳｉＣを用
いた従来のＭＯＳＦＥＴでは、５００Ｖ以上の高耐圧の
半導体装置ではオン抵抗が大きくなり、高耐圧インバー
タの高性能化が困難であった。本発明の各実施例による
半導体装置を適用すれば、高耐圧インバータ装置の高性
能化、すなわちコンパクト化、低損失化、低雑音化を達
成できる。その結果インバータ装置を用いたシステムの
低コスト化、高効率化が実現できる。<< Inverter Device >> FIG. 11 is a circuit diagram showing an example of a three-phase inverter formed by using MOSFETs and diodes to which the present invention is applied. Six MOSFETs SW11 and SW as switching elements
12, SW21, SW22, SW31, SW32 and
In parallel with each of the six MOSFETs SW11 to SW32
Diodes D11, D12, D2 connected in the reverse direction
1. DC is converted to AC by D22, D31 and D32. The MOSFETs SW11... SW32 are switching elements having a high switching speed.
By applying the present invention to the SFET and the diode, the switching element can have a higher breakdown voltage. In a conventional MOSFET using SiC, on-resistance increases in a semiconductor device having a high withstand voltage of 500 V or more, and it has been difficult to improve the performance of a high withstand voltage inverter. By applying the semiconductor device according to each embodiment of the present invention, it is possible to achieve high performance of the high withstand voltage inverter device, that is, downsizing, low loss, and low noise. As a result, cost reduction and high efficiency of the system using the inverter device can be realized.

【手続補正４】[Procedure amendment 4]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】００３２[Correction target item name] 0032

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【００３２】《整流装置》図１２は、本発明を適用した
ＭＯＳＦＥＴおよびダイオードを用いて構成した、整流
装置の例を示す回路図である。ブリッジ接続した４個の
ＭＯＳＦＥＴＳＷ１１、ＳＷ１２、ＳＷ２１、ＳＷ２２
および各ＭＯＳＦＥＴに並列に接続したダイオードＤ１
１、Ｄ１２、Ｄ２１、Ｄ２２により交流を直流に変換す
る。本発明をＭＯＳＦＥＴとダイオードに適用すれば素
子のコンパクト化がはかれ、さらに高周波スイッチング
を行えることから、高耐圧整流装置のコンパクト化、低
損失化、低雑音化などの効果が得られる。したがって、
整流装置を用いたシステムの低コスト、高効率化が達成
できる。[0032] "rectifier" 1 2 was constructed using the applied MOSFET and diode present invention, is a circuit diagram showing an example of the rectifier device. Four bridge-connected MOSFETs SW11, SW12, SW21, SW22
And a diode D1 connected in parallel with each MOSFET
1, D12, D21, and D22 convert alternating current into direct current. If the present invention is applied to MOSFETs and diodes,
Higher frequency switching
, Which makes the high-voltage rectifier compact and low
Effects such as loss and noise reduction can be obtained. Therefore,
Low cost and high efficiency of the system using the rectifier can be achieved.

【手続補正５】[Procedure amendment 5]

【補正対象書類名】図面[Document name to be amended] Drawing

【補正対象項目名】図１２[Correction target item name] FIG.

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【図１２】 FIG.

Claims (24)

【特許請求の範囲】[Claims] 【請求項１】 半導体装置の第１の導電型の半導体層の
一方の表面の一部分に形成された第２の導電型の第１の
半導体層、 前記第１の導電型の半導体層の前記一方の表面の前記第
１の半導体層を有しない領域において、前記第１の半導
体層との間に所定の間隔を保って前記半導体層の表面か
ら所定の深さに底をもつ溝により隔てられて前記第１の
半導体層を囲むように設けられた少なくとも１個の第２
の導電型の第２の半導体層、 隣りあう２つの第２の導電型の半導体層の間の前記溝の
底部から前記第１の導電型の半導体層の内部に形成され
た第２の導電型の半導体領域、 前記第１の半導体層に設けられた電極、及び前記第１の
導電型の半導体層の他方の面に設けられた他の電極を有
する高耐圧半導体装置。A second conductive type first semiconductor layer formed on a part of one surface of the first conductive type semiconductor layer of the semiconductor device; the one of the first conductive type semiconductor layers; In a region not having the first semiconductor layer on the surface of the semiconductor layer, the semiconductor device is separated from the surface of the semiconductor layer by a groove having a bottom at a predetermined depth while maintaining a predetermined distance from the first semiconductor layer. At least one second semiconductor provided so as to surround the first semiconductor layer.
A second conductivity type formed inside the first conductivity type semiconductor layer from the bottom of the groove between two adjacent second conductivity type semiconductor layers. A high withstand voltage semiconductor device, comprising: a semiconductor region, an electrode provided on the first semiconductor layer, and another electrode provided on the other surface of the semiconductor layer of the first conductivity type. 【請求項２】 前記第２の導電型の第１の半導体層及び
第２の半導体層の表面と前記溝の内面に形成された絶縁
物層を有する請求項１記載の高耐圧半導体装置。2. The high breakdown voltage semiconductor device according to claim 1, further comprising an insulating layer formed on the surface of the first semiconductor layer and the second semiconductor layer of the second conductivity type and on the inner surface of the groove. 【請求項３】 前記第１の導電型の半導体層の不純物濃
度より濃い不純物濃度を有する第１の導電型の他の半導
体層が、最外周の第２の半導体層より外周の領域におけ
る前記第１の導電型の半導体層の表面部に設けられた請
求項１記載の高耐圧半導体装置。3. The semiconductor device of claim 1, wherein the other semiconductor layer of the first conductivity type having an impurity concentration higher than the impurity concentration of the semiconductor layer of the first conductivity type is formed in the outermost peripheral region of the second semiconductor layer. 2. The high breakdown voltage semiconductor device according to claim 1, wherein said high breakdown voltage semiconductor device is provided on a surface portion of said first conductivity type semiconductor layer. 【請求項４】 前記第１の半導体層と、前記第１の半導
体層に溝を隔てて隣接する前記第２の半導体層との間の
距離が、互いに隣接する他の２つの第２の半導体層の間
の距離より大きくなされていることを特徴とする請求項
１記載の高耐圧半導体装置。4. The distance between the first semiconductor layer and the second semiconductor layer adjacent to the first semiconductor layer with a groove therebetween is another two second semiconductor layers adjacent to each other. 2. The high breakdown voltage semiconductor device according to claim 1, wherein the distance between the layers is larger than the distance between the layers. 【請求項５】 前記第１の導電型の半導体層の前記一方
の表面における、前記第２の半導体層の高さが、前記第
１の半導体層の高さより低くなされていることを特徴と
する請求項１記載の高耐圧半導体装置。5. The semiconductor device according to claim 1, wherein a height of the second semiconductor layer on the one surface of the semiconductor layer of the first conductivity type is lower than a height of the first semiconductor layer. The high breakdown voltage semiconductor device according to claim 1. 【請求項６】 半導体装置の第１の導電型の半導体層の
一方の表面の一部分に形成された第２の導電型の第１の
半導体層、 前記第１の導電型の半導体層の前記一方の表面の前記第
１の半導体層を有しない領域において、前記第１の半導
体層との間に所定の間隔を保って前記半導体層の表面か
ら所定の深さをもつ溝により隔てられて前記第１の半導
体層を囲むように設けられた少なくとも１個の第２の導
電型の第２の半導体層、 隣りあう２つの第２の導電型の半導体層の間の前記溝の
底部から前記第１の導電型の半導体層の内部に形成され
た第２の導電型の半導体領域、 前記第１の半導体層に設けた電極、 前記第１の導電型の半導体層の他方の面に設けられた他
の電極、 前記第２の半導体層の接続部以外の表面及び前記溝の内
面にそれぞれ形成された絶縁物層、及び前記第２の半導
体層の前記接続部の表面と前記溝の底部の絶縁物層の表
面にわたって連続的に設けられた導電層を有する高耐圧
半導体装置。6. A first semiconductor layer of a second conductivity type formed on a part of one surface of a semiconductor layer of a first conductivity type of a semiconductor device, wherein the one of the first conductivity type semiconductor layers is formed. In a region not having the first semiconductor layer on the surface of the first semiconductor layer, the first semiconductor layer is separated from the surface of the semiconductor layer by a groove having a predetermined depth while maintaining a predetermined distance from the first semiconductor layer. At least one second semiconductor layer of the second conductivity type provided so as to surround the one semiconductor layer; and the first semiconductor layer from the bottom of the groove between two adjacent semiconductor layers of the second conductivity type. A second conductivity type semiconductor region formed inside the first conductivity type semiconductor layer, an electrode provided on the first semiconductor layer, and another provided on the other surface of the first conductivity type semiconductor layer. Electrodes on the surface of the second semiconductor layer other than the connection portion and on the inner surface of the groove, respectively. And an insulating material layer, and a high voltage semiconductor device having an insulator layer conductive layer provided continuously across the surface of the bottom surface and the groove of the connecting portion of the second semiconductor layer. 【請求項７】 半導体装置の第１の導電型の半導体層の
一方の表面の一部分に形成された第２の導電型の第１の
半導体層、 前記第１の導電型の半導体層の前記一方の表面の前記第
１の半導体層を有しない領域において、前記第１の半導
体層との間に所定の間隔を保って前記半導体層の表面か
ら所定の深さをもつ溝により隔てられて前記第１の半導
体層を囲むように設けられた少なくとも１個の第２の導
電型の第２の半導体層、 隣りあう２つの第２の導電型の半導体層の間の前記溝の
底部から前記第１の導電型の半導体層の内部に形成され
た第２の導電型の半導体領域、 前記第１の半導体層に設けられた電極、 前記第１の導電型の半導体層の他方の面に設けられた他
の電極、 前記の第２半導体層の表面に形成された絶縁物層、及び
前記第２の半導体層の絶縁物層の表面と前記溝の底面に
わたって連続的に設けられた導電層を有する高耐圧半導
体装置。7. A first semiconductor layer of a second conductivity type formed on a part of one surface of a semiconductor layer of a first conductivity type of the semiconductor device, wherein the one of the first conductivity type semiconductor layers is formed. In a region not having the first semiconductor layer on the surface of the first semiconductor layer, the first semiconductor layer is separated from the surface of the semiconductor layer by a groove having a predetermined depth while maintaining a predetermined distance from the first semiconductor layer. At least one second semiconductor layer of the second conductivity type provided so as to surround the one semiconductor layer; and the first semiconductor layer from the bottom of the groove between two adjacent semiconductor layers of the second conductivity type. A second conductivity type semiconductor region formed inside the first conductivity type semiconductor layer, an electrode provided on the first semiconductor layer, and a second conductivity type semiconductor region provided on the other surface of the first conductivity type semiconductor layer. Another electrode, an insulator layer formed on a surface of the second semiconductor layer, and the second High voltage semiconductor device having a conductive layer provided continuously over the bottom surface and the grooves of the insulating layer of the conductor layer. 【請求項８】 半導体装置の第１の導電型の半導体層の
一方の表面の一部分に形成された第２の導電型の半導体
層、 前記第１の導電型の半導体層の前記一方の表面の前記第
１の半導体層を有しない領域において、前記第１の半導
体層との間に所定の間隔を保って前記第１の半導体層を
囲むように設けられた少なくとも１個のショットキー接
合を形成するための導電層、 前記第１の半導体層に設けられた電極、及び前記第１の
導電型の半導体層の他方の面に設けられた他の電極を有
する高耐圧半導体装置。8. A semiconductor layer of the second conductivity type formed on a part of one surface of the semiconductor layer of the first conductivity type of the semiconductor device, wherein the one surface of the semiconductor layer of the first conductivity type is In a region not having the first semiconductor layer, at least one Schottky junction provided so as to surround the first semiconductor layer at a predetermined distance from the first semiconductor layer is formed. A high-voltage semiconductor device, comprising: a conductive layer for forming the first semiconductor layer; an electrode provided on the first semiconductor layer; and another electrode provided on the other surface of the first conductive semiconductor layer. 【請求項９】 互いに隣接する複数の導電層は前記第１
の導電型の半導体層の前記一方の表面に設けられた互い
に異なる高さを有する領域にそれぞれ形成された請求項
８記載の高耐圧半導体装置。9. The method according to claim 9, wherein the plurality of conductive layers adjacent to each other include the first conductive layer.
9. The high withstand voltage semiconductor device according to claim 8, wherein said semiconductor layers are formed in regions having different heights provided on said one surface of said conductive type semiconductor layer. 【請求項１０】 最外周の導電層が設けられた前記第１
の導電型の半導体層の表面部において、前記最外周の導
電層の内周の端部から所定距離離れた外周領域に、前記
第１の導電型の半導体層の不純物濃度より濃い不純物濃
度を有する第１の導電型の他の半導体層を設けた請求項
８記載の高耐圧半導体装置。10. The first electrode provided with an outermost conductive layer.
In a surface portion of the semiconductor layer of the first conductivity type, an impurity concentration higher than the impurity concentration of the semiconductor layer of the first conductivity type is provided in an outer peripheral region at a predetermined distance from an end of an inner periphery of the outermost conductive layer. 9. The high breakdown voltage semiconductor device according to claim 8, wherein another semiconductor layer of the first conductivity type is provided. 【請求項１１】 半導体装置の第１の導電型の半導体層
の一方の表面の一部分に形成された第２の導電型の第１
の半導体層、 前記第１の導電型の半導体層の前記一方の表面の前記第
１の半導体層を有しない領域において、前記第１の半導
体層との間に所定の間隔を保って前記半導体層の表面か
ら所定の深さに底をもつ溝により隔てられて前記第１の
半導体層を囲むように設けられた少なくとも１個の第２
の導電型の第２の半導体層、 前記第２の半導体層の表面及び前記溝の側面に形成され
た絶縁物層、 前記溝の底面に形成された導電層、 前記第１の半導体層に設けられた電極、及び前記第１の
導電型の半導体層の他方の面に設けられた他の電極を有
する高耐圧半導体装置。11. A second conductive type first layer formed on a portion of one surface of a first conductive type semiconductor layer of a semiconductor device.
A semiconductor layer of the first conductivity type semiconductor layer, in a region not having the first semiconductor layer on the one surface of the first conductive type semiconductor layer, maintaining a predetermined gap between the semiconductor layer and the first semiconductor layer; At least one second semiconductor provided to surround the first semiconductor layer and to be separated by a groove having a bottom at a predetermined depth from the surface of the first semiconductor layer
A second semiconductor layer having a conductivity type of: an insulator layer formed on a surface of the second semiconductor layer and a side surface of the groove; a conductive layer formed on a bottom surface of the groove; and provided on the first semiconductor layer. A high-breakdown-voltage semiconductor device, comprising: an electrode provided on the other surface of the semiconductor layer of the first conductivity type; 【請求項１２】 前記第１の導電型の半導体層の前記一
方の表面の周辺部に形成した導電層、及び前記導電層を
形成した前記半導体層の表面部において、前記導電層の
内周の端部から所定距離離れた外周領域に、前記第１の
導電型の半導体層の不純物濃度より濃い濃度の第１の導
電型の他の半導体領域を設けたことを特徴とする請求項
１１記載の高耐圧半導体装置。12. A conductive layer formed on a peripheral portion of the one surface of the first conductive type semiconductor layer, and a surface portion of the semiconductor layer on which the conductive layer is formed, wherein an inner periphery of the conductive layer is formed. 12. The semiconductor device according to claim 11, wherein another semiconductor region of a first conductivity type having a concentration higher than an impurity concentration of the semiconductor layer of the first conductivity type is provided in an outer peripheral region at a predetermined distance from an end. High breakdown voltage semiconductor device. 【請求項１３】 前記導電層が溝の底面において両側面
の絶縁物層にはさまれた部分に形成されたことを特徴と
する請求項１１記載の高耐圧半導体装置。13. The high breakdown voltage semiconductor device according to claim 11, wherein said conductive layer is formed in a portion sandwiched between insulator layers on both sides at the bottom of the groove. 【請求項１４】 半導体装置の第１の導電型の半導体層
の一方の表面の一部分に形成され第２の導電型の第１の
半導体層、 前記第１の導電型の半導体層の前記一方の表面の前記第
１の半導体層を有しない領域において、前記第１の半導
体層との間に所定の間隔を保って前記半導体層の表面か
ら所定の深さをもつ溝により隔てられて前記第１の半導
体層を囲むように設けられた少なくとも１個の第２の導
電型の第２の半導体層、 隣りあう２つの第２の導電型の半導体層の間の前記溝の
底面に形成した導電層、 前記第１の半導体層に設けた電極、及び前記第１の導電
型の半導体層の他方の面に設けた他の電極を有する高耐
圧半導体装置。14. A first semiconductor layer of a second conductivity type formed on a part of one surface of a semiconductor layer of a first conductivity type of the semiconductor device, wherein the one of the first semiconductor layers of the first conductivity type is formed. In a region of the surface not having the first semiconductor layer, the first semiconductor layer is separated from the surface of the semiconductor layer by a groove having a predetermined depth while maintaining a predetermined distance from the first semiconductor layer. At least one second conductive type second semiconductor layer provided so as to surround the semiconductor layer, and a conductive layer formed on the bottom surface of the groove between two adjacent second conductive type semiconductor layers. A high breakdown voltage semiconductor device comprising: an electrode provided on the first semiconductor layer; and another electrode provided on the other surface of the semiconductor layer of the first conductivity type. 【請求項１５】 前記第２の導電型の半導体領域は、最
内周のものが最も高い不純物濃度を有し、外周部のもの
は、外周に向かって順次不純物濃度が斬減するように形
成された請求項１、４、６又は７記載の高耐圧半導体装
置。15. The semiconductor region of the second conductivity type is formed such that the innermost region has the highest impurity concentration and the outermost region has the impurity concentration gradually reduced toward the outer periphery. The high breakdown voltage semiconductor device according to claim 1, 4, 6, or 7. 【請求項１６】 前記の第２の導電型の第２の半導体層
は、最内周のものが最も高い不純物濃度を有し、外周部
のものは外周に向かって順次不純物濃度が斬減するよう
に形成された請求項１、４、６、７、１１又は１４記載
の高耐圧半導体装置。16. The second semiconductor layer of the second conductivity type has the highest impurity concentration at the innermost periphery, and the impurity concentration gradually decreases toward the outer periphery at the outer periphery. The high breakdown voltage semiconductor device according to claim 1, wherein the semiconductor device is formed as described above. 【請求項１７】 前記の第２の導電型の複数の半導体領
域は、それぞれ所定の不純物濃度を有することを特徴と
する請求項１、４、６又は７記載の高耐圧半導体装置。17. The high breakdown voltage semiconductor device according to claim 1, wherein each of the plurality of semiconductor regions of the second conductivity type has a predetermined impurity concentration. 【請求項１８】 前記の第２の導電型の複数の第２の半
導体層は、それぞれ所定の不純物濃度を有することを特
徴とする請求項１、４、６、７、１１又は１４記載の高
耐圧半導体装置。18. The semiconductor device according to claim 1, wherein each of the plurality of second semiconductor layers of the second conductivity type has a predetermined impurity concentration. Withstand voltage semiconductor device. 【請求項１９】 前記半導体装置は、ＭＯＳ型ＦＥＴ、
ダイオ−ド、絶縁ゲートバイポーラトランジスタ（ＩＧ
ＢＴ）、ゲートターンオフサイリスタ（ＧＴＯサイリス
タ）、ＳＩサイリスタ、から構成された群から選択され
た１種である請求項１、６、７、８、１１又は１４記載
の高耐圧半導体装置。19. The semiconductor device, comprising: a MOS FET;
Diode, insulated gate bipolar transistor (IG
15. The high breakdown voltage semiconductor device according to claim 1, wherein the device is one selected from the group consisting of BT), a gate turn-off thyristor (GTO thyristor), and an SI thyristor. 【請求項２０】 前記半導体装置は、炭化珪素（Ｓｉ
Ｃ）、ダイヤモンド、ガリウムナイトライド、シリコン
及びガリウム砒素から構成された群から選択した材料を
基材とするダイオードである請求項１、６、７、８、１
１又は１４記載の高耐圧半導体装置。20. The semiconductor device, comprising: a silicon carbide (Si)
A diode based on a material selected from the group consisting of C), diamond, gallium nitride, silicon and gallium arsenide.
15. The high breakdown voltage semiconductor device according to 1 or 14. 【請求項２１】 前記半導体装置は、前記第１の半導体
層の近傍のトレンチゲート内に設けられたゲート電極を
有し、炭化珪素（ＳｉＣ）、ダイヤモンド、ガリウムナ
イトライド、シリコン及びガリウム砒素から構成された
群から選択した材料を基材とするＭＯＳ型のＦＥＴであ
ることを特徴とする請求項１、６、７、８、１１又は１
４記載の高耐圧半導体装置。21. The semiconductor device has a gate electrode provided in a trench gate near the first semiconductor layer, and is made of silicon carbide (SiC), diamond, gallium nitride, silicon, and gallium arsenide. 2. A MOS-type FET having a material selected from a selected group as a base material.
5. The high breakdown voltage semiconductor device according to 4. 【請求項２２】 前記半導体装置は、プレーナ型トラン
ジスタ、トレンチ型トランジスタ及び埋め込み型トラン
ジスタから構成される群から選択された請求項１、６、
７、８、１１又は１４記載の高耐圧半導体装置。22. The semiconductor device according to claim 1, wherein the semiconductor device is selected from the group consisting of a planar transistor, a trench transistor, and a buried transistor.
15. The high breakdown voltage semiconductor device according to 7, 8, 11, or 14. 【請求項２３】 一対の直流入力端子と、 前記一対の直流入力端子間に接続された少なくとも２対
の、２個の半導体素子が直列接続された接続体と、 前記各半導体素子に逆方向に接続されたダイオードとを
有し、 前記半導体素子が半導体素子の第１の導電型の半導体層
の一方の表面の一部分に形成された第２の導電型の第１
の半導体層、 前記第１の導電型の半導体層の前記一方の表面の前記第
１の半導体層を有しない領域において、前記第１の半導
体層との間に所定の間隔を保って前記半導体層の表面か
ら所定の深さに底をもつ溝により隔てられて前記第１の
半導体層を囲むように設けられた少なくとも１個の第２
の導電型の第２の半導体層、 隣りあう２つの第２の導電型の半導体層の間の前記溝の
底部から前記第１の導電型の半導体層の内部に形成され
た第２の導電型の半導体領域、 前記第１の半導体層に設けられた電極、 前記第１の導電型の半導体層の他方の面に設けられた他
の電極及び前記第１の半導体層の近傍に設けられたゲー
ト電極を有する高耐圧半導体装置であることを特徴とす
る電力変換器。23. A pair of DC input terminals; a connection body in which at least two pairs of two semiconductor elements connected between the pair of DC input terminals are connected in series; A first diode of a second conductivity type formed on a part of one surface of a semiconductor layer of the first conductivity type of the semiconductor device.
A semiconductor layer of the first conductivity type semiconductor layer, in a region not having the first semiconductor layer on the one surface of the first conductive type semiconductor layer, maintaining a predetermined gap between the semiconductor layer and the first semiconductor layer; At least one second semiconductor provided to surround the first semiconductor layer and to be separated by a groove having a bottom at a predetermined depth from the surface of the first semiconductor layer
A second conductivity type formed inside the first conductivity type semiconductor layer from the bottom of the groove between two adjacent second conductivity type semiconductor layers. A semiconductor region, an electrode provided on the first semiconductor layer, another electrode provided on the other surface of the semiconductor layer of the first conductivity type, and a gate provided near the first semiconductor layer A power converter characterized by being a high breakdown voltage semiconductor device having electrodes. 【請求項２４】 一対の交流入力端子と、 前記一対の交流入力端子間にブリッジ接続された、少な
くとも４対の半導体素子とダイオードの並列接続体とを
有し、前記半導体素子が、 半導体素子の第１の導電型の半導体層の一方の表面の一
部分に形成された第２の導電型の第１の半導体層、 前記第１の導電型の半導体層の前記一方の表面の前記第
１の半導体層を有しない領域において、前記第１の半導
体層との間に所定の間隔を保って前記半導体層の表面か
ら所定の深さに底をもつ溝により隔てられて前記第１の
半導体層を囲むように設けられた少なくとも１個の第２
の導電型の第２の半導体層、 隣りあう２つの第２の導電型の半導体層の間の前記溝の
底部から前記第１の導電型の半導体層の内部に形成され
た第２の導電型の半導体領域、 前記第１の半導体層に設けられた電極、 前記第１の導電型の半導体層の他方の面に設けられた他
の電極及び前記第１の半導体層の近傍に設けられたゲー
ト電極を有する高耐圧半導体装置であることを特徴とす
る整流装置。24. A semiconductor device comprising: a pair of AC input terminals; and a parallel connection of at least four pairs of semiconductor elements and diodes connected in a bridge between the pair of AC input terminals; A first semiconductor layer of the second conductivity type formed on a part of one surface of the semiconductor layer of the first conductivity type; the first semiconductor on the one surface of the semiconductor layer of the first conductivity type In a region having no layer, the first semiconductor layer is surrounded by a groove having a bottom at a predetermined depth from a surface of the semiconductor layer while maintaining a predetermined distance from the first semiconductor layer. At least one second provided
A second conductivity type formed inside the first conductivity type semiconductor layer from the bottom of the groove between two adjacent second conductivity type semiconductor layers. A semiconductor region, an electrode provided on the first semiconductor layer, another electrode provided on the other surface of the semiconductor layer of the first conductivity type, and a gate provided near the first semiconductor layer A rectifier characterized by being a high breakdown voltage semiconductor device having electrodes.
JP9237511A 1997-09-02 1997-09-02 Semiconductor device having high breakdown strength and power converter employing the same Pending JPH1187698A (en)

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