JPH118565A - Transmission/reception equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide transmission/reception equipment, with which data can be surely exchanged between plural miniaturized and simplified transmission/ reception equipment, without extending memory or the like. SOLUTION: This equipment 1 has an input part 3 for inputting data, a display part 6 for displaying data, a transmission part 4 for transmitting data, a reception part 5 for receiving data, and a control part 2 for controlling these respective equipment parts 3 to 6. The control part 2 has a CPU 11 for controlling the respective equipment parts 3 to 6, ROM 12 for storing control instructions or the like, and a RAM 13 for temporarily storing transmission/ reception data or the like. The RAM 13 has plural register 13a-13f. Moreover, the input part 3 has four switches for setting the data to be transmitted. The control part 2 finds a random value N from that count value of data of '1' bit through header-demodulating processing, so that the length of reception processing can be determined.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmitting / receiving apparatus, and more particularly, to a data transmitting / receiving apparatus for asynchronously transmitting and receiving data.

[0002]

2. Description of the Related Art A conventional transmitting / receiving apparatus includes an input section for inputting data, a display section for displaying data and control commands, a transmitting section for transmitting data, a receiving section for receiving data, and each of these device sections. It has a control unit for controlling. The control unit is connected to each device via an interface, and controls a CPU that controls each device, a ROM (Read Only Memory) that stores control instructions and the like, and a plurality of devices that temporarily store transmission / reception data and the like. RAM consisting of buffers
(Random Access Memory).

In such a conventional transmitting and receiving apparatus, data input from an input unit is stored in a RAM in a control unit. The CPU sends the data in the RAM with a header attached to the transmission unit, and the transmission unit receives the transmission data from the CPU and transmits it. The data stored in the RAM is compared with data received later.

In receiving data, a receiving unit receives data at a high frequency sample clock in order to receive asynchronous data. The received data is sampled and stored in the RAM in the control unit. When all the data reception is completed, the CPU compares the data stored in the RAM with the data stored in the RAM before transmission to determine the data. If the result of this determination is that the received data matches the data stored in advance, it means that correct data has been received, and the CPU sends this received data to the display unit. The display unit displays the data sent from the CPU.

As described above, the conventional transmitting / receiving apparatus periodically repeats data transmission processing and reception processing among a plurality of transmission / reception apparatuses, and when data transmitted by a partner is received, the data is displayed on a display unit. Was to be displayed.

In such a conventional transmission / reception apparatus, when the specifications of a plurality of transmission / reception apparatuses that transmit / receive data to / from each other are the same, the time (the number of times of sampling) of the transmission processing and the reception processing and the cycle thereof are the same. Therefore, the phases of the transmission processing and the reception processing match each other, and when one is performing the transmission processing, the other also performs the transmission processing, and when one is performing the reception processing, the other performs the reception processing. Eventually, there was a possibility that data could not be received by each other.

FIG. 11 shows a case where two transmitting / receiving apparatuses have the same phase of transmission processing and reception processing. In FIG. 11, the numbers shown under each process are as follows:
The number of times of the processing (that is, the length of the processing time) is shown. In the transmission processing, the number of data transmissions is one, and in the reception processing, the number of data receptions is three.

That is, when the two transmission / reception devices 31 and 32 are in a state as shown in FIG. 11, they cannot receive data with each other.

In order to solve such a problem, in a conventional transmitting / receiving apparatus, processing for changing the number of times of sampling (length of processing time) of the receiving processing is performed. As this processing, for example, there is a method in which the number of times of sampling of the reception processing is changed for each reception processing using a random number value. In this case, as a method of generating a random value, there is a method of calculating a random value every time by a CPU, a method of providing a random number table in a ROM or the like, and referencing the table.

As described above, the conventional transmitting and receiving apparatus transmits and receives data by changing the number of times of sampling in the receiving process by using a random number value.

[0011]

However, according to the conventional transmission / reception device for calculating the random number value by the CPU every time, a complicated operation such as a floating-point operation must be performed each time the reception processing is performed. There is a problem that it is difficult to obtain a random number value in a small and easy transmission / reception device using a CPU.

Further, according to the conventional transmission / reception device in which a random number table is provided in an internal memory such as a ROM and a random number value is obtained by referring to the random number table, there is a problem that the memory has to be added and the cost is high.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a transmission / reception device that can reliably transmit and receive data between a plurality of small and easy transmission / reception devices without adding a memory or the like.

[0014]

In order to achieve the above-mentioned object, the present invention provides a setting means for setting predetermined transmission data, a transmission means for transmitting a transmission signal based on the transmission data, When the receiving means for receiving and the transmitting means transmit the transmission signal, a header is added to the transmission data to form a transmission signal, and the header included in the transmission signal after the reception means starts reception and before the header is received. And a control means for detecting a received noise signal and determining a period of the next reception by the receiving means in accordance with the noise signal.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a transmitting / receiving apparatus according to the present invention will be described in detail.

FIG. 1 shows an embodiment of a transmitting / receiving apparatus according to the present invention. The transmitting / receiving device 1 of the present invention includes an input unit 3 for inputting data, a display unit 6 for displaying data and control commands, a transmitting unit 4 for transmitting data, a receiving unit 5 for receiving data,
And a control unit 2 for controlling these device units 3 to 6. The control unit 2 is connected to each of the device units 3 to 6 via an interface (not shown).
6 for controlling the CPU 6, and an RO for storing control instructions and the like
M12 and RA for temporarily storing transmission / reception data, etc.
M13.

The RAM 13 has a work register 13a for work used in the reception processing, a reception register 13b for storing reception data, a data register 13c for storing identification data (transmission data), and the number of samplings performed in the reception processing. Count register 13 that stores
d, a random number value register 13e for storing the number of samplings (random number value N) in the receiving process, and a counter register 13f for storing a counter value used when calculating the random number value N
And a plurality of registers. The input unit 3 has four switches for setting data to be transmitted.

FIG. 2 shows an overall flow of data transmission / reception processing in the transmission / reception device 1 of the present invention. Transceiver 1
In, by pressing any one of the four switches of the input unit 3, an identification data (ID) code serving as transmission data is set (201). That is, of the four switches, an electric signal from a pressed switch becomes a high-level (H) signal, and an electric signal from an unpressed switch becomes a low-level (L) signal. To the CPU 11. CPU11
Corresponds to the electrical signal input from the input unit 3, the bit is turned “ON” for the H level signal, and the bit is “OFF” for the L level signal, The data is stored in the RAM 13 in the control unit 2. This ID
More specifically, the code is transmitted and received as a biphase signal in order to maintain the quality of the transmission / reception processing, and indicates OFF “0” or ON “1” in a 2-bit configuration. That is, data (L) of OFF “0” is represented by two bits of “10”, and data (H) of ON “1” is represented by two bits of a control unit of “01”. Therefore, the CPU 11 converts the four electric signals input from the input unit 3 into 8-bit data and stores them in the RAM.
13 in the data register 13c.

Thereafter, the CPU 11 initializes each value (202). That is, the work register 13a, the reception register 13b, the sample count register 13d, the random number value register 13e, and the counter register 13f are cleared.

When the initialization is completed, a data transmission process is performed (203). The CPU 11 sends a high-level (H) transmission control signal (Txcont = 1) to the transmission unit 4, and
Receives the transmission control signal (H) and is turned on. The CPU 11 adds a header stored in the ROM 12 to the head of the data in the data register 13c, and further adds an EC (Error Correction code) for recovering data from an error during transmission / reception to the end of the data. Thus, transmission data is formed and transmitted to the transmission unit 4. The transmitting unit 4 modulates the transmission data into a carrier wave and transmits it as a radio wave (203). The data (ID code) stored in the data register 13c is compared with data received later. When the transmission is completed, the CPU 11
Transmits a low-level (L) transmission control signal (Txcont = 0) to the transmission unit 4 to save power, and the transmission unit 4 receives the transmission control signal (L) and turns off the power. .

When the data transmission process (203) is completed, a data reception process is performed (204). CPU1
1 sends a high-level (H) reception control signal (Rxcont = 1) to the receiving unit 5 at the start of the data receiving process, and turns on the power of the receiving unit 5. When the reception is completed, C
The PU 11 sends a low-level (L) transmission control signal (Rxcont = 0) to the receiving unit 5 to save power, and the PU 11
Turn off the power.

FIG. 3 shows the receiving process. Reception processing 204
Calculates a random number N first. The random number value N indicates the number of samples in the reception data processing 304 in the subsequent stage.
The period of the reception data processing 304 is determined by this value. The CPU 11 reads a random number counter value from the counter register 13f. The random number counter value will be described later in detail. In the first receiving process, this value is “0” because it has been initialized in step 202 of FIG. Further, the CPU 11 reads from the ROM 12 a basic reception number that is set in advance according to the number of data to be received. The number of basic receptions may be input by the user from the input unit 3 in accordance with the number of transmission / reception devices 1 to be transmitted / received. Further, the CPU 11 reads from the ROM 12 the number of samples required to read data transmitted from one other transmitting / receiving device 1. The CPU 11
Using these basic reception number, random number counter value, and sampling number, a random number value N (the sampling number of the reception data processing 304) is calculated. (Equation 1) represents an equation for calculating the random number value N. (Equation 1) Random number value N = (Basic reception number + Random number counter value) × Sampling number

The CPU 11 stores the random number N obtained by (Equation 1) in the random number register 13e (301).

Next, the CPU 11 operates the counter register 1
3f and the sample count register 13d are cleared (302, 303). This sample count register 1
3d counts the number of samplings generated in the reception processing, and plays a role of a kind of timer. When all these initializations are completed, the received data processing is performed (304).

FIG. 4 shows the reception data processing 304 of FIG. The reception data process 304 performs two processes of a header demodulation process 401 and a reception data demodulation process 403. In the reception data processing 304, first, a header demodulation processing 401 is performed.

FIG. 5 shows the header demodulation process 401 of FIG. In the header demodulation process 401 of FIG. 5, first, the CPU 11 causes the receiving unit 5 to output a high level (H) signal.
Send a reception control signal. Upon receiving the reception control signal (H) from the CPU, the receiver 5 is turned on and starts receiving data with a high-frequency sampling pulse to receive asynchronous data (RxD). The received data is sampled and stored bit by bit in the LSB (Least Significant Bit) of the work register 13a in the RAM 13 (501). The CPU 11 checks whether the stored bit, that is, the bit stored in the LSB is "1" (502).

If the bit stored in the LSB of the work register 13a is "1", the CPU 11
Increases the value of the counter register 13f by “1” (50
3). If the bit stored in the LSB of the work register 13a is not "1" (that is, "0"),
The CPU 11 keeps the value of the counter register 13f as it is. The value of the counter register 13f is used to determine the random number N in step 301 (FIG. 3) of the next reception process 204. Each time the CPU 11 stores the sampled data in the LSB one bit at a time, it shifts the storage part of the work register 13a left by one bit by one bit and performs a serial / parallel conversion process (504).

Returning to FIG. 4, the CPU 11 compares the data stored in the work register 13a by the header demodulation processing 401 with the expected header value stored in the ROM 12 (402). If these data match, it means that the header of the data to be received has been detected, and the CPU 11 performs the received data demodulation processing (40).
3).

In the reception data demodulation process 403, the CP
The U11 receives the data transmitted following the header, samples the data one bit at a time, and stores it in the LSB of the work register 13a in the RAM 13. At this time, every time the sampling data is stored one bit at a time, the storage portion of the work register 13a is shifted left by one bit at a time, and a serial / parallel conversion process is performed. Each time a sample clock is generated to demodulate received data, the value of the sample count register 13d is counted up.

In step 402, if the detection of the header cannot be confirmed with a predetermined number of sample clocks, or
When the received data demodulation processing in step 403 is completed,
The reception data processing 304 ends.

Returning to FIG. 3, when the reception data processing 304 is completed, the value of the sample count register 13d, that is, the timer value, is compared with the random number N in the random number register 13e (305). The received data processing is repeated until the timer value becomes equal to or greater than the random number N (304, 305). When the timer value becomes equal to or larger than the random number value N, the reception data processing 304 has been performed a predetermined number of times determined by the random number value N, and the reception processing 204 ends.

As described above, the next reception processing 20 is performed using the count value of the random number counted in the reception data processing 304 a plurality of times, that is, the value of the counter register 13f.
Since the random number N that determines the number of times of sampling of the reception data processing 304 in Step 4 is calculated, the processing time of the reception processing 204 changes every time.

Returning to FIG. 2, when the receiving process 204 ends, the display process 205 starts. The CPU 11 transmits the received data in the work register 13a to the data register 13
Then, a comparison is made as to whether the data is the same as the data sent by itself in c. If they are the same, it means that the correct data has been received, and the CPU 11 moves the received data from the work register 13a to the reception register 13b. CPU1
1 converts 8-bit data of the reception register 13b into a 4-bit ID code, and each bit is "1".
, A low level signal (L) is sent to the display unit 6 when "0" is shown. The display unit 6 turns on and off four LEDs (Light Emitting Diodes) according to the level signal sent from the CPU 11 (205). When the correct data is not received, the values of the reception register 13b are all "0", so that all the signals to the display unit 6 are low level signals (L), and the LED of the display unit 6 , All remain extinct.

FIG. 6 shows how the transmitted data is received. FIG. 6A shows a frame.
(2) shows a reception control signal (Rxcont) for turning on / off the power of the receiving unit 5. (3) is C in the transmission / reception device 1.
A sample clock signal (Sample clock) of the PU 11 is shown, and a timing at which the CPU 11 takes in RxD is indicated by a rising portion of one signal. (4) indicates the received data (Rx
D) is shown. Also, (5) shows the CPU 1 of the transmitting / receiving device 1.
1 shows the processing content (Process).

In FIG. 6, after the transmission processing 203, the header demodulation processing 401 of the reception processing 204 is started. Since the transmitting / receiving device 31 is asynchronous with the transmitting / receiving device 32 on the receiving side, the receiving / receiving device 32 receives the signal (4).
Is a noise signal at the beginning. A header is detected after this noise. The process from the reception of this noise to the detection of the header is a header demodulation process, and the number of "1" bits detected during this period is stored in the counter register 13f. After detecting this header, the received data demodulation processing 4
03, and steps 304 and 305 in FIG.
As shown by, the reception data processing 304 is repeated by a predetermined number (the number of samplings determined by the random number N). The received data is composed of a header of a predetermined pattern, data indicated by four biphase signals added immediately after the header, and an error recovery EC.

FIG. 7 shows how two transmitting / receiving devices 31, 32 transmit and receive data to / from each other. The numbers shown below the transmission and reception indicate the respective processing times, and the transmission processing 203 has one processing number. The first transmission process 203 includes the transmission / reception devices 31, 3
2 is performed at the same timing,
04 is 3 (3 + 0) times in the transmission / reception device 31, and 5 (3 + 2) times in the transmission / reception device 32. here,
The first number "3"

## EQU1 ## is the "basic reception number", and the next added number is the "random number counter value".

As shown in FIG. 7, the length of the receiving process 204 is randomly changed by the "random number counter value" every time the process is performed. As a result, the transmission / reception timing of the transmission / reception devices 31 and 32 is shifted, so that data transmission / reception can be performed reliably.

FIG. 8 shows an example of a forced transmission process. In FIG. 8, regardless of the state of the transmitting / receiving device 1,
An ID code setting process, which is the same process as in steps 201 and 202 shown in FIG. 2, is performed, and an ID code for transmission is set (801). Next, a forced transmission key (not shown) attached to the input unit 3 is depressed (L), and a forced transmission signal is transmitted from the input unit 3 to the C of the control unit 2.
The data is sent to the PU 11 (802). The CPU 11 receives this forced transmission signal and performs the same transmission processing as in step 203 of FIG. In this case, the transmission process may be repeated while the forced transmission key of the input unit 3 is pressed down, or the transmission process may be performed a predetermined number of times and terminated (803). .

[0039]

FIG. 9 shows an embodiment of data transmission / reception by a plurality of transmission / reception devices 1 of the present invention. In FIG. 9, the transmission / reception device as a reference for data transmission / reception is the transmission / reception device 21 indicated by ○. Around the transmission / reception device 21, there are a plurality of transmission / reception devices 22 to 29 indicated by O and X. The transmission distance of data of each of the transmitting and receiving devices 21 to 29 is represented by r. Considering the transmission / reception device 21 as a reference, a circle 2 indicated by a dotted line with a radius r with the transmission / reception device 21 as the center.
The transmission / reception devices 22 to 25 indicated by a circle inside 0 are
Data can be transmitted to and received from the transmitting / receiving device 21;
The transmission / reception devices 26 to 29 outside the circle 20 cannot perform transmission / reception with the transmission / reception device 21.

The transmission / reception device 21 used as a reference receives data transmitted from the transmission / reception devices 22 to 25. If the ID of the received data is the same as its own ID,
The ID is displayed on the display unit 6 to notify that the other transmission / reception devices 22 to 25 exist in an area (within the circle 20) where data can be transmitted / received. Similarly, each of the transmission / reception devices 22 to 25 receives the ID transmitted by the transmission / reception device 21, and displays the ID of the transmission / reception device 21 on each display unit 6 when the received ID is the same as its own ID. At this time, the IDs of other transmitting / receiving apparatuses that can transmit and receive are also displayed in the same manner.

As described above, all the transmitting / receiving apparatuses 21 to 29
Are mutually transmitting and receiving data if they have the same ID. For reasons such as the manufacturing cost of the transmitting / receiving device,
All the transmission / reception devices 21 to 29 preferably have the same specifications, and in order to reduce the circuit scale, it is preferable that data transmission and reception be performed by time division multiplexing instead of frequency multiplexing.

FIG. 10 shows how data is transmitted and received by the transmitting and receiving apparatus 1 of the present invention. FIG. 10A shows a frame of data. (2) is transmission data (TxD) 9
1 and (3) indicate a transmission control signal (Txcont).
(4) shows the received data (RxD) 92 and (5)
Indicates a reception control signal (Rxcont). (6) indicates a reference clock (clk) in the transmission / reception device 1. Furthermore, (7)
Shows an outline of the transmission data (Txd) 91.

In (2) and (3) of FIG. 10, when the transmission control signal (3) is at the H level, the power of the transmission unit 4 is turned on, and the transmission (2) of the data 91 is performed. Similarly, in (4) and (5), when the reception control signal is at the H level, the power supply of the receiving unit 5 is turned on and the reception of the data 92 is performed (3). It should be noted that the reception data 92 requires more time than the transmission of the data, whereas the transmission data 91 only has one ID, while the reception data 92
This is because reception is performed from a plurality of other transmission / reception devices.

As is clear from (3) and (5) in FIG. 10, the H level of the transmission control signal and the H level of the reception control signal are alternately and periodically repeated. That is, at one point, the power of one of the transmitting unit 4 and the receiving unit 5 is turned on, and the other power is turned off. Further, although not shown in FIG. 9, when data is displayed on the display unit 6, both power sources are turned off. This power operation saves power.

In (7) of FIG. 10, as described above, the transmission data 91 has a header of a predetermined value added to the head of the data portion, and a bi-phase header is added after the header. The signal “0” is given.
The header transmitted by the receiving side can be detected by the header and the bi-phase signal “0”. At the end of the transmission data, a correction code EC (Error Cor
rection Cade) is provided so that a data error can be detected and corrected at the receiving end when data is received.

As described above, an example of the present invention has been described.
3 may be a memory having a general configuration instead of a configuration of a plurality of registers, and a memory area may be divided, and data storage and control may be performed by address control. Also,
It is not always necessary to provide the work register 13a. Furthermore, in the case of a CPU having a register file inside,
In particular, the register file in the CPU may be directly used without providing the RAM 13.

FIG. 6 generally shows that noise data is received before the header is detected. However, it may be considered that noise data is not received before the header is detected. Is the value of the counter register 13f is the number of "1" bits in the header portion. In addition, the transmission / reception device 1 can receive data having different header patterns. If there are a plurality of detectable headers, the reception period can be changed only by these header portions.

Further, in FIGS. 3 to 5, the addition processing of the value of the counter register 13f is performed until the header is demodulated, that is, from the detection of the noise signal to the detection of the header. It may be used, and when there are a plurality of detectable headers, only the value counted only in these header portions may be used.

[0049]

As described above, according to the transmitting / receiving apparatus of the present invention, the period of the receiving processing is changed by the number of "1" bits detected in the header demodulation processing. As a result, the timings of the transmission processing and the reception processing do not coincide, and data transmission and reception can be reliably performed between a plurality of small and simple transmitting / receiving apparatuses without adding a memory or the like.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a transmission / reception apparatus of the present invention.

FIG. 2 is an overall flowchart of a data transmission / reception process in the transmission / reception device of the present invention.

FIG. 3 is a flowchart of a reception process shown in FIG. 2;

FIG. 4 is a flowchart of the reception data processing shown in FIG. 3;

FIG. 5 is a flowchart of a header demodulation process shown in FIG. 4;

FIG. 6 is a time chart showing a state of reception of transmitted data.

FIG. 7 is a time chart showing a state of data transmission / reception between two transmission / reception devices of the present invention.

FIG. 8 is a flowchart of a forced transmission process.

FIG. 9 is a diagram showing one embodiment of data transmission / reception by a plurality of transmission / reception devices of the present invention.

FIG. 10 is a time chart showing how data is transmitted and received by the transmitting and receiving device of the present invention.

FIG. 11 is a time chart showing a state of data transmission / reception between two conventional transmission / reception devices.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 transmission / reception device 2 control unit 3 input unit 4 transmission unit 5 reception unit 6 display unit 11 CPU 12 ROM 13 RAM 13a work register 13b reception register 13c data register 13d sample count register 13e random number register 13f counter register 20 transmission / reception radius

Claims (3)

[Claims] 1. A setting unit for setting predetermined transmission data, a transmission unit for transmitting a transmission signal based on the transmission data, a reception unit for receiving a reception signal, and when the transmission unit transmits the transmission signal. Adding a header to the transmission data to form the transmission signal, detecting a header included in the transmission signal after the reception unit starts reception and a noise signal received before receiving the header, and detecting the noise. Control means for determining a period of the next reception by the receiving means in accordance with a signal. 2. The transmission / reception apparatus according to claim 1, wherein said control means determines a period of the next reception by said reception means according to said detected header. 3. The transmitting / receiving apparatus according to claim 1, wherein said control means determines a period of next reception by said receiving means in accordance with said detected noise signal and said header.