JPH118544A - Drive circuit and drive method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To deal with the fluctuations of bias voltage, when performing communication conforming to the Institute of Electrical and Electronic Engineers(IEEE) 1394. SOLUTION: A capacitor Cref is charged by a bias voltage in the high impedance state of cable, through which a differential signal is transmitted. further, at the time of bus reset, a digital value is outputted fro equalizing a common mode voltage as the average value of differential signal with a bias voltage, corresponding to the charge of capacitor Cref at an A/D converter 31. Then, at the time of differential signal output, the on/off of plural parallel-connected transistors p11-p1n and p21-p2n for turning on/off the current of differential signal is controlled, corresponding to that digital value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a drive circuit and a drive method, and more particularly to, for example, an IEEE (Inst.
itute of Electrical and Electronic Engineers) 13
The present invention relates to a drive circuit and a drive method suitable for driving a cable for a physical layer when performing communication conforming to a standard such as 94.

[0002]

2. Description of the Related Art For example, communication conforming to the IEEE 1394 standard uses a twisted pair cab (twisted pair cab).
This is done by biasing the cable and exchanging differential signals between the devices connected in le).

FIG. 8 shows a conventional communication system for performing such communication (a system is a group of a plurality of devices that are logically aggregated, and whether or not the devices of each configuration are in the same housing. Is not limited).

In this communication system, device D
EVICE 1 and DEVICE 2 are connected by a cable (twisted pair cable) 1.

In the device DEVICE1, a cable bias (Cable Bias) circuit 11 biases a pair wire 1A constituting the cable 1. That is, pair wire 1
One end of the device A connected to the device DEVICE1 is terminated by a series connection of two resistors RT as terminating resistors, and the cable bias circuit 1
Numeral 1 biases a connection point between two resistors RT as a terminating resistor to a predetermined bias voltage.

A drive circuit 112 is connected to one end of the pair wire 1A, which is biased by the cable bias circuit 11, on the device DEVICE1 side. The other end of the pair wire 1A is connected to a drive circuit 125 of the device DEVICE2, so that the drive circuit 112 of the device DEVICE1,
The drive circuit 125 of the device DEVICE2 operates by sharing the bias voltage from the cable bias circuit 11.

The drive circuit 112 generates a differential signal (a signal of 2) corresponding to information to be transmitted, and one of the signals is
(The other signal is inverted), and the differential signal is transmitted to the device DEVICE2 via the pair line 1A. One end of the pair line 1A on the device DEVICE2 side is connected to a bias circuit 125, a terminating resistor in which two resistors RT are connected in series and a receiver circuit 26, and from the drive circuit 112 via the pair line 1A. The supplied differential signal is received by the receiving circuit 26.

In the device DEVICE2,
The other end of a resistor R whose one end is grounded is connected to a connection point between two resistors RT as a terminating resistor of the pair line 1A.

The drive circuit 125 of the device DEVICE2 also outputs a differential signal corresponding to information to be transmitted, and the differential signal is transmitted to the device DEVICE1 via the pair line 1A. You. A receiving circuit 13 is also connected to one end of the pair line 1A on the device DEVICE1 side, and a differential signal supplied from the drive circuit 125 via the pair line 1A is received by the receiving circuit 13.

By the way, the device DEVI of the pair line 1A
At one end on the CE1 side, two resistors RT as a terminating resistor are provided.
In addition, a resistor in which two resistors RC as resistors for detecting a common mode voltage are connected in series is connected in parallel with the two resistors RT. The connection point between the two resistors RT is connected to a common mode signal detection circuit (Common Mode
pareator) 14 is connected to the non-inverting input terminal (+) of the comparator, and the inverting input terminal (−)
It is connected to a connection point between two resistors RT as a terminating resistor.

In IEEE1394, the average value of differential signals (the average value of the potentials of the two lead wires of a pair wire 1A (1B) composed of two lead wires when a differential signal is output (hereinafter referred to as the average value) , A common mode voltage) is set to a predetermined voltage, for example, a speed signal (IEEE1) as information on a data transmission rate.
394-1995)
The common mode signal detection circuit 1 is capable of transmitting a so-called common mode signal such as
At 3, the common mode signal is detected. For example,
In the receiving circuit 13, the common mode voltage detecting circuit 13
The differential signal from the device DEVICE2 is received as a data transmitted at a transmission rate corresponding to, for example, a speed signal as the common mode signal detected at the step S1.

The drive circuit 115 and the receive circuit 16 of the device DEVICE1 connected to the pair line 1B correspond to the drive circuit 125 and the receive circuit 26 of the device DEVICE2 described above. The part of the cable bias circuit 21, the drive circuit 122, the receive circuit 23, and the common mode signal detection circuit 24 of the device DEVICE2 connected to the line 1B is the same as the device DEVIC2 described above.
E1 cable bias circuit 11, drive circuit 11
2, since it corresponds to the receiving circuit 13 and the common mode signal detecting circuit 14, the description thereof is omitted.

The device DEVICE1 has two drive circuits 112 and 115, and the device DEVICE2 has a drive circuit 122.
And 125 are provided, for example, in order to transmit information about the clock in one drive circuit and transmit normal data in the other drive circuit. For the same reason, each device is also provided with two receive circuits.

[0014]

In the above communication system, as described above, two devices DEVIC are used.
Since the bias voltage is shared between E1 and DEVICE2, if there is a variation in the ground level between them, the bias voltage will also fluctuate.

That is, for example, the difference in ground level between the devices DEVICE1 and DEVICE2 is-
When the voltage is allowed in the range of 0.5 V to +0.5 V, for example, the bias voltage supplied by the cable bias circuit 11 in the device DEVICE1 is 1.8.
Assuming 5V, device DEVIC via pair line 1A
The bias voltage supplied to E2 ranges from 1.35V to 2.35V.
It changes in the range of 35V. In consideration of the variation in the characteristics of the cable bias circuit 11 itself, the bias voltage supplied to the device DEVICE2 further varies.

As described above, when the bias voltage fluctuates, the output current flowing through the drive circuit fluctuates, and the voltages of the two signals constituting the differential signal become unbalanced. That is, for example, in the above case, the device DEVI
The differential signal of the drive circuit 125 in CE2 becomes unbalanced. If the differential signals become unbalanced, the common mode voltage (the voltage of the common mode signal) changes, making it difficult to accurately transmit and receive the signals.

Therefore, for example, US Pat.
For example, FIG. 9 discloses a drive circuit for performing feedback for correcting an output current according to a received bias voltage, as shown in FIG.

In this drive circuit, a transistor (N-channel MOS (Metal Oxide Semiconductor))
FETs (Field Effect Transistors) 201 and 202 constitute a current mirror circuit for passing a current corresponding to one of the differential signals, and a transistor (N-channel MOS FET) 2
In 01 and 203, a current mirror circuit for flowing a current corresponding to the other signal constituting the differential signal is formed, and a predetermined output current flows by these current mirror circuits.

Then, two resistors RT as a terminating resistor
, That is, the bias voltage supplied from the communication partner is monitored by the operational amplifier 204, and the operational amplifier 205 controls the drain voltages of the transistors 202 and 203 constituting the current mirror circuit to be equal to the bias voltage. (P channel MO
By controlling the gate voltages of the SFETs 206 to 207, the imbalance of the differential signals does not occur even if the bias voltage fluctuates. The transistors 206 and 207 are for adjusting the current of the differential signal, and the transistors 208 and 209
Is for adjusting the current of the common mode signal.

In this drive circuit, a current mirror circuit is provided to allow a predetermined current to flow as a differential signal, and the transistors 202 and 203 constituting this current mirror circuit need to operate in a saturation region. is there. Therefore, for example, when the drain voltage of the transistors 206 and 207 increases due to a change in the bias voltage, the voltage between the drain and the source of the transistors 206 to 209 decreases, so that the transistors 202 and 203 operate in the saturation region. for,
It is necessary to reduce the voltage between the gate and the source of the transistors 206 to 209. And the transistor 20
It is necessary to use channels 6 to 209 having a large channel width so that a predetermined current can flow even under such conditions.

Furthermore, since the characteristics of the transistors 202 and 203 constituting the current mirror circuit usually have variations, the channel length of the transistors 206 and 207 needs to be increased in order to absorb the variations.

Therefore, it is necessary to use large transistors as the transistors 206 to 209.
This hinders a reduction in the power supply voltage and a reduction in the circuit area of the circuit, which is expected to proceed in the future.

The present invention has been made in view of such circumstances, and it is an object of the present invention to provide a small-sized drive circuit capable of coping with fluctuations in bias voltage.

[0024]

According to a first aspect of the present invention, there is provided a drive circuit comprising: a plurality of switching means connected in parallel for turning on / off a current; a converting means for converting a bias voltage into a digital value; Control means for performing control for turning on or off the corresponding switching means.

In the drive method according to the ninth aspect, when the drive circuit includes a plurality of switching means connected in parallel for turning on / off the current, the bias voltage is converted into a digital value, and the bias voltage is converted to a digital value. The switching means is turned on or off.

In the drive circuit according to the first aspect, the plurality of switching means are connected in parallel to turn on / off the current. The conversion means converts the bias voltage into a digital value, and the control means performs control to turn on or off the switching means corresponding to the digital value.

In the driving method according to the ninth aspect, the bias voltage is converted into a digital value, and a plurality of switching means connected in parallel for turning on / off a current corresponding to the digital value are turned on or off. It has been done.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below, but before that, the correspondence between each means of the invention described in the claims and the following embodiments will be clarified. For this reason, the features of the present invention are described as follows by adding the corresponding embodiment (however, an example) in parentheses after each means.

That is, the drive circuit according to claim 1 is
A drive circuit for passing a current corresponding to a differential signal to be transmitted to a communication partner connected via a cable biased to a predetermined bias voltage, wherein a plurality of switching circuits connected in parallel for turning on / off the current Means (for example,
Transistor shown in FIG. 2 (P-channel MOS FET)
p11 to p14, p21 to p24, p31 to p3
4, p41 to p44, and the transistors (p-channel MOS FETs) p11 to p1 shown in FIGS.
n, p21 to p2n, p31 to p3n, p41 to p4n), and a conversion means (for example, an up / down counter (32) shown in FIG. 2) for converting a bias voltage into a digital value, and a conversion means shown in FIG. An AD converter (AD (Analog Digital) Converter) 31 and an up / down counter 32, the AD converter 31 shown in FIG. 6 and FIG. ,
The up-down counter 32 shown in FIG.
(D converter 31 and up / down counter 32, AD converter 31 shown in FIGS. 6 and 7).

In the drive circuit according to the present invention, the conversion means converts the bias voltage into a digital value by A / D conversion (for example, A / D conversion means shown in FIG. 3).
Counting means for incrementing or decrementing a count value as a digital value based on the magnitude relationship between the average value of the differential signal and the bias voltage (for example, the up / down counter 32 shown in FIG. 3) ), And the digital value output from the A / D conversion means is used as the initial value of the count value of the counting means.

The drive circuit according to claim 7 is a storage means for storing a bias voltage when the cable is in a high impedance state (for example, a capacitor Cre shown in FIG. 3).
f etc.), wherein the conversion means converts the bias voltage stored in the storage means into a digital value.

In the drive circuit according to the present invention, when the cable is in a high-impedance state, the current control means (the transistor shown in FIG. 7) for supplying a current corresponding to a monitor differential signal in accordance with a digital value. (P channel MO
S FET) p51 to p5n, p61 to p6n), and the conversion means outputs a digital value for making the bias voltage equal to the average value of the differential signal for monitoring by the current control means. I do.

According to a ninth aspect of the present invention, there is provided a drive method for a drive circuit for flowing a current corresponding to a differential signal transmitted to a communication partner connected via a cable biased to a predetermined bias voltage. A plurality of switching means (for example, transistors p11 to p14, p21 to p24, and p31 to p3 shown in FIG. 2) connected in parallel so that the drive circuit turns on / off the current.
4, p41 to p44 and the transistors p11 to p1n, p21 to p2n, and p31 shown in FIGS. 3, 6, and 7.
, P3n, p41 to p4n), the bias voltage is converted into a digital value, and the switching means corresponding to the digital value is turned on or off.

Of course, this description does not mean that each means is limited to those described above.

FIG. 1 shows a configuration example of an embodiment of a communication system to which the present invention is applied. In FIG. 8, FIG.
The same reference numerals are given to the portions corresponding to the case in. That is, this communication system is basically the same as the communication system of FIG. 9 except that drive circuits 12, 15, 22, or 25 are provided instead of drive circuits 112, 115, 122, or 125, respectively. It is configured similarly.

Here, the drive circuits 12, 15, 22,
And 25 have the same configuration here, so that only the drive circuit 12 will be described below.

FIG. 2 shows a configuration example of the drive circuit 12 of FIG. The drive circuit 12 is, for example, a CMOS and is configured as a one-chip IC. Further, in FIG. 2 (the same applies to FIGS. 3, 6, and 7 described later), the transistor (FE
In T), those with a circle indicating inversion at the gate are P-channel MOS FETs, and those without the mark are N-channel MOS FETs.

The up / down counter 32 is, for example, 4
A bit counter increments or decrements the count value at the timing of an input signal to the clock terminal (CK). In addition,
Whether to increment or decrement the count value is determined by an input signal to its up / down terminal (U / D).

The count value of the up / down counter 32 is determined by the NAND gates 34 _{1 to} 34 ₄ and 35 _{1 to} 3
5 ₄ is adapted to be supplied to. That is, the LSB of the 4-bit count value of the up / down counter 32
(0th bit), 1st bit, 2nd bit, MSB (3rd bit) are NAND gates 34 _{1 to} 34 ₄ and 3
It is adapted to be supplied to one input terminal of the 5 ₁ to 35 _4.

[0040] NAND gate 34 ₁ to 34 ₄ and the other input terminal, to both, when communicating, for example, H (High)
Level, and at other times, the signal TpEn which is at the L (Low) level is supplied.
Here, when the signal TpEn is at the H level, data (hereinafter, appropriately referred to as differential data) TpD or TpDX which is a differential signal to be transmitted to a communication partner is supplied to each of the inverters 36 and 37 described below. It has been made like that. The differential data TpD and TpDX are, for example, such that when one of them is 1, the other is 0.

The output terminal of the NAND gate 34 ₁ to 34 _4, a plurality of transistors p connected in parallel to the power supply
11 to p14 and transistors p21 to p21
It is connected to 24 sets of gates.

The transistors p11 to p14 are for pull-up, and their sources are all connected to the power supply, and their drains are all connected to the drain of the transistor 38. The differential data TpD is supplied to the gate of the transistor 38 via the inverter 36. Therefore, the transistor 38 is turned on / off in accordance with the differential data TpD.
It has been made to turn off.

The source of the transistor 38 is the transistor N1 which forms a current mirror circuit with the transistor N1.
2 and the source of the transistor N2 is grounded. The gate of the transistor N2 is connected to the gate of the transistor N1 whose source is grounded, and the gate of the transistor N1 is connected to its drain. The connection point between the gate and the drain of the transistor N1 is connected to the drain of the transistor 40 whose source is connected to the current source Iref. The drive circuit 12 is connected to the gate of the transistor 40.
Is enabled or disabled (di
sable) signal is supplied. Here, the signal Active is
For example, when the drive circuit 12 is at the L or H level,
Is enabled or disabled
Each is made to be in a state.

Here, when the transistor 40 is turned on, the transistors N1 and N2 constituting the current mirror circuit operate, whereby a current corresponding to the differential data TpD flows through the transistor 38. The drain of the transistor 38 and the transistor p1 connected in parallel
The signal at the connection point between the drains 1 to p14 is output as one of the differential signals Tp.

Similarly to the transistors p11 to p14, the transistors p21 to p24 are for pull-up. All of the sources are connected to the power supply, and the drains are all the drains of the transistor 39. Is connected to The differential data TpDX is supplied to the gate of the transistor 39 via the inverter 37. Therefore, the transistor 39 is turned on / off in accordance with the differential data TpDX. .

The source of the transistor 39 is the transistor N1 which forms a current mirror circuit with the transistor N1.
3 and the source of the transistor N3 is grounded. Further, the gate of the transistor N3 is connected to the gate of the transistor N1, like the gate of the transistor N2. Therefore, when the transistor 40 is turned on, the transistors N1 and N3 constituting the current mirror circuit operate, thereby
The current corresponding to the differential data TpDX is the transistor 3
Flow to 9. A signal at a connection point between the drain of the transistor 39 and the drains of the transistors p21 to p24 connected in parallel is output as the other signal TpX of the differential signal.

The output terminal of the signal Tp and the signal TpX
Connected in series with two resistors RC for detecting a common mode voltage and a bias voltage from a communication partner.

Here, the transistors N2 and N3 are
For example, in each case, a current of 8 mA flows. The transistors p11 to p1 connected in parallel
The set of 4 and the set of transistors p21 to p24 are:
For example, in each case, a current of 4 mA flows.

A set of transistors p11 to p14
, The width of the channel of the transistor p11 is W
Then, the width of the channel of the transistors p12 to p14
Is 2 ¹W, 2^TwoW, 2^ThreeW respectively. to this
Therefore, each of the transistors p12 to p14 is simply
By turning on alone, only transistor p11 is turned on.
2 compared to when¹, 2^Two, 2^ThreeApply twice the current
It has been made like that. That is, when the signal TpEn is at the H level
At this time, the transistors p11 to p14 connected in parallel
Means that the count value of the up / down counter 32 becomes 1
Only the bit corresponding to the bit
The current corresponding to the count value of
You. As described above, the transistors p11 to p14 are
Essentially, it works as a switch, but the channel width is
As described above, the power corresponding to the count value
It is made to flow.

The transistors p21 to p24 have the same configuration as the transistors p11 to p14. Therefore, when the signal TpEn is at the H level, a current corresponding to the count value of the up / down counter 32 flows. I have.

Transistors p11 to p14 or p2
Since the currents flowing from 1 to p24 flow through the transistors 38 and N2 or 39 and N3, the currents of the signals Tp and TpX change according to the count value of the up / down counter 32.

Each of the other input terminals of the NAND gates 35 _{1 to} 35 ₄ is supplied with, for example, a speed signal SpdSig as one of the common mode signals. Speed signal SpdSig
Sets the transmission rate to, for example, 100 Mbps or 20 Mbps.
When it is set to 0 Mbps, it is set to the L or H level, respectively.

The output terminals of the NAND gates 35 _{1 to} 34 ₄ are connected to a plurality of transistors p connected in parallel to a power supply.
31 to p34 and transistors p41 to p41
It is connected to 44 sets of gates.

The transistors p31 to p34 are used to change the voltage of the common mode signal. All of the sources are connected to the power supply, and all of the drains are connected to the drain of the transistor 38. Have been.

Similarly to the transistors p31 to p34, the transistors p41 to p44 are for changing the voltage of the common mode signal. All of the sources are connected to the power supply, and all of the drains are connected to the power supply. , And the drain of the transistor 39.

Here, transistors p31 to p34
Is similar to the transistors p11 to p14 from the viewpoint of a switch for adjusting the current flowing through the transistor 38, but is based on the bias fluctuation in that the change in the voltage of the common mode signal due to the bias fluctuation is compensated. This is different from transistors p11 to p14 which compensate for a change in the voltage of the differential signal Tp. Therefore, the transistor p
The ratio of the channel widths of 31 to p34 is
11 to p14, but the current flowing when outputting a differential signal and the current flowing when outputting a common mode signal are generally different.
Through p34, the width of each channel is
The width is different from the width of each of the channels 11 to 14. That is, when the transistors p11 to p14 flow a pull-up current of, for example, 4 mA when outputting a differential signal, the transistors p31 to p34 need to flow a pull-up current of, for example, 0.5 mA when outputting a common mode signal. In some cases, transistors p31 to p34
The width of each channel and the transistors p11 to p11
The ratio of each channel to the width of each channel is 1: 8, which is the current ratio.

Accordingly, in this case, if the channel width of the transistor p11 is represented by W as described above, the channel width of each of the transistors p31 to p34 is 2 ⁰
W / 8,2 and has a ^{1 W / 8,2 2 W / 8,2} 3 W / 8.

It should be noted that the above is the same as the transistor p41.
The same applies to p44 to p44.

The connection point between the two resistors RC for detecting the common mode voltage and the bias voltage is connected to transmission gates 41 and 42. Transmission gates 41 and 42 each include an N-channel MOSFET and a P-channel MOSFET whose sources and drains are connected to each other, and an inverter that connects the gates of the two FETs. Signal Idle
Alternatively, the output of the NOR gate 44 is supplied. The transmission gate 41 or 42 is connected to the signal Idle or the NOR gate 4 respectively.
4 is, for example, H level or L level,
The conductive state or the insulated state is set.

Here, the signal Idle is set to the H level only when the cable 1 is in the high impedance state, and is set to the L level otherwise.

Transmission gate 41 or 42
Are turned on, the respective outputs are supplied to one end of a capacitor Cref whose other end is grounded or to the inverting input terminal (-) of the comparator 45. And the capacitor Cref
The connection point between the transmission gate 41 and the non-inverting input terminal (+) of the comparator 45 is connected.
The comparator 45 compares the voltage of the non-inverting input terminal with the voltage of the inverting input terminal. If the voltage of the non-inverting input terminal is higher than the voltage of the inverting input terminal, the comparator 45 sets the H level. The L level is output as a signal UD. The signal UD is supplied to an up / down terminal (U / D) of the up / down counter 32.

One input terminal of the NOR gate 44 has
The speed signal SpdSig and the signal TpEn are supplied to the other input terminal via the inverter 43, respectively. Therefore, the NOR gate 44 goes high only when the signal TpEn is high and the speed signal SpdSig is low, so that the transmission gate 42 is turned on.

The speed signal SpdSig is also supplied to one input terminal of a three-input NAND gate 47 via an inverter 48.
7, a clock CK and a signal TpEn are supplied to the remaining two input terminals. And NAND gate 4
The output of 7 is supplied to the clock terminal (CK) of the up / down counter 32 via the inverter 49.

Next, the operation of drive circuit 12 shown in FIG. 2 will be described.

Enable drive circuit 12
The signal Active to be in the state changes from H level to L
At that level, transistor 40 is turned on, thereby allowing transistors N1 and N2 and N3 to allow a pull-down current to flow through transistors 38 and 39.

When the cable 1 is in the high impedance state, the H-level signal Idle is supplied to the transmission gate 41 as described above.
Becomes conductive. The transmission gate 41
As described above, since the transmission gate 41 is connected to the connection point of the two resistors RC and the transmission gate 41 is turned on, the voltage at the connection point, that is, in this case, the cable 1 is set to the high impedance state. Therefore, the bias voltage output from the cable bias circuit 11 is applied to the capacitor Cref. As a result, the capacitor Cref is charged with a charge corresponding to the bias voltage.

When the signal Idel is at the H level, the differential signal is not transmitted and received, so that the signal TpEn is at the L level. Therefore, the signal TpE
Since n is supplied to one input terminal via the inverter 43 and the output of the NOR gate 44 is at L level, the transmission gate 42 is in an insulated state. Further, in the NAND gate 47 in which the signal TpEn is supplied to one of the three input terminals, the clock CK is masked by the signal TpEn, so that the output level does not change from the H level. , The up / down counter 32 does not operate.

[0068] The output of the NAND gate 34 ₁ to 34 ₄ which signal TpEn is supplied to one input terminal H
Level, and thus the transistors p11 to p14
And p21 to p24 are all turned off.

Further, when the signal Idel is at the H level, the speed signal SpdSig is set at the L level, so that the speed signal SpdSig is supplied to one of the input terminals.
The outputs of the ND gates 35 _{1 to} 35 ₄ are at the H level, whereby the transistors p31 to p34 and p41
To p44 are all turned off.

When the differential signal is output, the signal Id
le or TpEn is set to L or H level, respectively, and the speed signal SpdSig is kept at L level. When the signal Idle goes to L level, the transmission gate 41 is insulated and the capacitor Cr
A voltage corresponding to the electric charge charged to ef, that is, a bias voltage of the cable is applied to the non-inverting input terminal of the comparator 45.

When the signal TpEn goes high,
One input terminal of the NOR gate 44 has an inverter 4
The L level is supplied via 3. Further, since the L-level speed signal SpdSig is supplied to the other input terminal of the NOR gate 44, the output of the NOR gate 44 becomes H-level. As a result, the transmission gate 42 becomes conductive.

[0072] On the other hand, when the signal TpEn becomes H level, among the NAND gates 34 ₁ through 34 _4, of the count value of the up-down counter 32, the output of which corresponds to a bit that is a 1 and the L level Become. In this case, among the set of transistors p11 to p14, the one whose L level is supplied to the gate is turned on, and the set of transistors p21 to p24 whose L level is supplied to the gate is also turned on. Accordingly, a state in which a pull-up current can flow through the transistor 38 or 39 is established.

Then, the differential data TpD and TpDX
Of the differential data TpD or Td
The pDX is supplied to the gate of the transistor 38 or 39 via the inverter 36 or 37, respectively, whereby the transistor 38 or 39 turns on / off in response to the differential data TpD or TpDX.

As described above, the transistor 38 or 39
Signal Tp or T corresponding to the current flowing through
pX is output to cable 1.

In this case, the voltage at the connection point of the two resistors RC is the average value of the differential signals Tp and TpX, that is, the common mode voltage, which is in the conductive state as described above. The signal is applied to the inverting input terminal of the comparator 45 via the transmission gate 42.

The comparator 45 includes a capacitor Cref
A bias voltage, which is a voltage corresponding to the electric charge stored in the memory, is compared with a common mode voltage supplied via the transmission gate 42. If the bias voltage is higher than the common mode voltage, the H level is set. Output the L level. The output of the comparator 45 is supplied to an up / down terminal (U / D) of the up / down counter 32 as a UD signal.

Here, when the UD signal supplied to the up / down terminal (U / D) is at H level or L level, the up / down counter 32 outputs the clock terminal (CK).
The count value is incremented or decremented by 1 at the timing of the rising edge or the falling edge of the input to. In this case, since the signal TpEn is at the H level and the speed signal SpdSig is at the L level, the output of the NAND gate 47 is an inverted version of the clock CK. However, if the bias voltage is higher than the common mode voltage, it is incremented according to the clock, otherwise, it is decremented according to the clock.

As described above, the set of transistors p11 to p14 and the set of transistors p21 to p24 are turned on / off according to the count value, and the ratio of their channel widths is 2 as described above. Since the power is raised to a power, the pull-up current corresponding to the count value flows according to the set of transistors p11 to p14 or the set of transistors p21 to p24.
That is, thereby, the current corresponding to the differential signal Tp or TpX changes, and the common mode voltage that is the voltage at the connection point of the two resistors RC changes.

As described above, this common mode voltage is supplied to the comparator 45 via the transmission gate 42. Hereinafter, this common mode voltage corresponds to the charge charged in the capacitor Cref. The same processing is repeated until the voltage becomes equal to (approximately equal to) the bias voltage in the high impedance state.

Finally, a digital value for equalizing the common mode voltage and the bias voltage is output from the up / down counter 32 as a count value, and the set of transistors p11 to p14 or the transistor In each of the sets of p21 to p24, the transistor corresponding to the count value turns on,
As a result, the common mode voltage becomes (almost) equal to the bias voltage.

Thereafter, when a speed signal SpdSig, for example, is output as a common mode signal, the speed signal SpdSig is set to the H level. When the speed signal SpdSig becomes H level, the speed signal SpdSig becomes N level supplied through the inverter 48.
In the AND gate 47, the speed signal Spd
The clock CK is masked by Sig, and its output level remains at H level and does not change, so that the up / down counter 32 stops operating. That is, in this case, the up / down counter 32 outputs the speed signal S
The operation is stopped while the count value immediately before the pdSig becomes H level is held. Here, it is assumed that the speed signal SpdSig has already been set to the H level after the bias voltage and the common mode voltage have become substantially equal.

When the speed signal SpdSig is H
Level, the NAND gates 35 ₁ through 35 3
Of 5 _4, the output of which corresponds to a bit that is a 1 in the count value of the up-down counter 32 becomes L level. In this case, the transistors p31 to p34
Of the sets, the one whose L level is supplied to the gate is turned on, and also the set of transistors p41 to p44 whose L level is supplied to the gate is turned on.

As described above, since the width of the channel of each of the transistors p31 to p34 and p41 to p44 corresponds to the pull-up current flowing to output the common mode signal, it is held by the up-down counter 32. The transistors p31 to p34 and p41 to p44 are turned on in accordance with the count value (as described above, the count value that makes the bias voltage and the common mode voltage substantially equal), so that the common mode voltage fluctuates by the specified value. Of the pull-up current flows.

As described above, the transistors p11 to p11
Since 14, p21 to p24, p31 to p34, and p41 to p44 function as switches, the length of the channel (corresponding to the length of the gate) can be set to a minimum necessary value. Therefore, the size of these transistors can be reduced, and as a result, when the drive circuit is configured by CMOS or the like, the layout area can be significantly reduced.

Further, when a differential signal is output, the common mode voltage is controlled by feedback so that unnecessary current as a common mode signal does not flow, so that power consumption can be reduced. Becomes

Further, a common mode voltage when a differential signal is output and a common mode voltage (bias voltage) when the cable 1 is in a high impedance state are compared, and feedback is applied so that the two become equal. By controlling the pull-up current, it is possible to cope with a wide range variation of the common mode voltage and to cope with a low voltage power supply.

In the above description, on the pull-up side,
Transistors p11 to p14, p21 to p24, p3 as switches connected in parallel for controlling current
Although 1 to p34 and p41 to p44 are provided, such a transistor as a switch can be provided on the pull-down side, and further, can be provided on both the pull-up side and the pull-down side. is there. However, for example, in a circuit for driving a differential signal, such as the drive circuit 12 shown in FIG. 2, it is particularly problematic that the H level voltage of the differential signal Tp or TpX decreases due to bias fluctuation. Therefore, it is desirable that the switch connected in parallel for controlling the current be provided on the pull-up side.

Further, in the above description, the transistors are used as the switches connected in parallel for controlling the current. However, other devices can be used.

In the above case, the differential signal T
In order to turn on / off the current (pull-up current) as p or TpX, four transistors p11 to p1
Although four or p21 to p24 are used in parallel, the number of transistors connected in parallel is not limited to four. That is, the number of transistors connected in parallel for turning on / off the current is, for example, the power supply voltage, the fluctuation range of the common mode voltage at the time of differential signal output, and the change of the common mode voltage due to turning on / off the speed signal SpdSig. In response to
Preferably, the number is appropriate. This means that the transistors p31 to p34 operating at the time of outputting the common mode signal
The same applies to the set of and the set of p41 to p44.

Further, for example, the transistors p11 to p11
In the fourteenth set, the ratio of the widths of the channels is a power of two, but the widths of these channels can be the same. However, the transistor p11
Or in the case where the ratio of the width of the channel of the p14 2 powers and, based on the current flowing when the transistor p11 is turned on, it is possible to flow until the about 2 ⁴ times the current channel Are the same, the current can flow only up to four times the current that flows when the transistor p11 is turned on, for example. Further, in this case, the up / down counter 32
Needs to be a 2-bit value, and it is necessary to convert the 2-bit output (count value) into a 4-bit value in which the number of bits corresponding to the output is only 4 bits.

In the above case, for example, one or more of the transistors p11 to p14 are turned on in accordance with the count value of the up / down counter 32. It is also possible to turn off one or more of the transistors p11 to p14 according to the value.

The drive circuit 12 shown in FIG.
Then, after the output of the differential signal is started, the count value in the up / down counter 32 is incremented or decremented in accordance with the comparison result between the bias voltage and the common mode voltage in the comparator 45, and the bias voltage and the common mode voltage So that
The transistors p11 to p14 and p21 to p24 are turned on, but the count value of the up / down counter 32 is incremented or decremented by one each time the comparator 45 outputs a comparison result between the bias voltage and the common mode voltage. Will be Therefore,
After the output of the differential signal is started, it may take time for the bias voltage and the common mode voltage to become equal. Specifically, for example, when the initial value of the up / down counter 32 is 0000B (B indicates that the preceding number is a binary number), the transistor p1
1 to p14 and transistors p21 to p21
24, when the count value is 11
Assuming that the bias voltage and the common mode voltage become equal at the time of 11B, at least 15 clocks (1111B) are required until the count value becomes such a value.
Clock).

This time is determined by the transistors that perform on / off control based on the count value of the up / down counter 32 (transistors p11 to p11 in FIG. 2).
14 and the number of transistors p21 to p24).

If the time required for the bias voltage and the common mode voltage to be equal to each other is long as described above, accurate transmission and reception of data during the time is not preferable, as described above.

FIG. 3 is a circuit diagram of the drive circuit 12 shown in FIG.
2 shows a second configuration example. In the figure, portions corresponding to those in FIG. 2 are denoted by the same reference numerals, and a description thereof will be omitted as appropriate below.

That is, in the embodiment of FIG. 3, each of the NAND gates 34 or 35 is provided with n, instead of four. Correspondingly, the set of transistors connected to the output terminal is also
11 to p1n, p21 to p2n, p31 to p3
and n transistors p41 to p4n. Note that, also in this case, the transistors p11 to p1
The width of each of the n channels has, for example, the relationship described with reference to FIG. Transistors p21 to p2
The same applies to n, p31 to p3n, and p41 to p4n. Further, the relationship between the channel widths of the transistors p31 to p3n and the transistors p11 to p1n is, for example, the relationship described with reference to FIG. The same applies to the transistors p41 to p4n.

Further, in the embodiment shown in FIG. 3, an AD converter 31 is provided. Here, the AD converter 31 includes transistors p11 to p1n, p2
Together with 1 to p2n and the comparator 45, a successive approximation type AD converter is configured. That is, the successive approximation type AD converter converts an analog value into a DA
A comparator for comparing with a DA conversion result of the converter, a successive approximation control circuit for outputting a digital value corresponding to the comparison result of the comparator, and a DA for DA converting the digital value
And outputs the output value of the successive approximation control circuit when the comparison result in the comparator becomes equal as the AD conversion result of the input analog value. The AD converter 31 in FIG. Of the successive approximation control circuit. The transistors p11 to p1n and p21 to p2n in FIG. 3 or the comparator 45 correspond to a DA converter or a comparator in a successive approximation type AD converter, respectively.

The AD converter 31 outputs a digital value of n bits (n is an integer of 2 or more) to an output terminal (F1,
F2,..., Fn). The n-bit digital value is input to the initial value input terminals (F′1, F′2,.
F'n), and is adapted to be supplied to the selector 33 ₁ to 33 _n each one input terminal (I1).

The AD converter 31 changes the digital value output from its output terminal in accordance with the input to its clock terminal (CK). The clock terminal has an AND gate. Fifty outputs are provided. The AND gate 50 is connected to the inverter 49 connected to the clock terminal (CK) of the up / down counter 32 in FIG.
And the NAND gate 47 are integrally shown.

Here, the AD converter 31 has its BR
The circuit operates in response to a signal input to the terminal, and the output of the AND gate 46 is supplied to the BR terminal. The AD converter 31 has an END terminal. The output of the END terminal is normally at L level, for example, but the digital value corresponding to the voltage at the non-inverting input terminal of the comparator 45 is Only when outputting from the output terminal (as will be described later, when a digital value is determined), for example, the signal is set to the H level.

The up / down counter 32 is basically configured in the same manner as in FIG. 2, but in the embodiment of FIG. 3, an n-bit up / down counter is used instead of a 4-bit up / down counter. Have been. Further, in the embodiment shown in FIG.
2 has a BR terminal and an END terminal. The up / down counter 32 operates in response to signals input to its BR terminal and END terminal. The output of the AND gate 46 is output to the BR terminal, and the AD converter is output to the END terminal. The outputs of the 31 END terminals are respectively supplied.

As described above, the output terminal of one of the input terminals of the AND gate 46 connected to the BR terminal of the AD converter 31 and the BR terminal of the up / down counter 32 or the other input terminal is the signal TpDA or TpD.
B are supplied respectively. here,
As described above, the devices DEVICE1 and DEVIC
E2 has two drive circuits, and the signals TpDA and TpDB correspond to the differential signal Tp output from the two drive circuits. That is, for example, the device DEVIC
Paying attention to E1, the signal TpDA is
Corresponds to the differential signal Tp output from the driver circuit 15, and the signal TpDB is a differential signal (driver circuit 12) output from the driver circuit 15.
Corresponds to the differential signal Tp output).
The signals TpDA and TpDB are output from the device DE.
VICE1 is set to H level during a bus reset period, which is a predetermined period immediately before starting output of a differential signal as actual data.
Therefore, during the bus reset period, the AND gate 4
6 becomes H level (in other periods,
Basically it becomes L level).

The n-bit output terminals (Q1, Q2,..., Qn) of the up / down counter 32
_{1 to} 33 _n are connected to the other input terminals (I0). The selector 33 ₁ to 33 _n each selected terminal (S), have been made such that the output of the AND gate 46 is supplied, the selector 33 ₁ to 33 _n are input to the selection terminal (S) L Level or H level,
One input terminal (I0) or the other input terminal (I
1) Select each of the signals input to the
Gates 34 _{1 to} 34 _n and one input terminal of NAND gates 35 _{1 to} 35 _n are supplied.

Next, FIG. 4 shows the AD converter 31 of FIG.
Is shown.

One input terminal of the NAND gate 51 has a clock CK supplied to a clock terminal (CK).
The output of the AND gate 46 supplied to the BR terminal (hereinafter, appropriately referred to as a BR signal) is supplied to the other input terminal, respectively.
In the AND gate 51, a signal obtained by inverting the logical sum of the clock CK and the BR signal is obtained and supplied to the clock terminals of DFFs (D flip-flops) 51 _{1 to} 54 _{n + 1} via the inverter 52.

[0106] Here, BR signal, as described above, since the H level only in the bus reset period, to the clock terminal of the 51 ₁ to 54 n _{+ 1,} only the bus reset period,
Clock CK is supplied.

The BR signal is supplied to NOR gates 58 _{1 to} 5 via a pulse generator (1 Shot Pulse Generator) 53 and an inverter 57 in addition to the NAND gate 51.
It is supplied to one input terminal of the 8 _n. The pulse generator 53 converts the BR signal from L level to H level, for example.
At a timing (rising edge) when the level becomes, for example, one pulse (one-shot pulse) having a width corresponding to the cycle of the clock CK is output, and this one-shot pulse is input to the DFF 54 _{n + 1} . It is supplied to the terminal (D). Therefore, the DFF 54 _{n + 1} latches the one-shot pulse (1) output from the pulse generator 53 immediately after the start of the pass reset period.

The output terminal (Q) of the DFF 54 _{n + 1} is connected to the DF
F54 is connected to the input terminal (D) of _n, In the same manner, Dff 54 _n to Dff 54 ₁ is connected in series. Therefore, 1 (one-shot pulse) (H level) latched by the DFF 54 _{n + 1} is applied to the clock C
In synchronization with K, the data is sequentially latched by the DFFs 54 _{n to} 54 ₁ . DFF54 ₁ of the output terminal (Q) is, EN
D terminal, so that the AD converter 31
After the start of the bus reset period, n +
At the first clock, the H level is output.

[0109] DFF54 output terminal of the _{n + 1} to 54 _2, D
The clock terminals of the FFs 59 _{n to} 59 ₁ are also connected to each other, and the clear terminals (reset terminals) (CL) of the DFFs 59 _{n to} 59 ₁ have inverted outputs of the NOR gates 58 _{n to} 58 _1. Are respectively input. The other input terminal of the NOR gate 58 _n to 58 ₁ are respectively connected to the output terminal of the AND gate 56 _n to 56 _1, also, the AND gate 56 _n
To the one input terminal of the 56 _1, via the inverter 55, UD signal is adapted to be supplied. The other input terminals are connected to the output terminals of the DFFs 54 _{n to} 54 ₁ , respectively.

The power supply voltage (H level) is applied to the input terminals (D) of the DFFs 59 _{n to} 59 ₁ .
The output terminals (Q) are connected to the input terminals (D) of the DFFs 60 _{n to} 60 ₁ , respectively. DFF60
The clock terminals _{n to} 60 ₁ are connected to the output terminal of the inverter 52, and the output terminal (Q) is connected to the output terminal (Fn (MSB), Fn−1,.
.., F1 (LSB)).

AD converter 3 configured as described above
At 1 in the bus reset period, since the BR signal changes from L level to H level, a pulse is output from the pulse generator 53, latched by the DFF 54n _{+ 1} , and output from its output terminal (Q). . The latch output, since supplied to the clock terminal of the DFF59 _n, the DFF59 _n, H level is latched. DF
The latch output of F59 _n (output of output terminal (Q)) is D
The signal is supplied to the input terminal (D) of the FF 60 _n , and therefore, the latch output of the DFF 60 _n , that is, the output of the output terminal Fn becomes H level (1).

At the timing of the next clock CK, for example, when the UD signal goes to the H level, an inverted version of the UD signal and the output of the DFF 54 _n are supplied to the input terminal of the AND gate 56. The output of _n becomes L level. Further, during the bus reset period, since the BR signal is at the H level, the output of the NOR gate 58 _n in which the BR signal via the inverter 57 and the output of the AND gate 56 _n are supplied to the input terminal is It becomes H level. Therefore, the output of the NOR gate 58 _n is inverted and the DFF 59 _n supplied to the clear terminal is not reset, and as a result, the latch output of the DFF 60 _n is fixed at H level (1).

In the DFF 59 _n-1 in which the output of the DFF 54 _n is supplied to the clock terminal, the H level is latched. As a result, the output of the DFF 60 _n-1 ie the output of the output terminal Fn-1 is H level. Level (1) is reached.

On the other hand, after the latch output of the DFF 60 _n goes high, at the next clock CK timing, for example, when the UD signal goes low, UD
The output of the AND gate 56 _n , whose inverted signal and the output of the DFF 54 _n are supplied to the input terminal, goes high. Further, during the bus reset period, BR
Since the signal is at the H level, the output of the NOR gate 58 _n in which the BR signal via the inverter 57 and the output of the AND gate 56 _n are supplied to the input terminal is at the L level. Therefore, the output of the NOR gate 58 _n is inverted and the DFF 59 _n supplied to the clear terminal is reset, and as a result, the latch output of the DFF 60 _n is fixed at L level (1).

The output of the DFF 60 _n-1 is at the H level (1) as described above.

In the same manner, the latch outputs of the DFFs 60 _{n-1 to} 60 ₁ are successively determined in accordance with the level of the UD signal.
4 _first latch output, i.e., END of the AD converter 31
The output of the terminal becomes H level.

When the BR signal goes low due to the elapse of the bus reset period, no clock is supplied to the DFFs 54 _{1 to} 54 _{n + 1} and 60 _{1 to} 60 _n , and the AD converter 31 stops operating. Stop.

Next, FIG. 5 shows a configuration example of the up / down counter 32 of FIG.

XNOR (eXclusive NOR) 61 _{n to} 61
_One of the input terminals is connected to initial value input terminals (F′1, F′2,..., F′n) of the up / down counter 32, respectively. Also, XNORs 61 _{n to} 61 ₁
Are connected to the output terminals (Q) of the DFFs 71 _{n to} 71 ₁ , respectively. And XNOR6
1 output terminals of _n to 61 _1, n-input NAND gate 62
Is connected to the input terminal of An output terminal of the NAND gate 62 is connected to one input terminal of the three-input NAND gate 64. The clock CK and the latch output of the DFF 63 are supplied to the other two input terminals of the NAND gate 64.

The DFF 63 is an up / down counter 32
H level is latched in synchronization with the input from the END terminal. The clear terminal (CL) of the DFF 63 is supplied with an inverted version of the BR signal.

An output terminal of the NAND gate 64 is connected to one input terminal (I1) of the selector 66.
The clock CK is supplied to the other input terminal (I0) via the inverter 65.
Then, the selector 66 responds to the BR signal by
The output of one of the D gate 64 and the inverter 65 is selected and output. The output of the selector 66 is supplied to the DFF 7 via the inverter 68.
The clock signals are supplied to clock terminals 11 _{1 to} 71 _n .

An H level is supplied to one input terminal (I1) of the selector 67, and a UD signal is supplied to the other input terminal (I0). The selector 67, like the selector 66,
One of the H level and the UD signal is selected and output. The output of the selector 67, full adder 70 ₁ carry (carry) input terminal (Ci)
And full adders 70 _{1 to} 70 _n via an inverter 69
And the second input terminal (A2).

[0123] full adder 70 ₁ to 70 _n-1 carry output terminal (Co) are connected to the carry input terminal of the full adder 70 ₂ to 70 _n (Ci). The first input terminals (A1) of the full adders 70 _{1 to} 70 _n are DFFs.
71 ₁ is connected to a 71 _n output terminals (Q), the output terminal (S) are respectively connected to the DFF71 ₁ to 71 _n input terminals (D). The full adders 70 _{1 to} 70 _n consider the addition of the input bits from the first input terminal (A1) and the second input terminal (A2) in consideration of the carry from the carry input terminal (Ci). The result of the addition (sum) is output from the output terminal (S). If there is a carry in the addition result, the carry is output from the carry output terminal (Co).

Output terminals (Q) of DFFs 71 _{1 to} 71 _n
Are output terminals (Q1, Q1) of the up / down counter 32.
2,..., Qn), so that the latch outputs of the DFFs 71 _{1 to} 71 _n are output as count values.

In the up / down counter 32 configured as described above, during the bus reset period, its EN
When the input to the D terminal becomes H level, that is, when the output of the AD converter 31 is determined, the DFF 63
The level is latched and supplied to the input terminal of NAND gate 64.

On the other hand, initial value input terminals (F'1, F'2,
, F'n) is supplied with the output of the digital value determined in the AD converter 31 (hereinafter, appropriately referred to as a determined output). In the XNORs 61 _{1 to} 61 _n , each bit of the determined output is A value obtained by inverting the exclusive OR with the latch output of each of the DFFs 71 _{1 to} 71 _n is calculated. The operation results of the DFFs 71 _{1 to} 71 _n are NAN
The data is supplied to the D gate 62, where the product obtained by inverting the logical product thereof is calculated and supplied to the NAND gate 64.

A clock CK is further supplied to the NAND gate 64, where the latch output of the DFF 63, the output of the NAND gate 62, and the clock C
The result obtained by inverting the logical product of K is calculated, and the calculation result is supplied to the selector 66.

The selector 66 selects the output of the NAND gate 64 or the output of the inverter 65 when the BR signal is at H level or L level, for example. During the bus reset period, the BR signal is selected. Since it is at the H level, the selector 66
The output of AND gate 64 is selected.

Therefore, in this case, the DFFs 71 _{1 to} 71 _n
So the timing of the output of the NAND gate 64, the output of full adder 70 ₁ to 70 _n are latched.

When the BR signal is at H level or L level, for example, when the BR signal is at H level or U level,
The D signal is selected, and the BR signal is at the H level during the bus reset period. Therefore, the selector 67 selects the H level, and the carry input terminal of the full adder 70 ₁ ( is supplied to the ci), via the inverter 69, it is supplied to the second input terminal of the full adders 70 ₁ to 70 _n (A2).

Therefore, in this case, full adders 70 _{1 to} 7
0 _n , the latch outputs of the DFFs 71 _{1 to} 71 _n are:
It is incremented according to the clock CK, and the increment result is repeatedly latched by the DFFs 71 _{1 to} 71 _n .

When each of the latch outputs of the DFFs 71 _{1 to} 71 _n matches the corresponding bit of the definite output from the AD converter 31, the outputs of the XNORs 61 _{1 to} 61 _n all go to the H level.
The output of ND62 is at L level. When the output of the NAND 62 becomes L level, the output of the NAND 64 is fixed at H level, and the DFFs 71 _{1 to} 71 _n stop operating. That is, the full adders 70 _{1 to} 70 _n provide DFFs 71 _{1 to} DF
When the latch output of F71 _n is incremented according to the clock CK, and each of the latch outputs of DFFs 71 _{1 to} 71 _n matches the corresponding bit of the definite output from the AD converter 31, the DFF 71
_{1 to} DFF 71 _n are in a state of holding the value.

Thereafter, the bus reset period elapses and BR
When the signal goes to the L level, the clock CK or the UD signal via the inverter 65 is selected in the selector 66 or 67. As a result, the DFF 71 ₁
The clock CK is supplied to the DFF 71 _n via the inverter 68, and the full adders 70 _{1 to} 7
0 _n to start the latches on the output of.

On the other hand, in the full adders 70 _{1 to} 70 _n , UD
Whether the signal is H level or L level, the DFF 71 ₁
The latch output of DFF 71 _n is incremented or decremented, and the increment or decrement result is output to DFF 71 _{1 to} DFF 71 _n .

Therefore, the up / down counter 32 sets the definite output supplied from the AD converter 31 as an initial value of the count value during the bus reset period, and after the bus reset period elapses, according to the UD signal. The count value is incremented or decremented.

Next, the operation of drive circuit 12 shown in FIG. 3 will be described.

As described with reference to FIG. 2, when the cable 1 is in the high impedance state, the capacitor Cref is charged with a charge corresponding to the bias voltage. Then, after that, when the output of the differential signal is started, a bus reset period is provided.
Signals TpDA and TpDB are both at H level. As a result, the output of the AND gate 46, that is, the BR signal becomes H level. In the bus reset period, the signal Idle or TpEn becomes L or H, respectively.
Level, and the speed signal SpdSig is kept at the L level.

When the BR signal goes high, the AD converter 31 starts operating, and a predetermined output is supplied to the selector 33.
It is supplied to one input terminal (I1) of _{1 to} 33 _n . The selector 33 ₁ to 33 _n, if BR signal is H level, since selects the output of the AD converter 31, thereby, its output via the NAND gate 34 ₁ to 34 _n, the transistor p11 through p1n, And the gates of the transistors p21 to p2n. As a result, a pull-up current flows as the differential signal Tp or TpX through the transistor 38 or 39, respectively.

When the signal Idle goes to L level,
The transmission gate 41 becomes insulated, and a voltage corresponding to the charge charged in the capacitor Cref,
That is, the bias voltage of the cable is applied to the non-inverting input terminal of the comparator 45. Further, when signal TpEn attains an H level, transmission gate 42 is rendered conductive as described above.

Therefore, the comparator 45 is supplied with the common mode voltage which is the voltage at the connection point of the two resistors RC and the bias voltage which is the voltage corresponding to the electric charge accumulated in the capacitor Cref. The comparison result of the magnitude comparison is output as a UD signal.

As described above, the AD converter 31 outputs its output (D in FIG. 4) in accordance with the level of the UD signal.
FF60 _n-1 to 60 ₁ of the latch output), it is sequentially determined. That is, the digital value output from the AD converter 31 is DA-converted by the transistors p11 to p1n and the transistors p21 to p2n.
The common mode voltage as a result of the A conversion is compared in the comparator 45 with a bias voltage. Then, the comparison result is output as a UD signal, and in the AD converter 31, the digital value is sequentially determined based on the UD signal so that the common mode voltage and the bias voltage coincide with each other from the upper bits.

As described above, the AD converter 31, the transistors p11 to p1n, p21 to p2n, and the comparator 45 perform the successive approximation type AD conversion, whereby the bias voltage is reduced by the bias voltage and the common mode voltage. And transistors p11 to p1n and p1 that can pass a pull-up current to make
21 to p2n are converted into digital values required to turn on.

When the digital value output from the AD converter 31 is determined (in the successive approximation type AD converter,
When the result of the AD conversion of the bias voltage is determined), the END terminal of the AD converter 31 becomes H level, and this H level is supplied to the END terminal of the up / down counter 32.

The up / down counter 32 has its END
When the H level is supplied to the terminal, as described above, AD
The digital value output from converter 31 is set as the initial value of the count value.

Thereafter, when the bus reset period elapses,
The BR signal changes from the H level to the L level, and the AD converter 31 stops operating. When the BR signal goes low, the up / down counter 32 increments or decrements the count value according to the UD signal, as described above.

As described above, the successive approximation type A / D conversion is performed during the bus reset period, so that the bias voltage causes the pull-up current to flow for matching the bias voltage with the common mode voltage. Since the digital values necessary for turning on the transistors p11 to p1n and p21 to p2n are converted, necessary ones of the transistors p11 to p1n and p21 to p2n can be turned on in a short time. .

The digital value is set as an initial value,
Since the up / down counter 32 is operated, it is possible to cope with a change in the common mode voltage due to a change in the characteristics of the transistors N2 and N3 due to, for example, heat after the bus reset period. .

Next, FIG. 6 shows a third configuration example of the driver circuit 12 of FIG. In the figure, portions corresponding to those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted as appropriate below. That is, this embodiment, except that the up-down counter 32 and a selector 33 ₁ to 33 _n is not provided, is configured as in FIG.

Therefore, during the bus reset period, AD
When the digital value output from converter 31 is determined, transistor p1 is output according to the digital value.
Among the 1 to p1n and the p21 to p2n, the one to be turned on is determined in the same manner as the embodiment of FIG. 3, but in the embodiment of FIG. Using the digital value determined during the period as it is, the transistors p11 to p1n, p1
Necessary ones of 21 to p2n are turned on.

As a result, after the bus reset period has elapsed, for example, the transistors N2 and N3 caused by heat or the like
Be due to the characteristic change in to follow the change of the common mode voltage becomes difficult, does not require a ₁ to 33 _n up-down counter 32 and a selector 33, it is possible to construct a circuit in size. The up-down counter 32 consumes power to change its count value while outputting a differential signal after the elapse of the bus reset period. In the present embodiment, such power is consumed. Consumption can also be reduced.

Next, FIG. 7 shows a fourth configuration example of the driver circuit 12 of FIG. In the figure, parts corresponding to those in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted below as appropriate.

In this embodiment, when the cable 1 is in the high impedance state, a current corresponding to the differential signal for monitoring flows, and the common mode voltage as an average value of the differential signal for monitoring and the bias voltage The transistors p11 to p1 are turned on at the time of outputting the actual differential signal according to the digital value.
n, p21 to p2n are determined.

That is, in this embodiment, the clock CK or the Idle signal is supplied to the clock terminal (CK) or the BR terminal of the AD converter 31, respectively. Further, the output terminals (Fn, Fn-1,..., F2, F1) of the AD converter 31 are DFF
82 _{n to} 82 ₁ , NAND gates 34 _{n to} 3 _n
41, _one input terminal and NAND gates 35 _{n to} 35 _n
1 is connected to one input terminal. Note that DFF8
The clock terminals 2 _{1 to} 82 _n are connected to the END terminal of the AD converter 31. Therefore, in the DFFs 82 _{n to} 82 ₁ , when the digital value output from the AD converter 31 is determined, the digital value is latched and supplied to the NAND gates 34 _{n to} 34 ₁ and the NAND gates 35 _{n to} 35 _1. Has been made.

The output terminals of the AD converter 31 (Fn, Fn
n-1,..., F2, F1) are further connected to one of the input terminals of the NAND gates 81 _{n to} 81 ₁ . The Idle signal is supplied to the other input terminal of each of the NAND gates 81 _{n to} 81 ₁ , and the respective output terminals are connected to transistors p5n to p5n.
51 and the gates of the transistors p6n to p61. Therefore, the gates of the transistors p5n to p51 and the transistors p6n to p61
Is turned on according to the digital value output from the AD converter 31 while the Idle signal is at the H level, that is, while the cable 1 is in the high impedance state.

The transistors p5n to p51 or the transistors p6n to p61 have the same configuration as the transistors p1n to p11 or the transistors p2n to p21, and are adapted to flow a current as a monitoring differential signal.

That is, the sources of the transistors p5n to p51 and the sources of the transistors p6n to p61 are
Both are connected to the power supply. Then, the drains of the transistors p5n to p51 or the transistor p6n
Through p61 is the transistor 38 or 39
Are connected to the drains of transistors 85 and 87, respectively.

Here, the gate of the transistor 85 is
The transistor 87 is connected to the output terminal (Q) of the DFF 84, and the gate of the transistor 87 is grounded here. The source of the transistor 85 or 87 is connected to the drain of the transistor 86 or 88 having the same configuration as the transistor N2 or N3, respectively. The transistor 86 or 88 forms a current mirror circuit together with the transistor N1, similarly to the transistor N2 or N3, respectively.

Therefore, the same signal as the differential signal Tp, the drains of the transistors p6n to p61 and the transistor 87 are output from the connection point between the drains of the transistors p5n to p51 and the drain of the transistor 85.
From the connection point, the same signal as the differential signal TpX can be extracted as a signal for monitoring.

The input terminal (D) of the DFF 84 is connected to a power supply, and its clock terminal is supplied with an Idle signal. The output of the END terminal of the AD converter 31 is supplied to the clear terminal (CL) of the DFF 84 via the buffer 83 and inverted. Therefore, the DFF 84 latches the H level when the Idle signal changes from the L level to the H level. Then, the latch output is cleared when the output of the END terminal of the AD converter 31 changes from L level to H level (to L level).

Between the connection point between the drains of the transistors p5n to p51 and the drain of the transistor 85, and the connection point between the drains of the transistors p6n to p61 and the transistor 87, a resistor having two resistors Rc 'connected in series is connected. ing. The resistor Rc 'is the same as the resistor RC, and therefore, the same monitor voltage as the common mode voltage can be extracted from the connection point of the two resistors Rc'. This connection point is connected to the non-inverting input terminal (+) of the comparator 45.

Between the connection point between the drains of the transistors p5n to p51 and the drain of the transistor 85 and the connection point between the drains of the transistors p6n to p61 and the transistor 87, 2
One in which two resistors Rt ′ are connected in series is also connected.
Note that the resistance Rt ′ has a resistance value that is の of the resistance value of the termination resistance RT in FIG. Further, the resistance Rt ′
Can be externally attached to the one-chip drive circuit 12 or can be built-in.

The connection point between the two resistors Rt 'is connected to the output terminal of an operational amplifier 89 whose output terminal is connected to the non-inverting input terminal (+). The inverting input terminal (-) of the operational amplifier 89 is It is connected to a connection point of two resistors RC. This connection point is also connected to the inverting input terminal (-) of the comparator 45.

Next, the operation will be described.

When the cable 1 goes into a high impedance state and the Idle signal goes to the H level, the AD converter 31 whose Idle signal is supplied to the BR terminal starts operating, and the predetermined output (digital value) becomes NAND.
One input terminal of the gates 81 _{1 to} 81 _n and the DFF 8
2 _{n to} 82 ₁ .

The other input terminal of each of the NAND gates 81 _{1 to} 81 _n is supplied with the idle signal at the H level. Therefore, the output (inverted) of the AD converter 31 is supplied to the NAND gate 81. _The signals are supplied to the gates of the transistors p51 to p5n and the transistors p61 to p6n via _{1 to} 81 _n . as a result,
The differential signal Tp is applied to the transistor 85 or 87, respectively.
Alternatively, a pull-up current flows as a signal for monitoring TpX.

Here, in this embodiment, when the Idle signal changes from L level to H level, the DFF 84
At the H level, and the latched output is supplied to the gate of the transistor 85. The gate of the transistor 87 is grounded. Therefore, the pull-up current as a monitor signal flows only through the transistor 85.

When a monitor current flows, two resistors R
A common mode voltage for monitoring appears at the connection point of c ′, and this voltage is applied to the non-inverting input terminal of the comparator 45. On the other hand, the inverting input terminal of the comparator 45 has the voltage at the connection point of the two resistors RC, that is, the cable 1.
Is in a high-impedance state. In this case, a bias voltage is applied. Therefore, the comparator 45 compares the magnitudes of the bias voltages and outputs a UD signal as a comparison result.

As described above, the AD converter 31 outputs its output (D in FIG. 4) in accordance with the level of the UD signal.
FF60 _n-1 to 60 ₁ of the latch output), it is sequentially determined. That is, the digital value output from the AD converter 31 is DA-converted by the transistors p51 to p5n and the transistors p61 to p6n.
The common mode voltage as a result of the A conversion is compared in the comparator 45 with a bias voltage. Then, the comparison result is output as a UD signal, and in the AD converter 31, the digital value is sequentially determined based on the UD signal so that the common mode voltage and the bias voltage coincide with each other from the upper bits.

As described above, in the present embodiment, the AD converter 31 and the transistors p51 to p5n, p61
Through p6n and the comparator 45 perform successive approximation type AD conversion, whereby the bias voltage can flow a pull-up current for matching the bias voltage with the common mode voltage for monitoring. It is converted into a digital value required to turn on the transistors p51 to p5n and p61 to p6n.

Here, transistors p51 to p5n,
p61 to p6n are transistors p11 to p1n,
Since they have the same configuration as p21 to p2n, respectively, they are necessary to turn on transistors p51 to p5n and p61 to p6n that can flow a pull-up current for matching the common mode voltage for monitoring and the bias voltage. The digital values are as follows: transistors p11 to p1n, p2 capable of flowing a pull-up current for matching the actual common mode voltage and the bias voltage.
1 to the digital value required to turn on p2n.

[0171] Therefore, when the digital value AD converter 31 outputs is determined, the digital output of the END terminal from the L level to the H level, thereby, in DFF82 ₁ to 82 _n, the AD converter 31 outputs, which is determined The value is latched.

Thereafter, when an actual differential signal is output, the signal Idle or TpEn is set to L or H level, respectively, and the signal TpEn is set to H level, so that the latch outputs of the DFFs 82 _{1 to} 82 _n become NA
Through the ND gates 34 _{1 to} 34 _n , the transistor p1
1 to p1n and the gates of the transistors p21 to p2n. As a result, among the transistors p11 to p1n and p21 to p2n, those necessary for equalizing the common mode voltage and the bias voltage are turned on.

Note that when the signal Idle goes to L level, the DFF 84 is cleared, whereby the L level is applied to the gate of the transistor 85. Accordingly, the transistor 85 is turned off, and the current for monitoring the differential signal does not flow, so that the monitoring current flows after the actual output of the differential signal starts, so to say, wasteful power. Consumption can be prevented.

As described above, when the cable 1 is in the high impedance state, the digital value for equalizing the common mode voltage and the bias voltage is determined, so that the current changes when the differential signal is output. There is no. Also here, since the up / down counter 32 is not provided, the power can be saved by that amount. Further, each time the cable 1 enters the high impedance state, a digital value for equalizing the common mode voltage and the bias voltage is determined, so that it is possible to flexibly cope with the fluctuation of the bias voltage.

In the above description, the AD conversion is performed by the successive approximation type AD converter. However, the AD conversion can be performed by another method.

Further, the applicable range of the present invention is IEEE13
The communication is not limited to the communication conforming to the H.94 standard.

[0177]

According to the drive circuit according to the first aspect and the drive method according to the ninth aspect, a plurality of parallel circuits for converting a bias voltage into a digital value and turning on / off a current corresponding to the digital value. The connected switching means is turned on or off. Therefore, it is possible to provide a small-sized drive circuit that can cope with the fluctuation of the bias voltage.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of a communication system to which the present invention has been applied.

FIG. 2 is a circuit diagram showing a first configuration example of a drive circuit 12 of FIG. 1;

FIG. 3 is a circuit diagram showing a second configuration example of the drive circuit 12 of FIG. 1;

4 is a circuit diagram showing a configuration example of the AD converter 31 of FIG.

FIG. 5 is a circuit diagram showing a configuration example of an up-down counter 32 of FIG. 3;

FIG. 6 is a circuit diagram showing a third configuration example of the drive circuit 12 of FIG. 1;

FIG. 7 is a circuit diagram showing a fourth configuration example of the drive circuit 12 of FIG. 1;

FIG. 8 is a circuit diagram showing a configuration of an example of a conventional communication system.

FIG. 9 is a circuit diagram showing a configuration of an example of a conventional drive circuit.

[Explanation of symbols]

1 cable, 11 cable bias circuit, 12
Drive circuit, 13 receive circuit, 14 common mode signal detection circuit, 15 drive circuit, 16
Receive circuit, 21 Cable bias circuit, 2
2 drive circuit, 23 receive circuit, 24 common mode signal detection circuit, 25 drive circuit, 2
6 Receive circuit, 31 AD converter, 32
Up-down counter, 33 ₁ to 33 _n selector,
34 _{1 to} 34 _n , 35 _{1 to} 35 _n NAND gates,
36, 37 inverter (NOT gate), 38 to 40 transistors, 41, 42 transmission gate, 43 inverter, 44 NOR gate, 45 comparator, 46 AND gate,
47 NAND gate, 48, 49 inverter,
50 AND gate, 51 NAND gate, 52
Inverter, 53 pulse generator, 54 ₁
To 54 _{n + 1} DFFs, 55 inverters, 56 _{1 to} 56 _n AND gates, 57 inverters, 58 ₁
To 58 _n NOR gate, 59 _{1 to} 59 _n , 60 _{1 to} 60 _n DFF, 61 _{1 to} 61 _n XNOR gate, 62 NAND gate, 63 DFF, 64
NAND gate, 65 inverter, 66, 67
Selector, 68, 69 inverter, 70 _{1 to} 7
0 _n full adder, 71 _{1 to} 71 _n DFF, 81 _{1 to} 81 _n NAND gate, 82 _{1 to} 82 _n DF
F, 83 buffer, 84 DFF, 85 to 8
8 transistors, 89 operational amplifiers

Claims (9)

[Claims] 1. A drive circuit for flowing a current corresponding to a differential signal to be transmitted to a communication partner connected via a cable biased to a predetermined bias voltage, wherein the drive circuit turns on / off the current. A switching means connected in parallel, a conversion means for converting the bias voltage into a digital value, and a control means for controlling on / off of the switching means corresponding to the digital value. circuit. 2. When the first to n-th switching means are connected in parallel, i = 1, 2,.
The current flowing when the (i + 1) th switching means is turned on is twice as large as the current flowing when the (i) th switching means is turned on. The drive circuit according to 1. 3. The method according to claim 2, wherein the converting unit sets the bias voltage to A.
2. The drive circuit according to claim 1, wherein the digital value is obtained by performing / D conversion. 4. The drive circuit according to claim 3, wherein said conversion means is a successive approximation type A / D converter. 5. The method according to claim 5, wherein the conversion unit is a counter that increments or decrements the count value as the digital value based on a magnitude relationship between the average value of the differential signal and the bias voltage. The drive circuit according to claim 1. 6. An A / D converter for converting the bias voltage into an analog value by A / D converting the bias voltage, and a magnitude relationship between an average value of the differential signal and the bias voltage. Counting means for incrementing or decrementing the count value to be the digital value based on
2. The drive circuit according to claim 1, wherein the digital value output from the / D converter is used. 7. A storage unit for storing the bias voltage when the cable is in a high impedance state, wherein the conversion unit converts the bias voltage stored in the storage unit into a digital value. Claim 1
The drive circuit according to 1. 8. The apparatus according to claim 1, further comprising: a current control unit that, when the cable is in a high impedance state, supplies a current corresponding to the differential signal for monitoring in accordance with the digital value. 2. The drive circuit according to claim 1, wherein the digital value that makes a voltage equal to the average value of the differential signal for monitoring by the current control unit is output. 9. A drive method in a drive circuit for flowing a current corresponding to a differential signal to be transmitted to a communication partner connected via a cable biased to a predetermined bias voltage, wherein the drive circuit comprises: A drive method comprising: a plurality of switching means connected in parallel for turning on / off a current; converting the bias voltage into a digital value and turning on or off the switching means corresponding to the digital value; .