JPH117781A - Reconfigurable dual memory in programmable logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To specify the address having the efficient constituting capability by forming the contents addressable memory in the first mode, and forming the recostitutable dual-mode memory suitable to act as the random access memory in the second mode. SOLUTION: For example, a logic-array block LAB 204a and a row 250 is connected to a first and a second plural horizontal conductors 274 and 276 through programmable connectors 280 and 282. By the same way, the LAB 204a is connected to the second plural vertical connectors 290 and 292 through programmable connectors 296 and 294. Furthermore, a dual-mode memory block DEMM 202a is connected to the vertical connectors 292 and 291 and connected to horizontal conductors 274 and 276 with the respective programmable connectors 293 and 299. Thus, the reconfigurable logic circuit and the array in the dual-mode memory can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates generally to programmable logic circuits incorporating reconfigurable dual mode memories. Also described is a reconfigurable dual mode memory arranged to act as either a CAM or a RAM.

[0002]

2. Description of the Related Art Programmable logic circuits, ie, PL
D is a programmable integrated circuit that allows the user of the circuit to tailor the logic functions performed by the circuit using software control. Heretofore, logic functions performed by small, medium, and large scale integrated circuits can be performed instead by programmable logic circuits. Typical programmable logic circuits, when supplied by an integrated circuit manufacturer, cannot yet perform any particular function. The user can program the PLD with software provided by the manufacturer or software created by the user, or an associated source, to perform the specific functions required by the user's application. The PLD then behaves as if a dedicated logic chip is used in a large system designed by the user. It is to be understood that, for convenience of description, programmable logic means one-time programmable and one-time programmable re-programmable circuits.

[0003] Programmable logic encompasses all digital logic, including field programmable gate arrays (FPGAs) and complex PLDs (CPLDs), configured by the end user. One example of a CPLD is known as an embedded array programmable logic circuit. An embedded array programmable logic circuit comprises a plurality of embedded array blocks, or EABs, interconnected to be programmable to form a memory and logic array for implementing memory and dedicated logic functions.
Use Common logic functions are performed through the use of logic array blocks, or LABs, that are interconnected in a programmable manner. By properly interconnecting the EAB and LAB arrays in a programmable manner, the embedded array programmable logic circuit can perform many complex logic functions and combinational logic / memory functions.

[0004] The architecture of an embedded array programmable logic circuit may be formed by a plurality of logic array blocks arranged in a row direction and a column direction and coupled to a plurality of horizontal and vertical conductors via a programmable connector. . Similarly, an array of embedded array blocks may be configured such that one or more EABs appear on each row of the logic array block. The array of EABs is also coupled to multiple horizontal and vertical conductors by multiple programmable connectors. By way of example, FIG. 1 illustrates the architecture of an embedded array programmable logic circuit exemplified by the FLEX10K.RTM. Logic circuits manufactured by Altera Corporation of San Jose, Calif., USA. As described above, the logical array block 10
4a, 104b are configured to form a row 150 including a single embedded array block 102a. Similarly, the second row 15 including the arrangement of the logical array blocks 104c and 104d and the embedded array block 102b
2 are subsequently formed.

As mentioned above, each LAB and EAB can be programmably coupled to a plurality of vertical and horizontal conductors by appropriately located programmable connectors.
By way of example, LAB 104a included in row 150 may be electrically coupled to first plurality of horizontal conductors 174 and second plurality of horizontal conductors 176 by programmable connectors 180, 182, respectively. In a similar manner, the LAB 104a
Are connected to the first plurality of vertical conductors 190 and the second plurality of vertical conductors 19 by programmable connectors 194 and 196, respectively.
2 may be electrically coupled. Similarly, each array of EABs may be electrically coupled to one or more respective plurality of horizontal and vertical conductors. By way of example, EAB 102a is electrically coupled to vertical conductors 192, 191 by programmable connectors 195, 197, respectively, and horizontal conductor 17 by programmable connectors 193, 199, respectively.
4, 176 may be electrically coupled. In this way, an embedded array programmable logic circuit capable of implementing many complex logic functions and combinational logic / memory functions is formed.

[0006] EAB is a flexible block of random access memory, ie, RAM, with registers on input and output ports. As is known to those skilled in the art, a RAM is a single memory cell array that includes a plurality of transistors, each cell configured to store digital data in a single bit format. Typically, a single memory cell is configured to form data words of varying length depending on the particular application. In implementation, the data words can be of any length, with data word lengths of 1, 8, 16, and 32 bits being common, but any word length required by the user is possible. Structurally, the RAM device has the ability to access or read each stored data bit or data word independently of any other stored data bits or data words by selectively enabling the requested rows and columns. I have.

[0007]

However, many applications, such as database devices, image or voice recognition, or computers and communication networks,
Request fast searches of databases, lists, or patterns. In general, fast searches using RAM employ search algorithms such as binary, tree-based search, or lock-aside tag buffers. Unfortunately, the structure of the RAM is relatively slow and requires these algorithms to continuously compare the pre-stored data in RAM with the requested data in a way that results in unacceptable search times. And

[0008] In order to meet the needs for fast searching in large databases, lists or patterns, a device known to those skilled in the art as a content addressable memory, or CAM, has been developed. A CAM is a memory device that facilitates applications such as databases, database devices that require fast retrieval of lists or patterns, image or speech recognition, or computers and communication networks. Since the CAM compares the entire list of pre-stored data simultaneously, it can have significant performance advantages when using a RAM, when performing a fast search of a database, list, or pattern, as compared to using a RAM. Typically, when performing a fast search,
The CAM search engine provides up to an order of magnitude faster performance than the RAM search engine.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and has as its object to provide a programmable logic circuit which enables efficient addressing of configurable contents.

[0010]

In order to achieve the above object, a programmable logic circuit having a content addressable memory is disclosed. In a preferred embodiment,
In the first mode, as a content addressable memory,
Also disclosed is a reconfigurable dual mode memory suitable for acting as a random access memory in the second mode. The mode control switch circuitry is provided to allow a user to selectively configure the dual mode memory as either a content addressable memory or a random access memory.

In a preferred embodiment, the dual memory block is appropriately positioned for an output match address that matches the requested data word when the dual mode memory block is configured to act as a content addressable memory. Having a plurality of columns and rows. The dual mode memory cell also includes a plurality of dual mode memory cell data lines, row lines, match lines, a data storage circuit for storing data, a comparison circuit for comparing the stored data with the requested data, and a data storage circuit. And an insulation circuit for selectively insulating the comparison circuit.

[0012] The programmable logic circuit also has a comparator and a first encoder for storing and waiting for requested data. The first encoder is suitable for receiving and storing a match address, and also has a MATCH or NO
It is suitable for generating a system match flag indicating a MATCH state.

In another embodiment, a reconfigurable programmable logic circuit has an array of programmable interconnected logic cells suitable for use in implementing program logic functions. The reconfigurable programmable logic circuit also has a dual mode memory block that is programmably coupled to the array of logic cells. The dual mode memory block is configured to act as a content addressable memory in the first mode and as a random access memory in the second mode.

The programmable logic circuit also has a mode control switch circuit coupled to the content addressable memory block. The mode control switch circuit allows the dual mode memory block to act as a content addressable memory block or a random access memory block. In other embodiments, a dual mode memory block may act as a static random access memory block.

In yet another embodiment, a reconfigurable programmable logic circuit comprises an array of programmable interconnected logic cells and an array of logic cells suitable for use in implementing a program logic function. It has a content addressable memory block that is programmably coupled. The content addressable memory block is configured to output an address location corresponding to a requested data word. The reconfigurable logic circuit also has a mode control switch circuit coupled to the content addressable memory block. The mode control switch circuit may enable the content addressable circuit to act as a random access memory block.

In yet another embodiment, a programmable logic circuit using an embedded logic array block architecture configured as a dual mode memory is disclosed. Programmable logic circuits have an array of logic interconnected programmable blocks suitable for use in implementing program logic functions. The programmable logic circuit also has a dual mode memory block that is programmably coupled to the array of logic blocks. In this embodiment, the dual mode memory block is configured to act as a content addressable memory in the first mode and as a random access memory in the second mode.

Also disclosed is a dual mode memory circuit configured to act as a content addressable memory in a first mode and as a random access memory in a second mode. A dual mode memory cell includes a data storage circuit for storing data,
A comparing circuit for comparing the stored data with the requested data,
A match line is provided to indicate whether the stored data matches the request data, and an insulation circuit is provided to electrically insulate the data storage circuit from the comparison circuit and the match line.

[0018]

DETAILED DESCRIPTION OF THE INVENTION The present invention generally relates to a programmable logic circuit having a content addressable memory. In a preferred embodiment of the invention, the content addressable memory is configured to act as a dual mode memory so as to act as a content addressable memory, ie, a CAM in the first mode.
In the second mode, the memory acts alone as a static random access memory, ie, a RAM such as an SRAM.

Referring first to FIG. 2, an embedded array programmable logic circuit 200 including one or more dual mode memory blocks according to one embodiment of the present invention will be described. Programmable logic circuit 2
00 denotes a plurality of logical array blocks (LAB) 204
a, 204b, 204c, 204d and a plurality of embedded array blocks 202a, 202b taking the form of a dual mode memory block (DMMB). The general architecture of an embedded array programmable logic circuit is:
It is commonly known to those who understand the FLEX10K logic family, manufactured by Altera of San Jose, California, USA. Although several logical array blocks and dual mode memory blocks are shown, it should be understood that any number of blocks may be provided to meet the needs of a particular system.

The logical array blocks 204a to 204d,
And dual mode memory blocks 202a, 202b
Can each be programmably coupled to one or both of the plurality of vertical conductors and the plurality of horizontal conductors by appropriately positioned programmable connectors. For example, row 25
The LAB 204a contained in a part of the first and second horizontal conductors 274 and 276 is electrically coupled to the first and second horizontal conductors 274 and 276 by programmable connectors 280 and 282, respectively. Similarly, LAB 204a is electrically coupled to first plurality of vertical conductors 290 and second plurality of vertical conductors 292 by programmable connectors 296,294, respectively. Similarly, each array of DMMB is electrically coupled to at least one or more of a plurality of vertical and horizontal conductors. As an example, DMMB 202a
Are electrically coupled to vertical conductors 292 and 291 by programmable connectors 295 and 297, respectively, and electrically coupled to horizontal conductors 274 and 276 by programmable connectors 293 and 299, respectively. In this way, an array of reconfigurable logic circuits and dual mode memories is formed.

FIG. 3 shows a functional block diagram of an embedded array programmable logic architecture reconfigurable as a dual mode memory, in accordance with one embodiment of the present invention. In the embodiment of the present invention, the dual mode memory block 202a can be user-configured as a content addressable memory (CAM) or a random access memory (RAM). As shown, the dual mode memory block 202a includes:
Multiple selectivity program inputs 29 from vertical conductors 291
7 has an input control block 900 used to couple it to the column controller 500 and the row controller 300. RAM / CAM mode control input 225 (hereinafter "R
/ C mode control input ". ) Is directly coupled to the dual mode memory device. The R / C mode control input 225 causes the dual mode memory device 400 to act as a CAM or a RAM depending on the state of the R / C mode control input 225. In one embodiment, when the R / C mode control input 225 goes high (ie, represents a digital value of “1”), the dual mode memory device 4
00 can act as a CAM. On the other hand, R / C
When the mode control input 225 goes LOW (ie, represents a digital value “0”), the dual mode memory device 400 can act as a RAM.

In the described embodiment of the invention, a plurality of selectivity program inputs 297 are provided to select selected memory locations in dual mode memory device 400 when dual mode memory device 400 is configured to act as RAM. May include a plurality of data inputs 210 representing input data to be stored in the data input 210. On the other hand, when the dual mode memory device 400 is configured to act as a CAM, the plurality of data inputs 210 provide the required data to be compared with data previously stored in the dual mode memory device 400. Can be represented. Input 297 also
One embodiment may include a first multiple address input 220 that may represent a least significant bit (LSB) of a multi-bit addressing scheme. Input 297 is also a second multiple address input 2 that may represent the most significant bit (MSB) of the multi-bit addressing scheme in one embodiment.
22.

In the embodiment of the present invention described above, the column control device 500 controls the input data 21 via the input control 900.
0, and transmits it to the dual mode memory device 400 via the column data signal 520. The column controller 500 also includes a second multiple address input 2 representing the most significant bit (MSB) of the multi-bit addressing scheme.
22 is received. Then, the column controller 500 decodes the received address input 222 to form a column selection data set that is continuously transmitted to the dual mode memory device 400 via the column address signal 530. In this manner, column controller 500 may perform selectivity enabling of selected columns of memory cells included in dual-mode memory device 400 to receive input data 220. Similarly, row controller 300 receives input data 210 representing a least significant bit (LSB) of a multi-bit addressing scheme in one embodiment via input controller 900 and reads address signal 310 or write address signal 310. An address signal 320 is output to the dual mode memory device 400.

The dual mode memory device 400 has an RA
When configured to act as M, it communicates with output controller 600 via output signal 650 and
Communicate with global match output 800 when configured to act as M. The output control device 600 includes:
It may be coupled to an output driver (not shown) that is programmably coupled to one or more horizontal conductors of the plurality of horizontal conductors, or to one or more vertical conductors of the plurality of vertical conductors. FIG. 4 illustrates a dual mode memory block 202a that can be reconfigured as a content addressable memory or a random access memory via an R / C mode control input 225 according to one embodiment of the present invention.
3 is a functional block diagram of FIG. In this embodiment, the data-in register 910, the data buffer 912, the comparator 914, the address register 970, the address register 972, the address control 960, the read / write enable device 965, and the address decode 950 configure the input control device 900 of FIG. Form.

Referring to FIG. 4, when acting as a CAM, dual mode memory device 400 may receive input data 210 via data-in register 910. Data-in register 910 receives input data 210 and provides it to the input of data buffer 912. The data buffer 912 is a data buffer 91
2 receives the input data 210 and also sends the input data 210 to the input of the comparing device 914 to be queued as request data. It has an electronic buffer (not shown). In this embodiment, the requested data is stored in the memory storage cell circuit of the dual mode memory device 400 such that the address location of any matching stored data contained in the dual mode memory device 400, if any, is determined. This is compared with the pre-stored data. In other embodiments, the input data 210 may be received directly by the input of a comparanding device 914 as illustrated in FIG. 5 to conveniently eliminate any delay time associated with the data-in register 910 and the data buffer 912.

Referring again to FIG. 4, when the dual mode memory device 400 is configured to act as a RAM, the comparator 914 can be bypassed and the input data 210 can be passed through the data buffer 912 to the column controller. 500 data inputs directly.

In the embodiment described above, the user address information is input to the dual mode memory device 400 via the address input device 970 and the address input device 972. The user address information, in one embodiment, is the least significant bit of the address information (ie, LS
B) and a second group of address input data 222 that can represent the most significant bit (ie, MSB) of the address information. In the embodiment of the invention described above, the address input device 9
70 receives the first group of address input data 220 and transfers it to the address control 960. Next, address control 960 generates an output that is forwarded to address decoder 950. As an example, the first group of address input data 220 may be composed of five least significant bits of a multi-bit addressing scheme and six data bits representing one control bit. In this case, the address input device 970 receives five address bits and one control bit of the first address input data 220 group, and transfers them to the address control 960. Next, the address control 960 has six outputs, five of which represent selectable address locations that can be received by the address decode 950 and the sixth is a read / write control signal that is transferred directly to the row controller 300. Generate In the embodiment of the present invention, address decoder 950 has a decoder (not shown) for converting the received five address bits of first address input data 220 group into 32-bit read / write row address information. The 32-bit address information is sequentially transferred to the row control device 300.

The second group of address input data 222 can be input to the dual mode memory device 400 via the address input device 972 and the column control device 500. In operation, the address input device 972 receives the second group of address input data 222 and transfers it to the address input of the column controller 500. By way of example, the address information received by the address input 972 may comprise five address bits associated with the most significant bit of a multi-bit addressing scheme, and a write enable bit. The five most significant bits are
00. The column control device 500 has a column address decoder (not shown) that decodes the five most significant bits and generates 32 column address bits. The write enable bit output from the address input 972 is output to the read enable RE 966 signal and the write enable WE 96 input to the row controller 300.
7 form an input to a read / write controller 965 that produces a signal.

As described above, the row control device 300 receives the address information generated by the address decode 950. In the above-described embodiment, the row control device 300 receives the address bits generated by the address decode 950. Row control device 300 has two to one demultiplexers (not shown) that generate two groups of address bits, one corresponding to a read address and the other corresponding to a write address. As an example,
When address decode 950 outputs 32 read / write address bits to row controller 300, two to one demultiplexer included in row controller 300 outputs read address signal 3 of 32 bits.
It generates 10 and 32 bit write address signals 320. In this embodiment, the row control device 300 also
Complementary signals RE966, WE967 that determine whether the address information at the output of row controller 300 should be used for reading from and writing to dual mode memory device 400 are received.

In the embodiment of the invention described above, the output device 6
00 has a plurality of output buffer registers 620 and a first encoder 610. The plurality of output buffer registers 620 waits for data output from the dual mode memory device 400 and transfers the output data 622 to an output driver (not shown). In another embodiment of the invention, output buffer register 620 may have a larger R by cascading additional memory blocks.
The output data is converted to another DMMB or EAB included in a programmable logic circuit to form a block of AM.
Can be forwarded to When the dual mode memory device 400 is configured as a CAM, the first encoder 610 controls the global match data 8 indicating a match address.
00 may be received. First encoder 610 may transmit a SYSMATCH signal 612 indicating a MATCH or NO MATCH state. The first encoder 610 may also store multiple match addresses, and
MATCHF representing the total number of match addresses contained in 0
A LAG signal 614 may be generated.

In one embodiment, dual mode memory device 400 has an array of dual mode memory cells 410, one of which may be dual mode memory cell 420 illustrated in FIG. The dual mode memory cell 420 includes a data storage circuit 460, a comparison circuit 43
0, and an insulating circuit 450.

In the embodiment of the invention described above, the memory storage circuit 460 includes a p-channel transistor 464, an n-channel transistor 466, and a p-channel transistor configured to form a static random access memory cell, that is, an SRAM cell. 462, and n
A channel transistor 468 is provided. SRA shown
The M cell is configured as a cross-coupled inverter feedback circuit that can store digital data corresponding to digital 1 and digital 0, as is well known to those skilled in the art. In another embodiment, memory storage 460 includes:
Dual-port memory cells, read-only memory cells,
That is, it can be configured as a ROM or any other data-storable circuit known to those skilled in the art.

In the embodiment of the invention described above, the I / O node 465 includes the gates of the transistors 464 and 466, the drain of the transistor 462, and the transistor 468.
Is electrically connected to the source. Similarly, the second I / O node 463 is connected to the transistor 462,
The gate of the transistor 468, the drain of the transistor 464, and the source of the transistor 466 are electrically connected. In this configuration, the sources of transistors 464 and 462 are electrically connected to Vcc,
6, 468 have their drains connected to ground. The memory storage circuit 460 includes the n-channel pass gate transistor 4
72 may be electrically coupled to the first data line 424 and the word line 523. In this configuration, the transistor 4
72 has a source electrically connected to the first I / O node 465, a drain electrically connected to the data line 424, and a gate electrically connected to the word line 523. Further, the memory storage circuit 460 includes:
It may be electrically coupled to the second data line 422 and the word line 523 via the n-channel pass gate transistor 474. In this configuration, the transistor 474 is connected to the second I / O
It has a source electrically connected to the node 463, a drain electrically connected to the data line 422, and a gate electrically connected to the word line 523.
When the word line goes high, transistors 472, 474
Are substantially conductive such that I / O nodes 463 and 465 are electrically connected to data lines 422 and 424, respectively. In this method, the first I
The / O node 465 can receive data to be stored (referred to by those skilled in the art as a write operation) and transmit stored data (referred to as a read operation by those skilled in the art) via the data line 424. it can. Similarly,
The second I / O node 463 of the memory storage circuit 460 can receive data to be stored via the data line 422 and can transmit the stored data. In operation, the first node 465 and the second node 46
3 represents the complementary data state.

Comparison circuit 430 includes an n-channel transistor 432 whose drain is electrically connected to the source of n-channel transistor 436. Comparison circuit 430 also has an n-channel drain electrically connected to the source of n-channel transistor 438.
And a channel transistor 434. The sources of n-channel transistors 432, 434 are electrically connected to match line 440, and the drains of transistors 436, 438 are coupled to ground. Match line 440 is electrically connected to the sources of transistors 432 and 434 and forms part of global match line 800.

The isolation circuit 450 serves to couple the memory storage circuit 460 and the comparison circuit 430 via the n-channel transistors 454 and 452. In this configuration, the transistor 454 includes a source electrically connected to the gate of the transistor 436 of the comparison circuit 430,
It has a drain electrically connected to I / O node 465 of memory storage circuit 460. Similarly, the transistor 452 is connected to the transistor 438 of the comparison circuit 430.
And a drain electrically connected to the I / O node 463 of the memory storage circuit 460.

The R / C mode control input 225 is connected to the transistor 454 when the R / C mode control input 225 is high.
The node 455 is electrically connected to the gates of the transistors 454 and 452 so that both of them are conductive. In this method, the data storage circuit 460
Are electrically connected to the comparison circuit 430. In contrast, when R / C mode control input 225 is low, transistors 452, 454 are substantially non-conductive to effectively isolate memory storage circuit 460 and comparison circuit 430. In this method, when the comparison circuit 430 and the memory storage circuit 460 are electrically connected via the insulating circuit 450, the dual mode memory unit 400
Can act as a CAM. Alternatively, in this embodiment, when the comparison circuit 430 and the memory storage circuit 460 are electrically isolated via the isolation circuit 450, the dual mode memory circuit 420 can operate exclusively as a RAM.

In operation, when a user requests that the dual mode memory device 400 be configured for use exclusively as an SRAM, the R / C mode control input 255
It is pulled low so that both transistors 454, 452 of the isolation circuit 450 are turned off. In this method, the comparison circuit 4
30 and match line 440 are effectively electrically disconnected from memory storage circuit 460. In this manner, in the RAM only mode, the memory storage circuit 460 configured as an SRAM becomes a dedicated interaction circuit for the dual mode memory cell 420 such that the dual mode memory device 400 acts solely as an SRAM.

Alternatively, if the user requests that the dual mode memory device 400 be configured for use as a CAM, the R / C mode control input 255 will turn on both transistors 454, 452 of the isolation circuit 450, As a result, the comparison circuit 430 becomes the memory storage circuit 460
High to be electrically coupled to the I / O nodes 465, 463 of the same. In this manner, in the CAM mode, the comparison circuit 430, the match line 440, and the memory storage circuit 460 interact to act as a content addressable memory.

Once configured to act as a CAM, the data stored in the memory storage circuit 460 can be used to compare with any data entered via the comparator 914. By way of example, match line 440 forms an input to global match line 800 that can be electrically connected to a data register in a manner similar to first encoder 610 described above. In this embodiment,
Match line 440 may be precharged to a high state prior to the actual comparison operation. The single BIT of the data word DATA of a predetermined length waiting in the comparator 914 is, by the operation of the column controller 500 and the row controller 300 described above, a data line corresponding to the BIT and its complement / BIT, respectively. 424, 422 can be driven. Similarly, data word COMP may be pre-stored in a portion of memory cell array 410 by a previous write operation. In this embodiment,
Data word COMP may have a single bit COMBIT stored in memory storage cell 460. For example, COMB
IT sets the data line 424 to COMBIT during the previous write operation.
And if the data destination 422 is already written in the memory storage circuit 460 by driving it to / COMBIT, the voltage level corresponding to / COMBIT is I / O
It may appear at node 465. Similarly, a voltage level corresponding to COMBIT may appear at I / O node 463.

During the Compare operation, the word line 523 is connected to the data lines 422 and 424 from the output nodes 463 and 463, respectively.
It is driven low by the action of the low controller 300 which turns off the transistors 472, 474 that decouple 465. However, since the R / C mode switch is high, I / O nodes 463 and 465
6, 438 are electrically connected to the comparison circuit 430 via the gates. In this manner, I / O node 463 provides a first voltage level corresponding to COMBIT to the gate of transistor 438, and I / O node 465 provides a first voltage level corresponding to / COMBIT to the gate of transistor 436. 2
Supply voltage level.

Stored in memory storage circuit 460
A bit match occurs when COMBIT and the corresponding BIT stored in comparator 914 are at substantially similar voltage levels corresponding to the same digital value. In this manner, when a match occurs, comparison circuit 430 maintains the match line in its precharged high state. However, if COMBIT and BIT do not match, i.e., have substantially different voltage levels because they are considered to be different digital values, then the comparison circuit 430
Act to drive match line 440 to substantially ground or 0 volts provided by circuitry (not shown) coupled to global match line 800 to be in the NO MATCH state. Alternatively, all bits of DATA and COMP must match for a match to occur.

For example, if COMBIT matches digital one, I / O node 465 is connected to transistor 436
Is driven low (voltage level corresponding to digital "0"). Similarly, the I / O node 463
Is driven high (voltage level corresponding to digital “1”) to turn on transistor 438. If BIT also corresponds to digital 1 (representing MATCH),
Data line 424 is driven high to turn on transistor 432, and similarly, data line 422 is driven low to turn off transistor 434. In this manner, match line 440 remains high. On the other hand, COMBIT
And BIT do not match, the transistor 432,
Either the combination of 436, or the combination of transistors 434, 438 drives the match line low indicating a NO MATCH condition.

FIG. 7 illustrates a portion of an array 410 of dual mode memory cells including dual mode memory cells 420a-420d included in a dual mode memory device 400, according to one embodiment of the present invention. Illustrated. In this embodiment, the column control device 500 includes:
The received data is supplied via a column data signal 520 and the address selection data is supplied via a column address signal 530. When configured as a RAM, the column address signal is applied to the data lines 421-424 to facilitate reception of data to be stored during a write operation or transfer of data output during a read operation. Each is selectively enabled. The row control device 300 outputs a read address signal 310 or a write address signal 320 for selectively enabling or disabling individual word lines such as the word lines 523 and 521. Data lines 421-424 provide a plurality of differentials that convert the voltage levels output by the individual I / O nodes of the dual mode memory cells included in array 410 into a form that constitutes the data to be transferred to output register 620. It is coupled to the operational amplifiers 470-472. R / C mode input 2
When configured as a CAM by the operation of 25, a plurality of match lines, such as match lines 440, 442, are each combined to form an output match line 800 that sends global match data to the first encoder 610.

The present invention has been described based on some embodiments of the invention in order to clarify the understanding of the invention.
It should be understood that modifications and improvements can be made without departing from the spirit of the present invention. It should be noted that there may be other ways of implementing the invention. By way of example, the random access memory mode may be operated as a static random access memory (SRAM), a dual port memory, or a read only memory (ROM).

The present invention has been described with reference to a programmable logic circuit having an embedded array block architecture. However, the invention can also be implemented in other programmable logic architectures, such as a field programmable gate array type architecture. Furthermore, in the embodiments of the invention described above, each embedded array block has been described as a dual mode memory block, but this is not a requirement. Rather, some of the embedded array blocks are configured as dual mode memory, while other embedded array blocks are configured as single mode memory or any other suitable configuration.
Therefore, the foregoing illustration should be taken as illustrative, not as limiting. Further, the present invention is not limited to the above-described embodiments of the present invention, and can be improved within the scope of the claims of the present invention.

[0046]

As described above, according to the present invention,
Enables efficient configurable content addressing.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of the architecture of an embedded array programmable logic circuit.

FIG. 2 is a schematic diagram of an embedded array programmable logic circuit having a dual mode memory block according to one embodiment of the present invention.

FIG. 3 is a functional block diagram of an embedded array programmable logic architecture having the reconfigurable dual mode memory circuit illustrated in FIG.

FIG. 4 according to one of the embodiments of the invention according to the invention,
Input data may be received by a data-in / data-buffer combination and forwarded to a comparand device;
FIG. 4 is a functional block diagram of a dual mode memory block that can be configured as a user as a content addressable memory or a random access memory.

FIG. 5 according to one of the embodiments of the invention according to the invention,
Input data is received directly by the comparing device,
FIG. 3 is a functional block diagram of a dual mode memory block configured as a user as a content addressable memory by an R / C mode control input.

FIG. 6 according to one of the embodiments of the present invention,
FIG. 3 is a circuit diagram of a dual memory cell.

FIG. 7 shows one of the embodiments of the invention according to the present invention;
FIG. 2 is a circuit diagram showing a part of a dual mode memory array included in the dual mode memory.

[Explanation of symbols]

200: embedded array programmable logic circuit, 202
a, 202b: embedded array block (dual mode memory block), 204a, 204b, 204c, 20
4d: logic array block, 225: R / C mode controller, 250: low, 274: first plurality of horizontal conductors, 27
6. Second horizontal conductors 280, 282, 293, 29
4, 295, 296, 297, 299: programmable connector, 290: first plurality of vertical conductors, 292: second plurality of vertical conductors, 300: row control device, 400: dual mode memory device, 420a, 420b, 420c, 4
20d: dual mode memory cell, 430: comparison circuit, 440: match line, 450: insulation circuit, 460: data storage circuit, 462, 464: p-channel transistor, 463: second I / O node, 465 (first) I /
O node, 466, 468... N-channel transistor,
500: column controller, 600: output controller, 61
0: first encoder, 800: global match line, 9
00: Input control block, 910: Data in register, 912: Data buffer, 914: Coparend, 9
50 ... Address decoding, 972 ... Address input device.

Continued on the front page (72) Robert N. Inventor. Vailby United States 94566 Pleasanton Del Valle Court California 265

Claims (24)

[Claims] An array of programmable interconnected logic cells suitable for use in performing a programmed logic function, and an array of logic cells programmably coupled to the array of logic cells, each in a first mode. As a first type of memory,
A dual mode memory block having an array of dual mode memory cells suitable for operating as a second type of memory in a second mode; and the dual mode memory block for operating in either the first mode or the second mode. A mode control switching circuit suitable for selectively enabling dual mode memory cells. 2. The programmable logic circuit according to claim 1, wherein each of the dual mode memory cells acts as a content addressable memory cell in the first mode and a random access memory in the second mode. A programmable logic circuit that is suitable to act as. 3. The programmable logic circuit according to claim 1, wherein each of the dual mode memory cells includes: a data storage circuit for storing data; and data and request data stored in the data storage circuit. A match line for indicating whether the stored data matches the request data, and an insulation circuit for insulating the data storage circuit from the comparison circuit and the match line. A programmable logic circuit comprising: 4. The programmable logic circuit according to claim 3, wherein the isolation circuit is coupled to the mode control switching circuit, and stores the comparison circuit and the match line in the first mode. A programmable logic circuit electrically coupled to a circuit and configured to electrically decouple the comparison circuit and the match line from the data storage circuit in the second mode. 5. The programmable logic circuit according to claim 3, wherein said comparison circuit outputs a match address when said storage data matches said request data. 6. The programmable logic circuit according to claim 1, wherein said dual mode memory cells each include a column data input of a plurality of dual mode memory cells;
A programmable logic circuit arranged in a column of a plurality of dual mode memory cells having a column address of the plurality of dual mode memory cells and a column output of the at least one dual mode memory cell, and a row of the plurality of dual mode memory cells. . 7. The programmable logic circuit according to claim 6, wherein said dual mode memory block includes a plurality of column controller data inputs, a plurality of column controller address inputs, and a column data input of a selected dual mode memory cell. A column controller having a plurality of column controller data outputs coupled thereto and suitable for selecting a column of the requested dual mode memory cell; a plurality of row controller address inputs; and at least one row controller output. A row control device having a plurality of programmable data input lines programmably coupled to a column control device data input; a first plurality of programmable address input lines programmably coupled to the column control device address input; Connect multiple programmable address input lines to the row An input control device configured to programmably couple to an address input of the control device; and an output control device programmably coupling a column output of the at least one dual mode memory cell to a plurality of output drivers. , Programmable logic circuits. 8. The programmable logic circuit according to claim 6, wherein each of the dual mode memory cells further comprises a data storage circuit, a column data input of the associated dual mode memory, and a column output of the associated dual mode memory cell. A programmable logic circuit including a plurality of coupled dual mode memory cell data lines and a row line selectively coupled to an output of a row controller. 9. The programmable logic circuit as recited in claim 7, wherein said input control device further comprises: a first plurality of composite inputs programmably coupled to a plurality of programmable data input lines; and a plurality of column control devices. A companding device having a compare output coupled to a data input and used to store the request data; a plurality of data-in inputs programmably coupled to the plurality of programmable data input lines; and A data-in device having a data-in output coupled to the data inputs of the plurality of column controllers; and a data-in device programmably coupled to the first plurality of programmable address lines and coupled to the address inputs of the plurality of column controllers. A first address output having a plurality of first address outputs coupled thereto; A first address device and a second address device programmably coupled to a second plurality of programmable address lines and having a plurality of second address outputs coupled to an address input of the row control device. Logic circuit. 10. The programmable logic circuit according to claim 7, wherein said output control device is further coupled to a first encoder for receiving said match address and a column output of said at least one content addressable memory cell. A plurality of output buffers having a plurality of output buffer inputs and a plurality of outputs programmably coupled to the plurality of output drivers. 11. The programmable logic circuit according to claim 10, wherein said first encoder can generate a cis-match flag indicating the number of match addresses for said request data. 12. The programmable logic circuit according to claim 10, wherein said first encoder is capable of storing a plurality of said match addresses. 13. An array of programmably interconnected logic cells suitable for use in performing a program logic function, and a content addressable programmably coupled to the array of logic cells in a first mode. A dual mode memory block configured to act as a memory and to act as a random access memory in the second mode. 14. The programmable logic circuit according to claim 13, wherein said dual mode memory block acts as a static random access memory in said second mode. 15. The programmable logic circuit according to claim 13, wherein said dual mode memory blocks each have a content addressable memory cell,
And an array of dual mode memory cells suitable for acting as a static random access memory, wherein the programmable logic circuit further comprises the dual mode memory cell for acting as a content addressable memory cell or a random access memory cell. And a mode control switching circuit suitable for selectively enabling. 16. An array of programmable interconnected logic cells suitable for use in performing a program logic function, and an address location programmably coupled to said array of logic cells and corresponding to a requested data word. And a content addressable memory block configured to output the same. 17. The programmable logic circuit according to claim 16, further comprising: a mode control switching circuit coupled to said content addressable memory block for enabling said content addressable memory block to act as a random access memory cell. A programmable logic circuit. 18. The programmable logic circuit according to claim 17, wherein said mode control switching circuit enables said content addressable memory block to act as a static random access memory cell. 19. An array of programmatically interconnected logic blocks suitable for use in performing program logic functions, and a content addressable programmably coupled to the array of logic blocks in a first mode. A dual mode memory block configured to act as a memory and to act as a random access memory in the second mode. 20. The programmable logic circuit according to claim 19, wherein said dual mode memory block acts as a static random access memory in said second mode. 21. The programmable logic circuit according to claim 19, wherein each of the dual mode memory blocks comprises a content addressable memory cell.
Or an array of dual mode memory cells suitable to act as a static random access memory, wherein the programmable logic circuit further comprises the dual mode memory cell to act as a content addressable memory cell or a random access memory cell. A programmable logic circuit comprising a mode control switching circuit suitable for selectively enabling. 22. A dual mode memory circuit configured to act as a content addressable memory in a first mode and to act as a random access memory in a second mode, for storing data. A data storage circuit; a comparison circuit for comparing data stored in the data storage circuit with request data; and a match line for indicating whether the storage data matches the request data. A dual mode memory circuit, comprising: an insulation circuit for electrically insulating the data storage circuit from the comparison circuit and the match line. 23. The dual mode memory circuit according to claim 22, wherein said data storage circuit comprises first and second data storage circuits.
A dual mode memory circuit having an output node, wherein the comparison circuit has first and second comparator circuits. 24. The dual mode memory circuit according to claim 22, wherein the isolation circuit is electrically coupled to the first comparator circuit of the comparison circuit and the first output node of the data storage circuit. A mode control switching circuit having a first insulating transistor and a second insulating transistor electrically coupled to the second comparator circuit of the comparing circuit and the second output node of the data storage circuit; A dual mode memory circuit wherein the first and second isolation transistors are operated via a mode control switching circuit.