JPH1174230A - Manufacture of thin-film semiconductor device - Google Patents

Manufacture of thin-film semiconductor device

Info

Publication number
JPH1174230A
JPH1174230A JP9233799A JP23379997A JPH1174230A JP H1174230 A JPH1174230 A JP H1174230A JP 9233799 A JP9233799 A JP 9233799A JP 23379997 A JP23379997 A JP 23379997A JP H1174230 A JPH1174230 A JP H1174230A
Authority
JP
Japan
Prior art keywords
adhesive
support plate
semiconductor element
semiconductor
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9233799A
Other languages
Japanese (ja)
Inventor
Hideyuki Unno
秀之 海野
Oku Kuraki
億 久良木
Manabu Henmi
学 逸見
Shinichi Ofuji
晋一 大藤
Shigeo Ogawa
重男 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP9233799A priority Critical patent/JPH1174230A/en
Publication of JPH1174230A publication Critical patent/JPH1174230A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a thin-film semiconductor device, without causing cracks and chips in a production process even if the thickness of the semiconductor device is 100 μm or less. SOLUTION: A first supporting plate 23 is adhered to a circuit formed face 12a of a semiconductor substrate 21 with a first adhesive 22, which allows adhesive force after adhering to reduce. After performing thin-film deposition processing on the rear face of the semiconductor substrate 21, a second supporting plate 25 is adhered to the rear face of the semiconductor substrate with a second adhesive 24 which allows adhesive force after adhering to be reduced. After the first adhesive 21 and the first supporting plate 23 have been peeled, a dicing tape is stuck to the rear face of the second supporting plate 25 to divide the semiconductor substrate 21, and then second supporting plate 25 is peeled off.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、薄膜状に形成した
半導体素子を実装基板に実装する薄膜半導体装置の製造
方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film semiconductor device in which a semiconductor element formed in a thin film shape is mounted on a mounting substrate.

【0002】[0002]

【従来の技術】従来、半導体素子は、半導体基板(ウエ
ハ)に集積回路を多数形成し、これらの集積回路毎に半
導体基板を分割することによって形成している。集積回
路は、半導体基板に表面から内部へ不純物を拡散させた
後に半導体基板の表面上に絶縁膜や導電膜を設けること
によって形成している。半導体素子の集積回路部分の厚
みは数μm程度で、半導体素子の種類によっては1μm
に満たない場合もある。これに対して、半導体基板の厚
みは数百μmである。このように半導体基板を集積回路
部分に対して大幅に厚く形成するのは、半導体素子に強
度をもたせてハンドリング時に破損するのを阻止するた
めである。
2. Description of the Related Art Conventionally, a semiconductor element is formed by forming a large number of integrated circuits on a semiconductor substrate (wafer) and dividing the semiconductor substrate for each of these integrated circuits. An integrated circuit is formed by diffusing impurities from the surface to the inside of a semiconductor substrate and then providing an insulating film or a conductive film on the surface of the semiconductor substrate. The thickness of the integrated circuit portion of the semiconductor element is about several μm, and 1 μm depending on the type of the semiconductor element.
In some cases. On the other hand, the thickness of the semiconductor substrate is several hundred μm. The reason why the semiconductor substrate is formed to be much thicker than the integrated circuit portion is to increase the strength of the semiconductor element and prevent the semiconductor element from being damaged during handling.

【0003】半導体基板の厚みが厚いと半導体素子毎に
分割し難いばかりか、形成された半導体素子も厚くなっ
てこれを封止するパッケージも厚くなってしまう。従来
の半導体装置のパッケージの一例を図5に示す。
When the thickness of the semiconductor substrate is large, not only is it difficult to divide the semiconductor element into individual semiconductor elements, but also the formed semiconductor element becomes thick and the package for encapsulating the semiconductor element becomes thick. FIG. 5 shows an example of a package of a conventional semiconductor device.

【0004】図5は従来の半導体装置の断面図である。
同図において、符号1はパッケージを示し、2は半導体
素子を示す。前記パッケージ1は、凹陥部1aに半導体
素子2を接着し、凹陥部1aの開口部分を蓋体3によっ
て閉塞する構造を採っている。また、半導体素子2の電
極(図示せず)は、金あるいはアルミニウムなどからな
るボンディングワイヤ4によってパッケージ内の端子
(図示せず)に接続している。
FIG. 5 is a sectional view of a conventional semiconductor device.
In the figure, reference numeral 1 denotes a package, and 2 denotes a semiconductor element. The package 1 has a structure in which the semiconductor element 2 is adhered to the recess 1 a and the opening of the recess 1 a is closed by the lid 3. Further, an electrode (not shown) of the semiconductor element 2 is connected to a terminal (not shown) in the package by a bonding wire 4 made of gold or aluminum.

【0005】このように構成したパッケージ1は、半導
体素子2の厚みに対応させて凹陥部1aを深く形成しな
ければならないので、半導体素子2の厚みが厚ければ厚
いほどパッケージ1の厚みが厚くなってしまう。このた
め、従来では、半導体基板を半導体素子毎に分割する以
前に研削によって半導体基板の裏面を削り、半導体基板
の厚みを薄くしている。半導体基板の裏面に研削を施す
半導体装置の製造方法を図6(a)〜(f)によって説
明する。
In the package 1 configured as described above, the concave portion 1a must be formed deeply in accordance with the thickness of the semiconductor element 2, so that the thicker the semiconductor element 2, the larger the thickness of the package 1. turn into. For this reason, in the related art, the back surface of the semiconductor substrate is ground by grinding before dividing the semiconductor substrate into individual semiconductor elements, thereby reducing the thickness of the semiconductor substrate. A method of manufacturing a semiconductor device in which the back surface of a semiconductor substrate is ground will be described with reference to FIGS.

【0006】図6(a)〜(f)は従来の半導体装置の
製造方法を説明するための断面図である。これらの図に
おいて、符号5は集積回路が形成された半導体基板を示
し、6は表面保護用テープ、7はダイシング用テープを
示す。また、8は半導体素子、9はパッケージ、10は
ボンディングワイヤを示す。
FIGS. 6A to 6F are cross-sectional views for explaining a conventional method of manufacturing a semiconductor device. In these figures, reference numeral 5 denotes a semiconductor substrate on which an integrated circuit is formed, 6 denotes a surface protection tape, and 7 denotes a dicing tape. Reference numeral 8 denotes a semiconductor element, 9 denotes a package, and 10 denotes a bonding wire.

【0007】研削によって半導体基板5を薄くするため
には、先ず、図6(a)に示すように、集積回路を多数
形成した半導体基板5の回路形成面に表面保護用テープ
6を貼着する。この表面保護用テープ6は、研削中に回
路形成面が傷つくのを阻止する機能と、研削時の押圧力
を緩和する緩衝材としての機能とを有し、ポリエステル
や塩化ビニールなどを基材として厚みが100〜200
μmになるように形成している。
In order to thin the semiconductor substrate 5 by grinding, first, as shown in FIG. 6A, a surface protection tape 6 is attached to a circuit forming surface of the semiconductor substrate 5 on which a large number of integrated circuits are formed. . The surface protection tape 6 has a function of preventing a circuit forming surface from being damaged during grinding and a function as a cushioning material for reducing a pressing force at the time of grinding. 100-200 thickness
It is formed to be μm.

【0008】次に、この半導体基板5を図示してない研
削機に装填する。研削機による研削は、半導体基板5の
回路形成面側の表面保護用テープ6にスピンドルと呼称
されるドリルを押付けるとともに、半導体基板5の裏面
にバックグラインダーの研削砥石を押付けて行う。研削
後の半導体基板5を図6(b)に示す。
Next, the semiconductor substrate 5 is loaded into a grinder (not shown). The grinding by the grinder is performed by pressing a drill called a spindle on the surface protection tape 6 on the circuit forming surface side of the semiconductor substrate 5 and pressing a grinding wheel of a back grinder on the back surface of the semiconductor substrate 5. FIG. 6B shows the semiconductor substrate 5 after the grinding.

【0009】研削後、図6(c)に示すように、半導体
基板5上の表面保護用テープ6を剥離する。この剥離
は、表面保護用テープ6の表面にこれより接着力が大き
い剥離用テープ(図示せず)を貼着し、この剥離用テー
プを半導体基板5に対して剥がすことによって行う。次
に、図6(d)に示すように、半導体基板5の研削後の
裏面にダイシング用テープ7を貼着する。このダイシン
グ用テープ7は、次工程のダイシング工程で半導体素子
が脱落するのを阻止するために使用する。
After grinding, the surface protection tape 6 on the semiconductor substrate 5 is peeled off as shown in FIG. This peeling is performed by attaching a peeling tape (not shown) having a larger adhesive force to the surface of the surface protecting tape 6 and peeling the peeling tape from the semiconductor substrate 5. Next, as shown in FIG. 6D, a dicing tape 7 is adhered to the back surface of the semiconductor substrate 5 after grinding. The dicing tape 7 is used to prevent the semiconductor element from falling off in the next dicing step.

【0010】ダイシング工程では、半導体基板5に回路
形成面側からダイシングソーを押付け、集積回路毎に半
導体基板5を分割して半導体素子8を形成する。このよ
うに形成した半導体素子8は、ダイシング用テープ7か
らそれぞれ取外して図6(f)に示すようにパッケージ
9に実装し、ワイヤボンディングを実施してから樹脂封
止を施す。この封止工程が終了することによって半導体
装置が形成される。
In the dicing step, a dicing saw is pressed against the semiconductor substrate 5 from the circuit forming surface side, and the semiconductor substrate 5 is divided for each integrated circuit to form a semiconductor element 8. The semiconductor elements 8 thus formed are respectively removed from the dicing tape 7, mounted on a package 9 as shown in FIG. 6 (f), subjected to wire bonding, and then subjected to resin sealing. A semiconductor device is formed by completing the sealing step.

【0011】この種の半導体装置を多用する携帯電話機
やビデオカメラのような電子機器においては、小型化、
軽量化を図るために、半導体装置をさらに小型かつ軽量
に形成して半導体装置の実装密度の向上を図ることが要
請されている。
Electronic devices such as mobile phones and video cameras that make extensive use of this type of semiconductor device have been downsized,
In order to reduce the weight, it is required that the semiconductor device be formed smaller and lighter to improve the mounting density of the semiconductor device.

【0012】半導体装置の実装密度は、図5に示したよ
うな半導体装置、すなわち半導体素子2をパッケージ1
に収容する形態を採る半導体装置では、パッケージ1の
大きさで決まる。パッケージ1を使用する限り、実装密
度を向上させるためには限界がある。パッケージを使用
せずに半導体素子を実装基板に接続する構造、いわゆる
フリップチップ構造を採ることによって、パッケージを
使用する場合よりも実装密度を高くすることができる。
フリップチップ構造によって接続した半導体素子と実装
基板を図7に示す。
The packaging density of the semiconductor device is such that the semiconductor device as shown in FIG.
In the case of a semiconductor device that is housed in a package, the size is determined by the size of the package 1. As long as the package 1 is used, there is a limit in improving the mounting density. By employing a structure in which a semiconductor element is connected to a mounting substrate without using a package, that is, a so-called flip-chip structure, the mounting density can be increased as compared with the case where a package is used.
FIG. 7 shows a semiconductor element and a mounting board connected by a flip chip structure.

【0013】図7はフリップチップ構造を示す断面図で
ある。同図において、符号11は半導体素子を示し、1
2は実装基板を示す。半導体素子11は、回路形成面1
1aを実装基板12に対向させ、バンプ13によって電
極(図示せず)を実装基板12の端子(図示せず)に接
続している。
FIG. 7 is a sectional view showing a flip chip structure. In the figure, reference numeral 11 denotes a semiconductor element, and 1
Reference numeral 2 denotes a mounting board. The semiconductor element 11 has a circuit forming surface 1
1 a is opposed to the mounting substrate 12, and an electrode (not shown) is connected to a terminal (not shown) of the mounting substrate 12 by a bump 13.

【0014】図7に示したフリップチップ構造を採るこ
とにより、パッケージの分だけ実装基板12の実装面の
面積を小さくすることができ、実装基板12の軽量化が
可能になる。実装基板12の軽量化により、これを使用
する電子機器の軽量化を図ることができる。
By employing the flip chip structure shown in FIG. 7, the area of the mounting surface of the mounting substrate 12 can be reduced by the amount of the package, and the mounting substrate 12 can be reduced in weight. By reducing the weight of the mounting substrate 12, it is possible to reduce the weight of an electronic device using the same.

【0015】[0015]

【発明が解決しようとする課題】しかるに、上述した電
子機器においては更なる軽量化の要請があり、この要請
に応えるために半導体素子の重量も問題になってきた。
半導体素子の厚みは、図5に示したようにパッケージに
半導体素子を実装する場合には400μm程度であり、
図7に示したフリップチップ構造を採る場合には200
μm程度である。
However, there is a demand for a further weight reduction in the above-described electronic equipment, and the weight of the semiconductor element has become a problem in order to meet this demand.
The thickness of the semiconductor element is about 400 μm when the semiconductor element is mounted on a package as shown in FIG.
In the case where the flip chip structure shown in FIG.
It is about μm.

【0016】半導体素子の厚みを薄くして半導体素子を
薄膜状に形成するためには、前記図6(a)〜(b)に
よって説明した研削工程での研削量を増大させることに
よって実施する。しかし、研削量を増大させると、研削
砥石から加えられる押圧力によって半導体基板が割れた
り欠けたりし易くなるとともに、研削砥石が当たる部分
が僅かに湾曲した状態で研削されることに起因して半導
体基板の厚みのばらつきが大きくなってしまう。また、
図6(c)で説明した表面保護用テープの剥離工程で表
面保護用テープを半導体基板から剥離するときに、半導
体基板が割れてしまうおそれもある。さらに、薄膜状の
半導体基板を分割することによって形成した半導体素子
は、割れないように取扱いが慎重にならざるを得ず、半
導体素子を実装基板に実装する工程などでの作業性が悪
い。
In order to form the semiconductor element into a thin film by reducing the thickness of the semiconductor element, the amount of grinding in the grinding step described with reference to FIGS. 6A and 6B is increased. However, when the grinding amount is increased, the semiconductor substrate is easily broken or chipped due to the pressing force applied from the grinding wheel, and the semiconductor is caused by the fact that the portion hit by the grinding wheel is ground in a slightly curved state. Variations in the thickness of the substrate will increase. Also,
When the surface protection tape is separated from the semiconductor substrate in the surface protection tape separation step described with reference to FIG. 6C, the semiconductor substrate may be broken. Further, a semiconductor element formed by dividing a semiconductor substrate in the form of a thin film must be carefully handled so as not to be broken, and workability in a process of mounting the semiconductor element on a mounting substrate is poor.

【0017】このため、作業性、歩留りを考慮すると、
薄膜化するときの半導体基板の厚みは200μm程度が
限界である。なお、作業性や歩留りを無視すれば半導体
基板の厚みを100μm程度まで薄くすることはできる
が、歩留りが著しく低下してコストアップになってしま
う。すなわち、従来では、工業製品として成り立つ半導
体装置を製造するに当たり、半導体基板(半導体素子)
を厚みが100μm以下になるように形成することは困
難であった。
For this reason, considering workability and yield,
The limit of the thickness of the semiconductor substrate when thinning is about 200 μm. If the workability and the yield are neglected, the thickness of the semiconductor substrate can be reduced to about 100 μm, but the yield is significantly reduced and the cost is increased. That is, conventionally, when manufacturing a semiconductor device that can be realized as an industrial product, a semiconductor substrate (semiconductor element)
Was difficult to form so that the thickness was 100 μm or less.

【0018】本発明はこのような問題点を解消するため
になされたもので、半導体素子の厚みが100μm以下
でも製造工程で割れや欠けが生じることがない薄膜半導
体装置の製造方法を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and it is an object of the present invention to provide a method of manufacturing a thin film semiconductor device which does not cause cracking or chipping in the manufacturing process even when the thickness of the semiconductor element is 100 μm or less. With the goal.

【0019】[0019]

【課題を解決するための手段】本発明に係る薄膜半導体
装置の製造方法は、半導体基板の回路形成面に接着後に
接着力を低下させることが可能な第1の接着剤によって
第1の支持板を接着し、半導体基板に裏面側から薄膜化
処理を施した後、接着後に接着力を低下させることが可
能な第2の接着剤によって半導体基板裏面に第2の支持
板を接着し、第1の接着剤および第1の支持板を剥離し
た後、第2の支持板の裏面にダイシング用テープを貼着
して半導体基板を分割し、第2の支持板を剥離すること
によって実施する。
According to a method of manufacturing a thin film semiconductor device according to the present invention, a first support plate is provided with a first adhesive capable of reducing an adhesive force after bonding to a circuit forming surface of a semiconductor substrate. After the semiconductor substrate is subjected to a thinning process from the back surface side, the second support plate is bonded to the back surface of the semiconductor substrate with a second adhesive capable of reducing the adhesive force after the bonding, After the adhesive and the first support plate are peeled off, a dicing tape is attached to the back surface of the second support plate to divide the semiconductor substrate, and the second support plate is peeled off.

【0020】本発明によれば、半導体基板の薄膜化処理
を実施するときから半導体素子を実装基板に実装するま
での間の全ての工程において、半導体基板および半導体
素子を第1の支持板あるいは第2の支持板が補強する。
また、第1の支持板や第2の支持板を剥離するときに半
導体基板あるいは半導体素子に無理な力が加わることは
ない。
According to the present invention, the semiconductor substrate and the semiconductor element are connected to the first support plate or the first support plate in all steps from the time when the semiconductor substrate is thinned to the time when the semiconductor element is mounted on the mounting substrate. The second support plate reinforces.
Further, when the first support plate or the second support plate is peeled, no excessive force is applied to the semiconductor substrate or the semiconductor element.

【0021】他の発明に係る薄膜半導体装置の製造方法
は、上述した発明に係る薄膜半導体装置の製造方法にお
いて、半導体基板を分割して半導体素子を形成した後、
第2の接着剤の接着力を低下させる以前に、バンプを介
して半導体素子を実装基板に実装することによって実施
する。
According to another aspect of the invention, there is provided a method of manufacturing a thin film semiconductor device, comprising the steps of:
Before the adhesive force of the second adhesive is reduced, the semiconductor device is mounted on the mounting substrate via the bump.

【0022】本発明によれば、実装工程で第2の支持板
を把持しながら実装作業を実施することができる。
According to the present invention, the mounting operation can be performed while holding the second support plate in the mounting step.

【0023】他の発明に係る薄膜半導体装置の製造方法
は、半導体基板の回路形成面に半導体素子を囲むように
凹溝を格子状に形成し、接着後に接着力を低下させるこ
とが可能な第1の接着剤によって前記回路形成面に第1
の支持板を接着し、半導体基板に裏面側から薄膜化処理
を前記凹溝が露出するまで実施した後、接着後に接着力
を低下させることが可能な第2の接着剤によって半導体
基板の裏面に第2の支持板を接着し、しかる後、第1の
接着剤および前記第1の支持板を半導体素子から剥離
し、バンプを介して前記半導体素子を実装基板に実装し
てから第2の支持板を剥離することによって実施する。
According to another aspect of the present invention, there is provided a method of manufacturing a thin film semiconductor device in which concave grooves are formed in a lattice shape on a circuit forming surface of a semiconductor substrate so as to surround a semiconductor element, and the bonding force can be reduced after bonding. The first adhesive is applied to the circuit forming surface by the first adhesive.
After performing the thinning process from the back surface side to the semiconductor substrate until the concave groove is exposed, a second adhesive capable of reducing the adhesive force after the bonding is applied to the back surface of the semiconductor substrate. After bonding the second support plate, the first adhesive and the first support plate are peeled off from the semiconductor element, and the semiconductor element is mounted on a mounting substrate via bumps, and then the second support This is performed by peeling the board.

【0024】本発明によれば、半導体基板の薄膜化処理
工程から実装工程に至る全ての工程において、半導体基
板および半導体素子を第1の支持板あるいは第2の支持
板が補強する。また、第1の支持板や第2の支持板を剥
離するときに半導体基板あるいは半導体素子に無理な力
が加わることはない。さらに、全ての半導体素子を一つ
の第2の支持板によって保持させた状態で実装基板に実
装することができる。
According to the present invention, the semiconductor substrate and the semiconductor element are reinforced by the first support plate or the second support plate in all steps from the step of thinning the semiconductor substrate to the step of mounting. Further, when the first support plate or the second support plate is peeled, no excessive force is applied to the semiconductor substrate or the semiconductor element. Further, all the semiconductor elements can be mounted on the mounting board while being held by one second support plate.

【0025】ここで、第1の接着剤や第2の接着剤は、
加熱されることによって接着力が低下するものや、紫外
線が照射されることによって接着力が低下するものや、
水に触れることによって接着力が低下するものなどを使
用する。また、第1の接着剤と第2の接着剤とで接着力
を低下させる手法が異なるようにすることによって、第
1の接着剤を剥離するときに第2の接着剤が剥離しない
ようにすることができる。
Here, the first adhesive and the second adhesive are:
Those whose adhesive strength is reduced by being heated, those whose adhesive strength is reduced by being irradiated with ultraviolet light,
Use a material whose adhesive strength is reduced by contact with water. In addition, the first adhesive and the second adhesive are made different in the method of reducing the adhesive force so that the second adhesive does not peel when the first adhesive is peeled. be able to.

【0026】[0026]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

第1の実施の形態 以下、本発明に係る薄膜半導体装置の製造方法を図1お
よび図2によって詳細に説明する。図1および図2は本
発明に係る薄膜半導体装置の製造方法を説明するための
断面図で、図1は製造工程の前半を示し、図2は製造工
程の後半を示す。
First Embodiment Hereinafter, a method for manufacturing a thin film semiconductor device according to the present invention will be described in detail with reference to FIGS. 1 and 2 are cross-sectional views for explaining a method of manufacturing a thin film semiconductor device according to the present invention. FIG. 1 shows the first half of the manufacturing process, and FIG. 2 shows the latter half of the manufacturing process.

【0027】これらの図において、符号21は集積回路
を形成した半導体基板を示す。この半導体基板21は、
図面の上側が回路形成面21aになっている。22は第
1の接着剤、23は第1の支持板、24は第2の接着
剤、25は第2の支持板を示す。
In these figures, reference numeral 21 indicates a semiconductor substrate on which an integrated circuit is formed. This semiconductor substrate 21
The upper side of the drawing is the circuit forming surface 21a. Reference numeral 22 denotes a first adhesive, 23 denotes a first support plate, 24 denotes a second adhesive, and 25 denotes a second support plate.

【0028】前記第1の接着剤22および第2の接着剤
24は、接着後に何らかの処理を施すことによって接着
力が低下するものを採用している。例えば、加熱される
ことによって発泡して接着力が低下する性質のものや、
紫外線が照射されることによって硬化して接着力が低下
する性質のものや、水に触れることによって接着力が低
下する性質のものを使用する。なお、これらの接着剤2
2,24は、接着前にはどのような形態でもよい。例え
ば、液状、ゲル状、シート状の何れでもよい。
As the first adhesive 22 and the second adhesive 24, those whose adhesive strength is reduced by performing some processing after bonding are employed. For example, those that have the property of reducing the adhesive strength by foaming when heated,
A material having a property of being reduced by being irradiated with ultraviolet rays and having a reduced adhesive strength, or a material having a property of being reduced in adhesive strength when exposed to water is used. In addition, these adhesives 2
2, 24 may be in any form before bonding. For example, it may be liquid, gel, or sheet.

【0029】前記第1の支持板23および第2の支持板
25は、例えばガラス板やシリコンウエハのような半導
体基板と同等の硬度をもつ材料によって形成する。ま
た、これらの支持板23,25の厚みは、薄膜化する以
前の半導体基板21と同等程度が望ましい。
The first support plate 23 and the second support plate 25 are formed of a material having the same hardness as a semiconductor substrate such as a glass plate or a silicon wafer. Further, it is desirable that the thicknesses of these support plates 23 and 25 are approximately equal to the thickness of the semiconductor substrate 21 before being thinned.

【0030】図2において符号26はダイシング用テー
プを示し、27は半導体基板21を分割してなる半導体
素子を示す。また、図2(c),(d)において符号2
8は実装基板を示し、29はバンプを示す。
In FIG. 2, reference numeral 26 denotes a dicing tape, and 27 denotes a semiconductor element obtained by dividing the semiconductor substrate 21. 2 (c) and 2 (d).
8 indicates a mounting board, and 29 indicates a bump.

【0031】次に、この実施の形態による薄膜半導体装
置の製造方法を説明する。先ず、図1(a)に示すよう
に半導体基板21の回路形成面21aに第1の接着剤2
2の層を設ける。このとき、第1の接着剤22の接着前
の形態が液状やゲル状であればこれを回路形成面21a
に塗布し、接着前の形態がシート状であれば回路形成面
21aに押付けて接着する。第1の接着剤22を塗布す
る場合には、刷毛を使用したり、スピンコート法を採用
することができる。
Next, a method of manufacturing the thin film semiconductor device according to this embodiment will be described. First, as shown in FIG. 1A, a first adhesive 2 is applied to a circuit forming surface 21a of a semiconductor substrate 21.
Two layers are provided. At this time, if the form of the first adhesive 22 before bonding is in a liquid or gel state, it is changed to the circuit forming surface 21a.
If the form before bonding is a sheet, it is pressed against and bonded to the circuit forming surface 21a. When applying the first adhesive 22, a brush can be used or a spin coating method can be adopted.

【0032】その後、図1(b)に示すように、前記第
1の接着剤22を介して回路形成面21上に第1の支持
板23を接着する。次いで、この半導体基板21を第1
の支持板23とともに研削機(図示せず)に装填し、バ
ックグラインダーで半導体基板21の裏面に研削を施
す。研削終了後、前記裏面に研磨あるいは化学的エッチ
ングを施し、半導体基板21を厚みが100μm以下の
薄膜状に形成する。従来では、ここまでの工程で半導体
基板21に割れや欠けが生じることなく歩留りよく厚み
を100μm以下にすることは困難であった。しかし、
この製造方法によれば、第1の支持板23が半導体基板
21を補強するから、半導体基板21を厚みが100μ
m以下になるまで薄膜化することができる。なお、この
薄膜化処理工程では、バックグラインダーによる研削を
実施せずに最初から研磨あるいは化学的エッチングを施
してもよい。
Thereafter, as shown in FIG. 1B, a first support plate 23 is bonded on the circuit forming surface 21 via the first adhesive 22. Next, the semiconductor substrate 21 is
Is mounted on a grinder (not shown) together with the support plate 23 of FIG. 1, and the back surface of the semiconductor substrate 21 is ground by a back grinder. After the grinding, the back surface is polished or chemically etched to form the semiconductor substrate 21 into a thin film having a thickness of 100 μm or less. Conventionally, it has been difficult to reduce the thickness to 100 μm or less with good yield without cracking or chipping of the semiconductor substrate 21 in the steps up to here. But,
According to this manufacturing method, since the first support plate 23 reinforces the semiconductor substrate 21, the semiconductor substrate 21 has a thickness of 100 μm.
m or less. In the thinning process, polishing or chemical etching may be performed from the beginning without performing grinding with a back grinder.

【0033】このように薄膜状に半導体基板21を形成
した後、第1の支持板23を把持した状態で図1(d)
に示すように半導体基板21の裏面に第2の接着剤24
からなる層を設ける。この層の形成方法は、第1の接着
剤22の層を設ける場合と同じである。しかし、第2の
接着剤24は、第1の接着剤22とは接着力を低下させ
る手法が異なるものを使用する。例えば、第1の接着剤
22として加熱されることにより接着力が低下する性質
のものを用いた場合には、第2の接着剤24は、加熱に
よっては接着力が低下することがない性質のもの、すな
わち紫外線照射や水との反応などで接着力が低下する性
質のものを用いる。
After the semiconductor substrate 21 is formed into a thin film as described above, the first support plate 23 is gripped in FIG.
As shown in FIG. 3, the second adhesive 24
Is provided. The method of forming this layer is the same as the case where the layer of the first adhesive 22 is provided. However, the second adhesive 24 is different from the first adhesive 22 in a method of reducing the adhesive force. For example, in the case where a material having a property that the adhesive force is reduced by being heated as the first adhesive 22 is used, the second adhesive 24 has a property that the adhesive force is not reduced by heating. An adhesive having a property that the adhesive strength is reduced by ultraviolet irradiation or reaction with water is used.

【0034】次に、図1(e)に示すように、半導体基
板21の裏面に前記第2の接着剤24を介して第2の支
持板25を接着し、第1の接着剤22の接着力が低下す
る処理を施して第1の接着剤22および第1の支持板2
3を半導体基板21から剥離し、図1(f)に示すよう
に、半導体基板21の回路形成面21を露出させる。第
1の接着剤22および第1の支持板23の剥離は、第2
の支持板25を把持した状態で行う。なお、第2の接着
剤24は、第1の接着剤22とは異なる性質のものを使
用しているため、第1の接着剤22に対して接着力が低
下する処理を施しても接着力が低下することはない。
Next, as shown in FIG. 1E, a second support plate 25 is adhered to the back surface of the semiconductor substrate 21 via the second adhesive 24, and the first adhesive 22 is adhered. The first adhesive 22 and the first support plate 2
3 is peeled off from the semiconductor substrate 21 to expose the circuit forming surface 21 of the semiconductor substrate 21 as shown in FIG. The peeling of the first adhesive 22 and the first support plate 23
This is performed in a state where the support plate 25 is gripped. Since the second adhesive 24 has a property different from that of the first adhesive 22, even if a process for reducing the adhesive strength is performed on the first adhesive 22, the adhesive strength is reduced. Does not decrease.

【0035】その後、図2(a)に示すように、第2の
支持板25の裏面にダイシング用テープ26を貼着し、
図2(b)に示すように、従来周知のダイシングソーな
どによって半導体基板21を集積回路毎に分割する。こ
のとき、ダイシングソーの刃(図示せず)が第2の支持
板25にも達するようにして第2の支持板25も半導体
基板21と同時に分割する。このように半導体基板21
を分割することによって半導体素子27が形成される。
Thereafter, as shown in FIG. 2A, a dicing tape 26 is adhered to the back surface of the second support plate 25,
As shown in FIG. 2B, the semiconductor substrate 21 is divided into integrated circuits by a conventionally known dicing saw or the like. At this time, the second support plate 25 is also split at the same time as the semiconductor substrate 21 so that the blade (not shown) of the dicing saw reaches the second support plate 25. Thus, the semiconductor substrate 21
Is divided to form the semiconductor element 27.

【0036】そして、分割後の第2の支持板25をダイ
シング用テープ26から外す。第2の支持板25を外し
た後の実装工程では、半導体素子27の代わりに第2の
支持板25を把持して実装を行う。この実装は、従来周
知のフリップチップ構造が実現されるように行う。すな
わち、図2(c)に示すように、半導体素子27の回路
形成面を実装基板28の実装面に対向させ、バンプ29
を介して半導体素子27を実装基板28に接続する。
Then, the divided second support plate 25 is removed from the dicing tape 26. In the mounting process after removing the second support plate 25, the second support plate 25 is gripped and mounted instead of the semiconductor element 27. This mounting is performed so as to realize a conventionally known flip chip structure. That is, as shown in FIG. 2C, the circuit forming surface of the semiconductor element 27 is opposed to the mounting surface of the mounting substrate 28, and the bump 29
The semiconductor element 27 is connected to the mounting substrate 28 via the.

【0037】実装終了後、第2の接着剤24に対して接
着力が低下する処理を施し、図2(d)に示すように、
第2の接着剤24および第2の支持板25を半導体素子
27から剥離する。なお、このときには、第2の支持板
25のみを剥離して第2の接着剤24を半導体素子27
の裏面に残しておいてもよい。重量軽減の観点からは第
2の接着剤24も剥離することが望ましい。
After the mounting is completed, the second adhesive 24 is subjected to a process of reducing the adhesive strength, and as shown in FIG.
The second adhesive 24 and the second support plate 25 are separated from the semiconductor element 27. At this time, only the second support plate 25 is peeled off, and the second adhesive 24 is applied to the semiconductor element 27.
May be left behind. From the viewpoint of weight reduction, it is desirable that the second adhesive 24 is also peeled off.

【0038】このように半導体素子27を実装基板28
に実装した後、従来周知の封止構造により半導体素子2
7を封止することによって、半導体素子27の厚みが1
00μm以下の薄膜半導体装置を製造することができ
る。
As described above, the semiconductor element 27 is mounted on the mounting board 28.
After mounting on the semiconductor element 2 by a conventionally well-known sealing structure.
7, the semiconductor element 27 has a thickness of 1
It is possible to manufacture a thin film semiconductor device having a thickness of not more than 00 μm.

【0039】したがって、上述した製造方法によれば、
半導体基板21に薄膜化処理を実施する工程から実装工
程までの間の全ての工程において、半導体基板21およ
び半導体素子27を第1の支持板23あるいは第2の支
持板25が補強するから、製造工程の途中で薄膜状の半
導体基板21や半導体素子27が割れたり欠けたりする
ことはない。また、第1の支持板23や第2の支持板2
5を剥離するときに半導体基板21あるいは半導体素子
27に無理な力が加わることはない。
Therefore, according to the above-described manufacturing method,
Since the semiconductor substrate 21 and the semiconductor element 27 are reinforced by the first support plate 23 or the second support plate 25 in all the steps from the step of performing the thinning process on the semiconductor substrate 21 to the mounting step, The semiconductor substrate 21 and the semiconductor element 27 in the form of a thin film are not broken or chipped during the process. In addition, the first support plate 23 and the second support plate 2
When peeling 5, no excessive force is applied to the semiconductor substrate 21 or the semiconductor element 27.

【0040】さらに、第2の支持板25を把持しながら
実装作業を実施することができるから、半導体素子27
が薄膜状でも実装作業の作業性がよく、しかも、実装作
業中に半導体素子27が割れることもない。
Further, since the mounting operation can be performed while holding the second support plate 25, the semiconductor element 27
The workability of the mounting operation is good even when the thin film is used, and the semiconductor element 27 is not broken during the mounting operation.

【0041】なお、この実施の形態では、半導体素子2
7を実装基板28に接続するためにフリップチップ構造
を採用したが、図5に示したように、パッケージに半導
体素子27を接着してボンディングワイヤで接続する構
造を採ることもできる。
In this embodiment, the semiconductor device 2
Although a flip-chip structure is employed to connect the semiconductor chip 7 to the mounting substrate 28, a structure in which the semiconductor element 27 is bonded to a package and connected by bonding wires as shown in FIG. 5 can also be employed.

【0042】第2の実施の形態 他の発明に係る薄膜半導体装置の製造方法の一実施の形
態を図3および図4によって詳細に説明する。図3およ
び図4は他の発明に係る薄膜半導体装置の製造方法を説
明するための断面図で、図3は製造工程の前半を示し、
図4は製造工程の後半を示す。これらの図において前記
図1および図2で説明したものと同一もしくは同等部材
については、同一符号を付し詳細な説明は省略する。
Second Embodiment One embodiment of a method of manufacturing a thin film semiconductor device according to another invention will be described in detail with reference to FIGS. 3 and 4 are cross-sectional views for explaining a method of manufacturing a thin film semiconductor device according to another invention. FIG. 3 shows the first half of the manufacturing process.
FIG. 4 shows the latter half of the manufacturing process. In these figures, the same or equivalent members as those described in FIG. 1 and FIG. 2 are denoted by the same reference numerals, and detailed description is omitted.

【0043】この実施の形態による薄膜半導体装置の製
造方法を実施するためには、先ず、図3(a)に示すよ
うに、半導体基板21の回路形成面21aに集積回路
(半導体素子になる部分)を囲むように凹溝31を格子
状に形成する。この凹溝31は、ダイシングソー(図示
せず)の刃を回路形成面21a上のスクライブライン
(図示せず)に沿って移動させることによって形成す
る。
In order to carry out the method of manufacturing a thin film semiconductor device according to this embodiment, first, as shown in FIG. 3A, an integrated circuit (a part to be a semiconductor element) is formed on a circuit forming surface 21a of a semiconductor substrate 21. ) Are formed in a lattice shape so as to surround the groove. The concave groove 31 is formed by moving a blade of a dicing saw (not shown) along a scribe line (not shown) on the circuit forming surface 21a.

【0044】凹溝31の深さは、形成する半導体素子の
厚みと同じにする。例えば、厚みが50μmの半導体素
子を形成する場合には、凹溝31を深さが50μmにな
るように形成する。なお、凹溝31はダイシングソーで
形成する他に、化学的エッチングなどの他の手法によっ
て形成することもできる。
The depth of the groove 31 is the same as the thickness of the semiconductor element to be formed. For example, when a semiconductor element having a thickness of 50 μm is formed, the concave groove 31 is formed so as to have a depth of 50 μm. In addition, the concave groove 31 can be formed by other methods such as chemical etching in addition to the dicing saw.

【0045】次に、図3(b)に示すように、回路形成
面21a上に第1の接着剤22からなる層を設ける。こ
の層の形成方法は第1の実施の形態を採るときと同じで
ある。そして、図3(c)に示すように、半導体基板2
1上に前記第1の接着剤22を介して第1の支持板23
を接着する。
Next, as shown in FIG. 3B, a layer made of the first adhesive 22 is provided on the circuit forming surface 21a. The method of forming this layer is the same as when the first embodiment is employed. Then, as shown in FIG.
1 on the first support plate 23 via the first adhesive 22
Glue.

【0046】第1の支持板23を接着した後、半導体基
板21を第1の支持板ともに研削機(図示せず)に装填
し、バックグラインダーで半導体基板21の裏面に研削
を施す。この研削は、図3(d)に示すように、前記凹
溝31が露出するまで実施する。この研削工程が終了す
ることにより、半導体基板21から集積回路部分を残し
て余分な部分が削除され、半導体素子27が形成され
る。
After bonding the first support plate 23, the semiconductor substrate 21 is loaded together with the first support plate into a grinder (not shown), and the back surface of the semiconductor substrate 21 is ground by a back grinder. This grinding is performed until the groove 31 is exposed, as shown in FIG. When this grinding step is completed, an extra portion is removed from the semiconductor substrate 21 except for the integrated circuit portion, and the semiconductor element 27 is formed.

【0047】半導体基板21を薄膜状に形成するために
は、研磨や化学的エッチングによっても実施することが
できるし、前記研削とこれらとを組合わせて実施するこ
ともできる。この実施の形態を採るときでも第1の支持
板23が半導体基板21を補強するから、半導体基板2
1を厚みが100μm以下になるまで薄膜化することが
できる。
The semiconductor substrate 21 can be formed into a thin film by polishing or chemical etching, or by a combination of the above-mentioned grinding and these. Since the first support plate 23 reinforces the semiconductor substrate 21 even when this embodiment is adopted, the semiconductor substrate 2
1 can be thinned to a thickness of 100 μm or less.

【0048】このように半導体基板21に薄膜化処理を
施して半導体素子27を形成した後、第1の支持板23
を把持した状態で図3(e)に示すように半導体素子2
7の裏面に第2の接着剤24からなる層を設ける。この
層の形成方法や、第2の接着剤24の性質を選択する手
法も第1の実施の形態を採るときと同じである。そし
て、図4(a)に示すように、半導体素子27の裏面に
前記第2の接着剤24を介して第2の支持板25を接着
する。
After thinning the semiconductor substrate 21 to form the semiconductor element 27, the first support plate 23
While holding the semiconductor device, as shown in FIG.
7 is provided with a layer made of the second adhesive 24 on the back surface. The method of forming this layer and the method of selecting the properties of the second adhesive 24 are the same as in the case of the first embodiment. Then, as shown in FIG. 4A, a second support plate 25 is bonded to the back surface of the semiconductor element 27 via the second adhesive 24.

【0049】次いで、第1の接着剤22の接着力が低下
する処理を施して第1の接着剤22および第1の支持板
23を半導体素子27から剥離し、図4(b)に示すよ
うに、半導体素子27の回路形成面を露出させる。第1
の接着剤22および第1の支持板23の剥離は、第2の
支持板25を把持した状態で行う。
Next, the first adhesive 22 and the first support plate 23 are peeled off from the semiconductor element 27 by performing a process for reducing the adhesive strength of the first adhesive 22, and as shown in FIG. Then, the circuit formation surface of the semiconductor element 27 is exposed. First
The peeling of the adhesive 22 and the first support plate 23 is performed while the second support plate 25 is gripped.

【0050】その後、図4(c)に示すように、第2の
支持板25上に全ての半導体素子27が固定される状態
で、各半導体素子27を実装基板28にバンプ29を介
して実装する。従来では、テープ状に形成した実装基板
に半導体素子を一つずつ実装していたが、この実施の形
態では、複数の半導体素子27,27‥‥を一度に実装
基板28に実装する。このため、この実施の形態を採る
ときに用いる実装基板28は、半導体素子27を実装す
る実装部28aをシート28b上にマトリックス状に多
数配設した構造を採っている。なお、半導体素子27の
実装基板28への実装は、上述した実装方法を採る他
に、第2の支持板25上の半導体素子27を複数の実装
基板28に実装させることによっても行うことができ
る。この場合には、例えば、実装部28aが一列に並ぶ
テープ状に実装基板28を形成する。
Thereafter, as shown in FIG. 4C, in a state where all the semiconductor elements 27 are fixed on the second support plate 25, each semiconductor element 27 is mounted on the mounting board 28 via the bump 29. I do. Conventionally, semiconductor elements are mounted one by one on a mounting board formed in a tape shape. In this embodiment, a plurality of semiconductor elements 27, 27 # are mounted on the mounting board 28 at one time. For this reason, the mounting substrate 28 used when adopting this embodiment has a structure in which a large number of mounting portions 28a for mounting the semiconductor elements 27 are arranged in a matrix on a sheet 28b. The mounting of the semiconductor element 27 on the mounting board 28 can be performed by mounting the semiconductor element 27 on the second support plate 25 on a plurality of mounting boards 28 in addition to the above-described mounting method. . In this case, for example, the mounting substrate 28 is formed in a tape shape in which the mounting portions 28a are arranged in a line.

【0051】上述したように半導体素子27を実装基板
28に実装した後、第2の接着剤24に対して接着力が
低下する処理を施し、図4(d)に示すように、第2の
接着剤24および第2の支持板25を半導体素子27か
ら剥離する。なお、このときには、第2の支持板25の
みを剥離して第2の接着剤24を半導体素子27の裏面
に残しておいてもよい。重量軽減の観点からは第2の接
着剤24も剥離することが望ましい。
After the semiconductor element 27 is mounted on the mounting board 28 as described above, the second adhesive 24 is subjected to a process of reducing the adhesive force, and as shown in FIG. The adhesive 24 and the second support plate 25 are separated from the semiconductor element 27. At this time, only the second support plate 25 may be peeled off and the second adhesive 24 may be left on the back surface of the semiconductor element 27. From the viewpoint of weight reduction, it is desirable that the second adhesive 24 is also peeled off.

【0052】次に、図4(e)に示すように実装基板2
8を実装部28a毎に分割し、従来周知の封止構造によ
り半導体素子27を封止することによって、半導体素子
27の厚みが100μm以下の薄膜半導体装置を製造す
ることができる。
Next, as shown in FIG.
8 is divided for each mounting portion 28a, and the semiconductor element 27 is sealed by a conventionally known sealing structure, whereby a thin film semiconductor device having a thickness of the semiconductor element 27 of 100 μm or less can be manufactured.

【0053】したがって、この実施の形態による製造方
法によれば、半導体基板21に薄膜化処理を実施する工
程から実装工程までの間の全ての工程において、半導体
基板21および半導体素子27を第1の支持板23ある
いは第2の支持板25が補強するから、製造工程の途中
で薄膜状の半導体基板21や半導体素子27が割れたり
欠けたりすることはない。また、第1の支持板23や第
2の支持板25を剥離するときに半導体基板21あるい
は半導体素子27に無理な力が加わることはない。
Therefore, according to the manufacturing method of this embodiment, the semiconductor substrate 21 and the semiconductor element 27 are connected to the first substrate in all the steps from the step of performing the thinning process on the semiconductor substrate 21 to the mounting step. Since the support plate 23 or the second support plate 25 reinforces, the semiconductor substrate 21 or the semiconductor element 27 in the form of a thin film does not break or chip during the manufacturing process. Further, when the first support plate 23 or the second support plate 25 is peeled, no excessive force is applied to the semiconductor substrate 21 or the semiconductor element 27.

【0054】したがって、半導体基板21の厚みを10
0μm以下にしても歩留りがよく、しかも、薄膜状の半
導体基板21や半導体素子27の代わりに第1の支持板
23や第2の支持板25を把持して取扱うことができる
ので作業性もよい。また、全ての半導体素子27を一つ
の第2の支持板25によって保持させた状態で実装基板
28に実装することができるから、分割した半導体素子
を一つずつ実装基板に実装する場合に較べて実装作業の
作業時間を短縮することができる。
Therefore, the thickness of the semiconductor substrate 21 is set to 10
Even if the thickness is 0 μm or less, the yield is good, and the workability is also good because the first support plate 23 and the second support plate 25 can be gripped and handled instead of the thin-film semiconductor substrate 21 and the semiconductor element 27. . Further, since all the semiconductor elements 27 can be mounted on the mounting board 28 while being held by one second support plate 25, compared with the case where the divided semiconductor elements are mounted on the mounting board one by one. The working time of the mounting work can be reduced.

【0055】[0055]

【実施例】本発明の製造方法を実施するために用いる接
着剤、すなわち接着後に接着力を低下させることが可能
な接着剤としては、合成樹脂からなる基材に、接着後に
接着力を低下させることが可能な物質を添加したものが
ある。基材は、アクリル系樹脂、ポリエステル系樹脂、
エポキシ系樹脂、ウレタン系樹脂、ポリチオール系樹
脂、ポリイミド系樹脂など、どのような合成樹脂でもよ
い。
The adhesive used to carry out the production method of the present invention, that is, the adhesive capable of lowering the adhesive strength after bonding, reduces the adhesive strength after bonding to a substrate made of synthetic resin. Some substances have been added. The base material is acrylic resin, polyester resin,
Any synthetic resin such as an epoxy resin, a urethane resin, a polythiol resin, and a polyimide resin may be used.

【0056】加熱されることによって接着力が低下する
接着剤は、熱膨張係数が大きい物質をマイクロカプセル
に詰め、このマイクロカプセルを前記基材の中に均一に
添加した接着剤、いわゆる熱発泡型接着剤を使用した。
紫外線が照射されることによって接着力が低下する接着
剤は、光重合剤を前記基材に添加してなる紫外線照射硬
化型接着剤を使用した。
An adhesive whose adhesive strength is reduced by heating is an adhesive obtained by packing a substance having a large coefficient of thermal expansion in a microcapsule and uniformly adding the microcapsule to the base material, that is, a so-called thermal foaming type. An adhesive was used.
As the adhesive whose adhesive strength is reduced by being irradiated with ultraviolet rays, an ultraviolet irradiation-curable adhesive obtained by adding a photopolymerizing agent to the substrate was used.

【0057】水に触れることにより接着力が低下する接
着剤は、ポリイミド系樹脂からなる接着剤を使用した。
ポリイミド系樹脂は、それ自体の吸湿性から水に触れる
ことによって接着力が低下する。
As an adhesive whose adhesive strength is reduced by contact with water, an adhesive made of a polyimide resin is used.
The adhesive strength of the polyimide resin is reduced by contact with water due to its own hygroscopicity.

【0058】[0058]

【発明の効果】以上説明したように本発明によれば、半
導体基板の薄膜化処理を実施するときから半導体素子を
実装基板に実装するまでの間の全ての工程において、半
導体基板および半導体素子を第1の支持板あるいは第2
の支持板が補強するから、製造工程の途中で薄膜状の半
導体基板や半導体素子が割れたり欠けたりすることはな
い。しかも、第1の支持板や第2の支持板を剥離すると
きに半導体基板あるいは半導体素子に無理な力が加わる
ことはない。
As described above, according to the present invention, the semiconductor substrate and the semiconductor element are removed in all steps from the time when the semiconductor substrate is thinned to the time when the semiconductor element is mounted on the mounting substrate. The first support plate or the second
Since the support plate is reinforced, the thin-film semiconductor substrate or semiconductor element does not crack or chip during the manufacturing process. In addition, no excessive force is applied to the semiconductor substrate or the semiconductor element when the first support plate or the second support plate is peeled off.

【0059】したがって、半導体基板の厚みを100μ
m以下にしても歩留りがよく、しかも、薄膜状の半導体
基板や半導体素子の代わりに第1の支持板や第2の支持
板を把持して取扱うことができるので作業性もよい。
Therefore, the thickness of the semiconductor substrate is set to 100 μm.
Even if it is less than m, the yield is good, and the workability is also good because the first support plate and the second support plate can be gripped and handled instead of the thin film semiconductor substrate or semiconductor element.

【0060】半導体基板を分割してから第2の接着剤を
低下させる以前に半導体素子を実装基板に実装する他の
発明によれば、第2の支持板を把持しながら実装作業を
実施することができるから、半導体素子が薄膜状でも実
装作業の作業性がよく、しかも、実装作業中に半導体素
子が割れることもない。
According to another invention in which the semiconductor element is mounted on the mounting substrate before the second adhesive is lowered after the semiconductor substrate is divided, the mounting operation is performed while holding the second support plate. Accordingly, the workability of the mounting operation is good even when the semiconductor element is in the form of a thin film, and the semiconductor element is not broken during the mounting operation.

【0061】半導体基板の回路形成面に凹溝を形成して
第1の支持板を接着し、薄膜化処理を実施した後に裏面
に第2の支持板を接着する他の発明によれば、半導体基
板の薄膜化処理工程から実装工程に至る全ての工程にお
いて、半導体基板および半導体素子を第1の支持板ある
いは第2の支持板が補強するから、製造工程の途中で薄
膜状の半導体基板や半導体素子が割れたり欠けたりする
ことはない。しかも、第1の支持板や第2の支持板を剥
離するときに半導体基板あるいは半導体素子に無理な力
が加わることはない。
According to another invention, a concave groove is formed on a circuit forming surface of a semiconductor substrate, a first support plate is bonded, and after a thinning process is performed, a second support plate is bonded on the back surface. In all processes from the substrate thinning process to the mounting process, the semiconductor substrate and the semiconductor element are reinforced by the first support plate or the second support plate. The element does not crack or chip. In addition, no excessive force is applied to the semiconductor substrate or the semiconductor element when the first support plate or the second support plate is peeled off.

【0062】したがって、半導体基板の厚みを100μ
m以下にしても歩留りがよく、しかも、薄膜状の半導体
基板や半導体素子の代わりに第1の支持板や第2の支持
板を把持して取扱うことができるので作業性もよい。ま
た、全ての半導体素子を一つの第2の支持板によって保
持させた状態で実装基板に実装することができるから、
分割した半導体素子を一つずつ実装基板に実装する場合
に較べて実装作業の作業時間を短縮することができ、コ
ストを低減することができる。
Therefore, the thickness of the semiconductor substrate is set to 100 μm.
Even if it is less than m, the yield is good, and the workability is also good because the first support plate and the second support plate can be gripped and handled instead of the thin film semiconductor substrate or semiconductor element. Also, since all the semiconductor elements can be mounted on the mounting board while being held by one second support plate,
The operation time of the mounting operation can be reduced as compared with the case where the divided semiconductor elements are mounted on the mounting substrate one by one, and the cost can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明に係る薄膜半導体装置の製造方法を説
明するための断面図である。
FIG. 1 is a cross-sectional view for explaining a method for manufacturing a thin-film semiconductor device according to the present invention.

【図2】 本発明に係る薄膜半導体装置の製造方法を説
明するための断面図である。
FIG. 2 is a cross-sectional view illustrating a method for manufacturing a thin-film semiconductor device according to the present invention.

【図3】 他の発明に係る薄膜半導体装置の製造方法を
説明するための断面図である。
FIG. 3 is a cross-sectional view for explaining a method for manufacturing a thin-film semiconductor device according to another invention.

【図4】 他の発明に係る薄膜半導体装置の製造方法を
説明するための断面図である。
FIG. 4 is a cross-sectional view for explaining a method of manufacturing a thin-film semiconductor device according to another invention.

【図5】 従来の半導体装置の断面図である。FIG. 5 is a cross-sectional view of a conventional semiconductor device.

【図6】 従来の半導体装置の製造方法を説明するため
の断面図である。
FIG. 6 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device.

【図7】 フリップチップ構造を示す断面図である。FIG. 7 is a sectional view showing a flip chip structure.

【符号の説明】[Explanation of symbols]

21…半導体基板、22…第1の接着剤、23…第1の
支持板、24…第2の接着剤、25…第2の支持板、2
6…ダイシング用テープ、27…半導体素子、28…実
装基板、29…バンプ、31…凹溝。
Reference Signs List 21 semiconductor substrate, 22 first adhesive, 23 first support plate, 24 second adhesive, 25 second support plate, 2
6: dicing tape, 27: semiconductor element, 28: mounting board, 29: bump, 31: concave groove.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 大藤 晋一 東京都新宿区西新宿三丁目19番2号 日本 電信電話株式会社内 (72)発明者 小川 重男 東京都新宿区西新宿三丁目19番2号 日本 電信電話株式会社内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shinichi Ohto 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Within Japan Telegraph and Telephone Corporation (72) Inventor Shigeo Ogawa 3-192-1, Nishi-Shinjuku, Shinjuku-ku, Tokyo No. Japan Telegraph and Telephone Corporation

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 薄膜状に形成した半導体素子を実装基板
に実装する薄膜半導体装置の製造方法において、半導体
基板を半導体素子毎に分割する以前であって回路を形成
した後に、接着後に接着力を低下させることが可能な第
1の接着剤を介して第1の支持板を前記半導体基板の回
路形成面に接着し、この半導体基板に裏面側から薄膜化
処理を施した後、接着後に接着力を低下させることが可
能な第2の接着剤を介して前記裏面に第2の支持板を接
着し、次に、前記第1の接着剤の接着力を低下させてこ
の第1の接着剤および前記第1の支持板を半導体基板か
ら剥離し、次いで、前記第2の支持板の裏面にダイシン
グ用テープを貼着して半導体基板を第2の支持板と共に
分割することによって半導体素子を形成し、しかる後、
第2の接着剤の接着力を低下させて前記半導体素子から
第2の支持板を剥離することを特徴とする薄膜半導体装
置の製造方法。
In a method of manufacturing a thin film semiconductor device in which a semiconductor element formed in a thin film shape is mounted on a mounting substrate, before the semiconductor substrate is divided for each semiconductor element and after a circuit is formed, an adhesive force after bonding is reduced. A first support plate is adhered to a circuit forming surface of the semiconductor substrate via a first adhesive that can be reduced, the semiconductor substrate is subjected to a thinning treatment from the back surface side, and the adhesive force after the adhesion is applied. A second support plate is adhered to the back surface via a second adhesive capable of reducing the adhesive strength, and then the adhesive strength of the first adhesive is reduced to reduce the first adhesive and The first support plate is peeled from the semiconductor substrate, and then a dicing tape is attached to the back surface of the second support plate to divide the semiconductor substrate together with the second support plate to form a semiconductor element. After a while
A method for manufacturing a thin-film semiconductor device, comprising: separating a second support plate from the semiconductor element by lowering an adhesive force of a second adhesive.
【請求項2】 請求項1記載の薄膜半導体装置の製造方
法において、半導体基板を第2の支持板と共に分割して
半導体素子を形成した後、第2の接着剤の接着力を低下
させる以前に、バンプを介して半導体素子を実装基板に
実装することを特徴とする薄膜半導体装置の製造方法。
2. The method of manufacturing a thin film semiconductor device according to claim 1, wherein the semiconductor substrate is divided together with the second support plate to form a semiconductor element, and before the adhesive strength of the second adhesive is reduced. A method of manufacturing a thin film semiconductor device, comprising: mounting a semiconductor element on a mounting substrate via a bump.
【請求項3】 薄膜状に形成した半導体素子を実装基板
に実装する薄膜半導体装置の製造方法において、半導体
基板を半導体素子毎に分割する以前であって回路を形成
した後に、この半導体基板の回路形成面に半導体素子を
囲むように凹溝を格子状に形成し、前記回路形成面に、
接着後に接着力を低下させることが可能な第1の接着剤
を介して第1の支持板を接着し、半導体基板に裏面側か
ら薄膜化処理を前記凹溝が露出するまで実施することに
よって個々に分割された半導体素子を形成し、次いで、
接着後に接着力を低下させることが可能な第2の接着剤
を介して前記半導体素子の裏面に第2の支持板を接着
し、しかる後、前記第1の接着剤の接着力を低下させて
この第1の接着剤および前記第1の支持板を半導体素子
から剥離して半導体素子の回路形成面を露出させ、バン
プを介して前記半導体素子を実装基板に実装し、第2の
接着剤の接着力を低下させて前記半導体素子から第2の
支持板を剥離することを特徴とする薄膜半導体装置の製
造方法。
3. A method of manufacturing a thin-film semiconductor device in which a semiconductor element formed in a thin-film form is mounted on a mounting substrate, wherein a circuit is formed before the semiconductor substrate is divided into semiconductor elements and after a circuit is formed. On the formation surface, concave grooves are formed in a lattice shape so as to surround the semiconductor element, and on the circuit formation surface,
The first support plate is bonded via a first adhesive capable of reducing the bonding force after bonding, and the thinning process is performed on the semiconductor substrate from the back surface side until the groove is exposed. To form a divided semiconductor device, and then
A second support plate is bonded to the back surface of the semiconductor element via a second adhesive capable of reducing the adhesive force after the bonding, and thereafter, the adhesive force of the first adhesive is reduced. The first adhesive and the first support plate are peeled off from the semiconductor element to expose a circuit forming surface of the semiconductor element, and the semiconductor element is mounted on a mounting substrate via bumps, and the second adhesive is A method for manufacturing a thin-film semiconductor device, comprising: separating a second support plate from the semiconductor element by reducing an adhesive force.
【請求項4】 請求項1または請求項2記載の薄膜半導
体装置の製造方法において、加熱処理を施すことによっ
て接着力が低下する接着剤を使用することを特徴とする
薄膜半導体装置の製造方法。
4. The method for manufacturing a thin film semiconductor device according to claim 1, wherein an adhesive whose adhesive strength is reduced by performing a heat treatment is used.
【請求項5】 請求項1または請求項2記載の薄膜半導
体装置の製造方法において、紫外線が照射されることに
よって接着力が低下する接着剤を使用することを特徴と
する薄膜半導体装置の製造方法。
5. The method for manufacturing a thin film semiconductor device according to claim 1, wherein an adhesive whose adhesive strength is reduced by being irradiated with ultraviolet rays is used. .
【請求項6】 請求項1または請求項2記載の薄膜半導
体装置の製造方法において、水に触れることによって接
着力が低下する接着剤を使用することを特徴とする薄膜
半導体装置の製造方法。
6. The method for manufacturing a thin film semiconductor device according to claim 1, wherein an adhesive whose adhesive strength is reduced by contact with water is used.
【請求項7】 請求項1または請求項2記載の薄膜半導
体装置の製造方法において、第1の接着剤と第2の接着
剤は、接着力を低下させる手法が互いに異なるものを使
用することを特徴とする薄膜半導体装置の製造方法。
7. The method for manufacturing a thin film semiconductor device according to claim 1, wherein the first adhesive and the second adhesive are different from each other in a method of reducing an adhesive force. A method for manufacturing a thin film semiconductor device.
JP9233799A 1997-08-29 1997-08-29 Manufacture of thin-film semiconductor device Pending JPH1174230A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9233799A JPH1174230A (en) 1997-08-29 1997-08-29 Manufacture of thin-film semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9233799A JPH1174230A (en) 1997-08-29 1997-08-29 Manufacture of thin-film semiconductor device

Publications (1)

Publication Number Publication Date
JPH1174230A true JPH1174230A (en) 1999-03-16

Family

ID=16960768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9233799A Pending JPH1174230A (en) 1997-08-29 1997-08-29 Manufacture of thin-film semiconductor device

Country Status (1)

Country Link
JP (1) JPH1174230A (en)

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