JPH117422A - Memory mounted fast communication interface board and data transmitting and receiving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the facility costs of a communication path and to shorten response time from a server by resigning received data when the class to which the received data belong is different from a class corresponding to memory a part itself manages. SOLUTION: N memory managing parts 351 to 35n manage memory 301 to 30n respectively, that is, a memory managing part 351 manages the memory 301 , the managing part 352 manages the memory 302 and a memory managing part 35n manages the memory 30n . The parts 351 to 35n respectively discriminate classes to which sending data that are received from an internal bus interface controlling part 145 belong and to which receiving data that are received from an communication interface controlling part 120 belong, accumulate receiving data whose class is the same in the memory the parts 351 to 35n themselves manage when a class to which the discriminated receiving data belongs coincides with the class to which the memory they themselves manage, and resign the receiving data when the classes do not coincide.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of transmitting and receiving data in a distributed server system, and more particularly, to a distributed multimedia server connected by a high-speed communication path, which has a long and continuous data such as video and audio. The present invention relates to a memory-equipped communication interface board that transfers data between servers while mixing data having characteristics and control messages required for communication control between servers, which are relatively small in size.

More specifically, the present invention relates to a high-speed communication interface board for performing high-speed data input / output between an internal bus of a server and a communication path between the servers. Large data and control messages (transfer stop request, new data read request, error notification, etc.) for interactive communication between the user terminal and the server, and a buffer memory for each class. Is provided, when transmission / reception is performed in a form in which the video stream and the control message are mixed, the control message can be preferentially processed without waiting for the completion of the processing of the previously transmitted (or received) video stream. Even in the case where a single high-speed communication path is used for cost reduction, And the speed of the data transfer between the communication interface board, a communication interface board that can achieve both shortening response time to requests originating from a user terminal.

[0003]

2. Description of the Related Art A video-on-demand system as an example of a distributed server system will be described.

FIG. 7 is a block diagram showing a conventional video-on-demand system VODS1.

[0005] Video on demand system VODS1
Is composed of five servers SV1 to SV5 and a high-speed communication path C connecting these five servers SV1 to SV5 to each other.

The communication path C is, for example, a Fiber Ch
Annell (ANSI X3T11 standard). Server SV1
SV5 is, for example, a PC / AT compatible personal computer,
Each has a hard disk device for storing video streams. In the video-on-demand system VODS1, a VOD (Video-on-demand) terminal 6 is connected to the server SV1. The VOD terminal 6
For example, a PC / AT compatible personal computer, FDDI (Fi
The server SV1 is connected to the server SV1 by a ber Distributed Data Interface or the like, and issues a read request for a desired video program to the server 1. The server SV1 includes a memory for temporarily storing a video stream to be transferred to the VOD terminal 6.

[0007] The video stream is segmented for each data size corresponding to a unit reproduction time, and is divided into five servers SV1.
~ SV5, and is accumulated while striping (separated and accumulated sequentially). For example, when the server SV1 receives a request to transfer a predetermined video stream from the VOD terminal 6, the server SV1 converts each segment data to obtain a plurality of segment data constituting the requested predetermined video stream. Servers SV2 to SV2 are transferred to server SV1.
Requests are sequentially issued to 5.

[0008] In the order in which the video streams are striped, and in accordance with the video playback timing,
A request for transferring segment data is issued to a predetermined server. The server SV1 temporarily stores the segment data received from the servers SV2 to SV5 in an internal memory, and transfers the segment data to the VOD terminal 6 according to a predetermined bit rate of the video stream. It should be noted that the video data being reproduced by the VOD terminal 6 is not interrupted so that the segment data that is preceding the current segment data (the segment data being transferred to the VOD terminal 6) is transferred. A request is issued in advance.

The VOD terminal 6 stops the video program, pauses, and changes the playback point in the program (jump).
And the like, and in order to realize this, a control message such as a stop of reading of segment data or a reading of a new segment is sent between the servers.

A plurality of VOD terminals 6 can be connected to each of the servers SV1 to SV5.
In each of the plurality of connected VOD terminals, reproduction of the video stream and visual search can be executed independently of each other.

FIG. 8 is a block diagram of a conventional communication interface board CIB.

Conventional communication interface board CIB
Is a communication interface 10 which is an input / output connector unit for a high-speed communication path C, and a communication interface control unit 2 which controls transmission and reception of data to and from the communication interface 10
0, a transmission queue 31 in which predetermined transmission data is queued in the order of arrival, a memory 30 for storing a reception queue 31 in which predetermined reception data is queued in the order of arrival, and a host CPU (Central Processing Unit) 50. And an internal bus interface 40 that configures a data transfer path, and an internal bus interface control unit 45 that controls transmission and reception of data to and from the internal bus interface 40.

The communication interface control unit 20 assembles a header of transmission data and creates a frame in a transfer format on the communication channel C.
1 and a reception sequence manager 22 for decomposing a header from a received frame and extracting received data.

Next, the conventional communication interface board C
The operation of the IB will be described.

First, the communication interface board CIB
Will be described.

First, the internal bus interface control unit 45
Is connected to the host CP via the internal bus interface 40.
The data is received from U50, and the transmission queue 3 of the memory 30 is received.
Queue to the end of 1. As the queue length of the transmission queue 31 increases, the communication interface control unit 20 sends the transmission data to be transmitted to the communication path C to the memory 30.
Recognize that it exists. The transmission sequence manager 21 in the communication interface control unit 20 transmits the transmission data queued in the transmission queue 31 to the FI.
In order to extract the data in the order according to the FO (First In First Out) rule and to transfer the data to the communication path C, the transmission data is divided for each unit length and converted into a frame to which header information is added. Furthermore, the transmission data converted into this frame is
The data is sent out to the communication channel C via the communication interface 10.

Next, the data receiving operation in the communication interface board CIB will be described.

First, the reception sequence manager 22 in the communication interface control unit 20 deletes header information from one or more frames received via the communication interface 10, synthesizes received data, and combines the received data. The data is queued at the end of the reception queue 32 of the memory 30. Further, the presence of new received data in the memory 30 is determined by means such as an interrupt.
Notify to host CPU50. When the host CPU 50 knows that there is new data reception, it instructs the internal bus interface control unit 45 to read out new reception data. The internal bus interface control unit 45 converts the reception data queued in the reception queue 32 into
The data is taken out in the order according to the FIFO rules and transferred to the host CPU 50 via the internal bus interface 40.

[0019]

In a video-on-demand system or the like, while transferring large-size data having continuity like a video stream, the data is divided to quickly transfer small-size data. It may be necessary to send and receive. For example, when it is necessary to notify an interactive control message such as stop, pause, and jump for a video stream being transferred, or when a plurality of VOD terminals are accessing at the same time, an access request from another user is sent. In the case of notification, it is necessary to transmit and receive small data quickly even while transferring large data.

Conventionally, in this type of data transfer between servers, in order to promptly notify a control message in parallel with the transfer of a video stream, a configuration having a data bus and a control bus independently is considered. Have been. However, this has the disadvantage that the cost of the communication path is doubled. Furthermore, when the server platform is an inexpensive commercial PC, the communication interface module cannot be configured in parallel due to the limitation of the size of the communication interface board, or the number of expansion slots of the internal bus is limited. If a plurality of communication interface boards cannot be mounted due to restrictions, it is difficult to duplicate the communication path.

Therefore, a configuration is conceivable in which the servers are connected by a single high-speed communication path. In this case, the difference between the data transfer rate on the high-speed communication path and the data transfer rate on the internal bus of the server is considered. In order to absorb the data, a double buffer is formed on the interface board, and data is input / output while sequentially switching between a side accessed from a communication path and a side accessed from an internal bus. In this case, for example, if a control interface is received after receiving two video streams successively on a certain communication interface board, each of the two video streams arriving earlier than the control message is stored in the double buffer by one. The control message is stored in each of the buffers following the storing operation. That is, the control message cannot be processed unless the reception process is completed for at least one of the video streams. To process the control message, the reception process for one video stream is waited. There is a need. That is, in the above conventional example, there is a problem that it is not possible to respond quickly to a request from the user terminal.

According to the present invention, when data to be transmitted in a large transfer unit in bursts and data to be frequently transmitted in small transfer units are mixedly transferred, the equipment cost of a communication path can be reduced. It is another object of the present invention to provide a memory-mounted high-speed communication interface board capable of shortening a response time from a server and a method of transmitting and receiving data.

[0023]

According to the present invention, transmission data and reception data are classified into n types (n is an integer of 1 or more) into classes, and n memories for storing transmission data and reception data are provided. And one of the memories is made to correspond to one of the classified classes.
After instructing buffering for all memories,
By identifying the class of data and determining whether or not to store it for each memory and storing it, or by identifying the class when data is received,
By selecting a memory to be buffered, transmission data or reception data is independently buffered for each of the n types of classes.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing a communication interface board CIB1 according to one embodiment of the present invention.

The communication interface board CIB1 is a communication interface board for performing high-speed data input / output between a high-speed communication path C connecting a plurality of servers and an internal bus of the server.
When a communication interface control unit 120, n pieces of the memory 30 ₁ to 30 _n (first memory 30 _1, the second memory 3
0 _2, ..., a memory 30 _n) of the n, n pieces of the memory management unit 35 ₁ to 35 _n (first memory management unit 35 _1, a second
, The memory management units 35 ₂ ,...,.
_n ), an internal bus interface 140, and an internal bus interface control unit 145.

The communication interface control section 120 controls transmission and reception of data to and from the communication channel C, and has a transmission sequence manager 121 and a reception sequence manager 122.

The first memory 30 ₁ comprises a first transmission queue 31 _1, the first receive queue 32 ₁ and has a second memory 30 _2, and the second transmission queue 31, _second has two of the receive queue 32 _2, ..., the memory 30 _n of the n-th,
It has an n-th transmission queue 31 _n and an n-th reception queue 32 _n .

Each of the memories 30 ₁ to 30 _n corresponds to a class different from each other.
It corresponds to the n-th class. That is, the memory 30 ₁
Is corresponding to the first class, the memory 30 ₂ is corresponding to the second memory, ..., the memory 30 _n are corresponding to the class of the n.

When transmitting the first class of transmission data, the memory 30 ₁ stores the first class of transmission data in the first transmission queue 31 ₁ in the order of arrival, and when the first class of reception data is received, They are stored in the reception queue 32 ₁ in the order of their arrival. Memory 30 _2, when transmitting transmission data of the second class, in the order of arrival, the second accumulated in the transmission queue _312, if the received data of the second class is received, the reception on the order of arrival queue 32 ₂ to accumulate. Similarly,
When transmitting the n-th class of transmission data, the memory 30 _n stores the data in the n-th transmission queue 31 _n in the order of arrival, and when the n-th class of reception data is received, stores the reception queue in the order of arrival. 32 _n .

The internal bus interface control unit 145 includes:
Is for controlling the transmission and reception of data to the internal bus, the data received via the internal bus interface 140, those passing into n memory management unit 35 ₁ to 35 _n.

[0031] n memory management unit 35 ₁ to 35 _n, respectively manages the memory 30 ₁ to 30 _n, that is, the memory management unit 35 ₁ manages memory 30 _1, the memory management unit 35 _2, manage memory 30 _2, ..., the memory management unit 35 _n is configured to manage the memory 30 _n. Then, each of the n memory management units 35 _{1 to} 35 _n
The class to which the transmission data received from the internal bus interface control unit 145 or the reception data received from the communication interface control unit 120 belongs is determined, and the class to which the determined reception data belongs is the class to which the memory managed by itself belongs. If they match, the received data having the same class is stored in a memory managed by itself, and if the classes do not match, the received data is discarded.

The communication interface control unit 120 has a first
The transmission sequence manager 121 and the reception sequence manager 122 recognize that new transmission data exists by increasing the queue length of each of the transmission queues 31 ₁ to 31 _n.
And

The transmission sequence manager 121 in the communication interface control unit 120 controls each transmission queue 31 _1.
FIFO transmit data that has been queued to ~31 _n
(First In First Out) The processing is performed in the order according to the rules. That is, according to the order of accumulation in each of the transmission queues 31 _{1 to} 31 _n , the transmission data is divided into a predetermined unit transfer length, transmission header information is attached, and a frame is created. The transmission data thus converted into one or more frames is transmitted via the communication interface 110 to the communication path C.
Sent out to

The reception sequence manager 122 in the communication interface control 120 includes the communication interface 1
The header information is removed from one or more frames received via the interface 10, the data corresponding to the original data is combined, the reception data is assembled, and the reception data is further divided into n memory management units 35 ₁ To 35 _n .

[0035] Each of the memory management unit 35 ₁ to 35 _n that accumulates data received from the channel C, by means of an interrupt or the like, received in one memory of the memory 30 ₁ to 30 _n by itself managed data Is notified to the host CPU 150.

Here, the "class" is a set of data of the same type. For example, a large-sized multimedia data and a small-sized control message for inter-server communication are used. Depending on the size of the data, the data may be divided into classes, and a stream having continuity such as video and audio and data having no continuity such as text and still images may be used.
The data may be classified according to the presence or absence of continuity, or the data may be classified into three, namely, these and control messages for communication between servers. The classification of this data is arbitrary.

As the memories 30 ₁ to 30 _n , for a class for storing long data such as a video stream, for example, a highly integrated large capacity DRAM (Dynamic Random A
ccess Memory), and a class that accumulates small data such as control messages has a high-speed SRAM (Stat
ic Random Access Memory).

FIG. 2 shows a communication interface board CIB.
3 is a flowchart illustrating a transmission operation in the first embodiment.

First, when transmitting data, the host CP
U150 writes information for identifying the class to which the transmission data belongs in the header of the transmission data, and transfers the data to communication interface board CIB1 via the internal bus (T1). The internal bus interface control unit 145 includes:
The transmission data received via the internal bus interface 140, and transfers to all of the memory management unit 35 ₁ to 35 _n. That is, the data is transferred to the first memory management unit 35 ₁ , the second memory management unit 35 ₂ ,..., The n-th memory management unit 35 _n (T2).

[0040] For example, when the transmission data to be transmitted at that time is data belonging to the first class, the first memory management unit 35 _1, looking at the header portion of the transmitted data, belonging to the first class Recognize that it is data (T3
_1), the first transmission queue 31 in the first memory 30 _1
1 of the last queuing (T5 _1). In parallel with this, the second memory management unit 35 ₂ looks at the header part of the transmission data and recognizes that the data does not belong to the second class (T3 ₂ ), and therefore discards the data (T32). T4 _2). If the transmitted data belongs to the first class,
Other memory management unit 35 _3, ..., even in 35 _n, as in the process in the second memory management unit 35 ₂ discards the data.

If the transmission data belongs to a class other than the first class, the first memory management unit 35 ₁
Watches header portion of the transmitted data, recognizes that not data belonging to the first class (T3 _1), discards the transmission data (T4 _1). If the transmission data belongs to the second class, the second memory management unit 35 _2, looking at the header portion of the transmitted data, recognizes that the data belonging to the second class (T3 _2), second to second queuing at the end of the transmission queue 31 ₂ in the memory 30 ₂ (T
52 ₂ ).

_If the length of the transmission queues 31 _{1 to} 31 _n is increased, the transmission sequence manager 121 recognizes that new transmission data exists in the memories 30 _{1 to} 31 _n (T6). In accordance with the order of the transmission queue (one of the transmission queues 31 _{1 to} 31 _n ), the transmission data is taken out, the transmission data is framed (T 7), and transmitted to the communication path C via the communication interface 110.

FIG. 3 shows a communication interface board CIB.
3 is a flowchart illustrating a receiving operation in the first embodiment.

The reception sequence manager 122 decomposes header information from some frames received via the communication interface 110, and assembles reception data (R1). The communication interface control unit 120 transmits the received data to all the memory management units (the first memory management unit 3).
5 _1, the second memory management unit 35 _2, ..., and transfers the n memo portion managing unit 35 _n) to the (R2).

For example, if the received data is data belonging to the first class, the first memory management unit 35 ₁
Looking at the header part of the received data, it recognizes that the received data belongs to the first class (R3 ₁ ),
Queuing the first end of the receive queue 32 ₁ in the first memory 30 ₁ (R5 _1). In parallel with this, the second memory management unit 35 _2, looking at the header portion of the received data, recognizes that the received data is not data belonging to the second class (R3 _2), the received data discard the (R4 _2). Other memory management units 35 ₃ ,..., 3
Even 5 _n, to perform a second memory management unit 35 ₂ and the same processing.

[0046] Then, the first memory management unit 35 _1, by the means of interruption or the like, that new received data in the first memory 30 ₁ is present, informs the host CPU 150 (R6). Internal bus interface control unit 145
Are in the order queued in the first reception queue 32 ₁ according to an instruction from the host CPU 150.
Read the received data (R7).

Further, if the received data is data belonging to the second class, the second memory management unit 35 _2, looking at the header portion of the received data, the data that the received data belongs to the second class recognizes that there (R3 _2), second
Queues into a second end of the receive queue 32 ₂ in the memory 30 ₂ (R5 _2).

In parallel with this, the first memory management unit 35
₁ sees the header part of the received data, recognizes that the received data does not belong to the first class, and discards the received data (R4 ₁ ). Other memory management unit 35 _3, ... even 35 _n, the first of the memory management unit 35
The same processing as the above processing in ₁ is executed.

FIG. 4 is a block diagram showing a communication interface board CIB2 according to another embodiment of the present invention.

The communication interface board CIB2 is a communication interface board for performing high-speed data input / output between a high-speed communication path C connecting a plurality of servers and an internal bus of the server.
, A communication interface control unit 220, a communication path side memory switching unit 270, and n memories 40 ₁ ,..., 40 _n
(First memory 40 ₁ , second memory 40 ₂ ,..., N-th memory 40 _n ) and internal bus side memory switching section 260
, An internal bus interface 240, and an internal bus interface control unit 245.

The communication interface control unit 220 controls transmission and reception of data to and from a communication channel, and includes a transmission sequence manager 321 and a reception sequence manager 322.

Each of the memories 40 ₁ to 40 _n corresponds to a class different from each other.
It corresponds to the n-th class. That is, the memory 40 ₁
Corresponds to the first class, the memory 40 _2, corresponds to the second class, ..., the memory 40 _n corresponds to the class of the n.

[0053] Then, the memory 40 _1, when the transmission data belonging to the first class is transmitted, the order of arrival, and stored in the first transmission queue 41 _1, the received data is received belonging to the first class If, it accumulates in the receiving queue 42 ₁ to the order of arrival. Memory 40 _2, when the transmission data belonging to the second class is transmitted, the order of arrival, the second
And accumulation in the transmission queue 41 _2, if the received data belonging to the second class is received, the receive queue 4 in order of arrival
2 ₂ to accumulate. Similarly, when transmission data belonging to the n-th class is transmitted, the memory 40 _n accumulates the data in the n-th transmission queue 41 _n in the order of arrival, and receives the reception data belonging to the n-th class. In this case, the packets are accumulated in the reception queue 42 _n in the order of arrival.

The internal bus side memory switching section 260 identifies the class from the header information of the transmission data received from the internal bus interface 240, and transfers the transmission data only to the memory corresponding to the class.

The communication interface control section 220 knows that new transmission data exists by increasing the transmission queue length. Then, the communication sequence manager 221 in the communication interface control unit 220
The first transmission queue 41 ₁ , the second transmission queue 41 ₂ ,...
.., The transmission data entered in the n-th transmission queue 41 _n is processed in an order according to a FIFO (First In First Out) rule. That is, according to the order of accumulation in each transmission queue, the transmission data is divided into predetermined unit transfer lengths, transmission header information is attached, and a frame is created. The transmission data thus converted into one or more frames is sent out to the communication path C via the communication interface 210.

The reception sequence manager 222 in the communication interface control unit 220 removes the header information from one or more frames received via the communication interface 210, and combines the data constituting the original data. , And assembles the received data, and passes the received data to the communication path side memory switching unit 270.

The communication path side memory switching unit 270 identifies the class based on the header information of the received data, and transfers the received data only to the memory corresponding to the class. After that, the host CPU 250
Is notified that new received data exists.

Next, the communication interface board CIB2
Will be described.

FIG. 5 shows a communication interface board CIB.
6 is a flowchart showing a transmission processing operation in the second embodiment.

First, when transmitting data, the host CP
U250 writes information for identifying the class to which the transmission data belongs to in the header portion of the transmission data, and transfers the transmission data to internal bus interface board CIB2 via the internal bus (T11).

The internal bus interface control unit 245
The transmission data received via the internal bus interface 240 is passed to the internal bus side memory switching unit 260, and the internal bus side memory switching unit 260 identifies a class based on the header information of the transmission data (T12). For example,
When the transmission data belongs to the first class, the internal bus side memory switching unit 260 transfers the transmission data to the first memory 40 _1.
Is queued at the end of the first transmission queue 41 ₁ (T13 ₁ ). The increase in the queue length of the first transmission queue 41 ₁ causes the communication interface control 22
0 parts, in the first memory 40 _1, recognizes that the new transmission data exists (T14).

Then, the communication interface control section 220
Of the transmission data queued in the first transmission queue 41 ₁
Processing is performed in the order according to the O (First In First Out) rule.
That is, in accordance with the order of accumulation in the first transmission queue 41 ₁ , predetermined transmission data is transmitted to the communication path side memory switching unit 27.
0, the transmission data is divided into predetermined unit transfer lengths, transmission header information is attached, and a frame is created (T15). The transmission data thus converted into one or more frames is sent out to the communication path C via the communication interface 210 (T16).

[0063] When the transmission data belongs to the second class, the internal bus side memory switching section 260 queues the send data to the second end of the transmission queue 41 ₂ of the second memory 40 in ₂ ( T13 ₂ ). Due to the increase in the number of entries in the second transmission queue 41 ₂ , the second
Of the memory 40 _2, and the transmission data to be transmitted is generated, a communication interface control unit 220 recognizes (T
14). Subsequent processing is the same as the processing when the transmission data belongs to the first class.

FIG. 6 shows a communication interface board CIB.
6 is a flowchart illustrating a reception processing operation in the second embodiment.

First, the reception sequence manager 222 in the communication interface control unit 220 removes transmission header information from one or more frames received via the communication interface 210, and removes the transmission header information from the one or more frames. The data is combined to assemble the received data (R11). Further, the received data is passed to the communication path side memory switching unit 270. The communication path side memory switching unit 270 determines the class to which the received data belongs (S12), and transfers the data only to the memory corresponding to the determined class (R
13 ₁ ~R13 _n). For example, if the received data belongs to the first class, the first end of the receive queue 42 ₁ of the first memory 40 _1, and queues the received data (R13 _1).

The communication path side memory switching unit 270 stores new received data in the first memory 40 by means such as an interrupt.
₁ is notified to the host CPU 250 (R1
4). The internal bus-side interface control unit 245 responds to an instruction from the host CPU 250 to
21. The received data is fetched through the internal bus side memory switching unit 260 in the order queued in ₁
Send to PU250 (R15).

[0067] Also, if the received data belongs to the second class, the second receive queue 42 in the second memory 40 _{2 2}
Finally, the received data is queued (R13
₂ ). Communication roadside memory switching unit 270 by means such as an interrupt, that a new received data are stored in the second memory 40 _2, and notifies the host CPU 250 (R14). Subsequent processing is the same as the above processing when the received data belongs to the first class.

In the above-described embodiment, between a communication path connecting a plurality of servers and an internal bus of the server, long and continuous stream data such as video and audio,
If you want to transfer a relatively small size, such as control messages required for communication control between servers,
Transmission and reception data are classified into n types (n is an integer of 1 or more), and n memories for storing predetermined transmission data and predetermined reception data are provided for each class. After instructing buffering for all the memories, in each memory, by identifying the class of the data, it is determined whether or not to store the data, and then the data is stored. By identifying the class, the memory to be buffered is selected.

Therefore, in the above embodiment, since the data to be transmitted or received is buffered independently for each of the n types of classes, it is necessary to wait until the processing of the previously transmitted (or received) stream data is completed. Without
The control message and the like can be preferentially processed,
The response time to the request issued from the user terminal can be reduced. Therefore, even when a single communication path is used to reduce costs, the speed of data transfer between the communication interface boards is increased, and the response time to a request issued from a user terminal is reduced. And can be compatible.

[0070]

According to the present invention, different types of data are transmitted, for example, when data transmitted in a large transfer unit in bursts and data frequently transmitted in small transfer units are mixed and transferred. Independent buffering has the effect of reducing the equipment cost of the communication path, and has the effect of shortening the response time from the server.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a communication interface board CIB1 according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an operation at the time of transmission in the communication interface board CIB1.

FIG. 3 is a flowchart showing an operation of the communication interface board CIB1 at the time of reception.

FIG. 4 is a block diagram showing a communication interface board CIB2 according to another embodiment of the present invention.

FIG. 5 is a flowchart showing a transmission processing operation in the communication interface board CIB2.

FIG. 6 is a flowchart illustrating a reception processing operation in the communication interface board CIB2.

FIG. 7 shows a conventional video-on-demand system VODS1.
FIG.

FIG. 8 is a block diagram of a conventional communication interface board CIB.

[Explanation of symbols]

CIB1, CIB2 communication interface board, 110, 210 communication interface, 120, 220 communication interface control unit, 121, 221 transmission sequence manager, 122, 222 reception sequence manager, 140, 240 internal bus interface, 145 245 ... internal bus interface controller, 150, 250 ... CPU, 260 ... internal bus side memory switching unit, 270 ... communication roadside memory switching _{section, 30 1 ~30 n, 40 1} ~40 n ... memory, 31 ₁ to 31 _n , 41 _{1 to} 41 _n ... Transmission queue, 32 _{1 to} 32 _n , 42 _{1 to} 42 _n ... Reception queue, 35 _{1 to} 35 _n .

Claims (4)

[Claims] A communication interface board for performing high-speed data input / output between a communication path connecting a plurality of servers and an internal bus of the server, wherein predetermined transmission data and predetermined reception data are stored. N memories classified into n types (n is an integer of 1 or more); n memory management units for managing data input / output to / from each of the n memories; Passing the data received through all of the n memory management units, and a communication interface control unit that controls transmission and reception of data between the memory management unit and the communication path; Passing the received data to all of the n memory management units, and controlling the transmission and reception of data between the memory management unit and the internal bus; and an internal bus interface control unit. Each of the memory management unit, and classes that data it has received belongs,
If the class corresponding to the memory managed by the user is the same, the received data is stored in the memory managed by the user, while the class to which the data received belongs belongs to the memory managed by the user. A high-speed communication interface board with a memory, wherein the received data is discarded when the class is different. 2. A communication interface board for performing high-speed data input / output between a communication path connecting a plurality of servers and an internal bus of the server, wherein predetermined transmission data and predetermined reception data are stored. And n memories classified into n types (n is an integer of 1 or more); a communication interface control unit for controlling transmission and reception of data between the n memories and the communication path; A data input / output destination is switched between the n memories and the communication interface control unit, a class to which the data received from the communication path belongs is determined, and the communication corresponding to the determined class is stored in the memory corresponding to the determined class. A communication roadside memory switching unit for storing data received from the roadside;
An internal bus interface control unit for controlling transmission and reception of data between the n memories and the internal bus; between the n memories and the internal bus interface control unit,
An internal bus side memory for switching a data input / output destination, determining a class to which the data received from the internal bus side belongs, and storing the data received from the internal bus side in the memory corresponding to the determined class; A switching unit;
A high-speed communication interface board with a built-in memory, characterized by having: 3. A communication interface board for performing high-speed data input / output between a communication path connecting a plurality of servers and an internal bus of the server, wherein n communication interfaces provided on the interface board are provided. Associating each of the memories with n types (where n is an integer of 1 or more) of classes, and passing data received via the internal bus to all of the n memories; receiving via the communication path Passing the data to all of the n memories; identifying a class to which the transmission data or the reception data belongs; and a class associated with each of the n memories. Storing the identified data in the memory if the class of the data matches the class of the data; and a class associated with each of the n memories; If a separate been data class does not match, the identification data comprising: the memory is discarded; method for transmitting and receiving data, comprising a. 4. A communication interface board for performing high-speed data input / output between a communication path connecting a plurality of servers and an internal bus of the server, wherein n communication interfaces provided on the interface board are provided. Associating each of the memories with n (n is an integer of 1 or more) classes, and identifying the data received via the internal bus into n classes; and receiving the data via the internal bus Storing data only in a memory corresponding to the class to which the received data belongs; identifying data received through the communication path into n classes; and receiving data through the communication path Storing only in the memory corresponding to the class to which the received data belongs.