JPH1173299A - Buffer memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the loss of data, and to attain the control of overflow and empty by dividing a buffer memory into memory areas of certain data units, and operating data transfer by each data unit. SOLUTION: A buffer memory 1 is divided into memory areas of each certain data unit, and the empty of the buffer memory 1 is detected by a data discriminating circuit 29 by using flag signals 22, 23, and 24 for operating write and read control by each data unit, and data transfer is operated by each data unit by operating read control. Thus, the loss of data can be prevented, and also the control of overflow can be attained by the flag signals 22, 23, and 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer memory control device for temporarily storing data in a buffer memory and then performing data transfer.

[0002]

2. Description of the Related Art Generally, a buffer memory is provided between two communication systems having different data transfer speeds to adjust the data transfer speed. For example, a buffer memory of a data transfer source is written. This is used when the speed is faster than the speed of reading data from the buffer memory at the destination of the data transfer.

FIG. 8 is a block diagram showing a configuration of a conventional buffer memory control device which temporarily stores data in a buffer memory and then performs data transfer. In FIG. 8, reference numeral 1 denotes a buffer memory (8-bit data input / output) having a capacity of 3 cells (1 cell = 53 bytes, 1 byte = 8 bits).
Output, 8-bit read / write address input, read /
A write address input circuit for generating a write address of the buffer memory 1;
Is a write address generated by the write address generation circuit 2, 4 is write data to be written to the buffer memory 1, 5 is a write enable that enables the buffer memory 1 to be written, and 6 is a read that generates a read address of the buffer memory 1. An address generation circuit 7 for a read address generated by the read address generation circuit 6;
8 is read data read from the buffer memory 1,
9 is a read enable to enable reading of the buffer memory 1, and 149 is a write address 3 of the buffer memory 1.
And an address comparison circuit for comparing the read address 7 with a read address 7. This address comparison circuit takes two's complement by using two adders and performs subtraction. Reference numeral 150 denotes a subtraction result obtained by subtracting the read address 7 from the write address 3 by the address comparison circuit 149, and 151 detects that an overflow has occurred in the buffer memory 1 when the subtraction result 150 changes from -1 to 0. An overflow occurrence notifying circuit 152 is an empty occurrence notifying circuit for detecting that an empty has occurred in the buffer memory 1 when the subtraction result 150 changes from +1 to 0. 10 (a), 10 (b), and 10 (c) show the configurations of the address comparison circuit, the overflow occurrence notification circuit, and the empty occurrence notification circuit of FIG. 8, respectively.
0 (a), EX ₀₁ , EX ₀₂ , EX ₁₁ , EX ₁₂ ,
, EX _n1 and EX _n2 are exclusive OR circuits, AD ₀₁ and AD
_{02, AD 11, AD 12,} ..., AD n1, AD n2 is an AND _{circuit, OR 01, OR 11, ...} , OR n1 is an OR circuit.
A ₀ , A ₁ ,..., _An are the bits of the write address,
B ₀ , B ₁ ,..., B _n are each bit of the read address, S ₀ , S
_1, ..., each bit of the S _n is the subtraction result, C _0, C _1, ..., C _n is the bit carry.

In FIG. 10 (b), 51a is a decoder for decoding that the subtraction result of the address comparison circuit is 0, and 51b is a decoder for subtracting -1 from the address comparison circuit.
51c is a flag register that is set when the decoder 51b detects -1, 51d is a decoder 51a and a flag register 51d.
This is an AND circuit for notifying the occurrence of an overflow when both outputs of c become H.

In FIG. 10 (c), 52a is a decoder for decoding that the subtraction result of the address comparator is 0, and 52b is a decoder for subtracting +1 from the address comparator.
52c is a flag register set when the decoder 52b detects +1. 52d is a decoder 52a and a flag register 52.
This is an AND circuit for notifying the occurrence of an overflow when both outputs of c become H.

The operation of the buffer memory control device configured as described above will be described below. FIG.
As shown in (1), when the write enable 5 is at the LOW level (hereinafter referred to as L level), the buffer memory 1 writes the write data 4 to the write address 3 output from the write address generation circuit 2 in synchronization with the write clock. I do. The write address generation circuit 2 has a write enable 5
0 to 158 in synchronization with the write clock when
Are sequentially output from 0, and this is repeated. On the other hand, when the read enable 9 is at the L level, the buffer memory 1 reads the read data 8 from the read address 7 output by the read address generation circuit 6 in synchronization with the read clock. When the read enable 9 is at the L level, the read address generation circuit 6 outputs addresses 0 to 158 in order from 0 in synchronization with the read clock, and repeats this.

In this buffer memory control device, in order to detect the occurrence of overflow in the buffer memory 1, the address comparison circuit 149 subtracts the read address 7 from the write address 3 and the subtraction result 150
To the overflow occurrence notifying circuit 151 and the empty occurrence notifying circuit 152. The result of the subtraction takes a positive value in the normal operation because the write address takes a larger value than the read address, but when an overflow occurs, as shown in FIG.
This is a case where the AD overtakes the read address RAD to reach the highest address of the memory area, and once returns to the lowest address of the memory area, the address increases from there to the read address RAD. The circuit 151 detects an overflow when the subtraction result 150 changes from -1 to 0. On the other hand, when an empty occurs, the read address RAD catches up with the write address WAD as shown in FIG.
Numeral 52 detects the empty state when the value changes from plus 1 to 0, and stops reading.

In the buffer memory control device according to the prior art, when the transfer of write data is interrupted while data in units of cells, which is a set of data in units of data, is written to the buffer memory, In order to read the written data, even in the middle of the cell, pseudo data is inserted into the subsequent data and data transfer is performed, but the receiving side discards the cell unit containing the pseudo data and discards it. Therefore, a loss occurs in the transmitted cell data.

The overflow or empty state of the buffer memory is detected by using an address comparison circuit as shown in FIG. 10A. When the address comparison circuit subtracts the read address B from the write address A, A + Since the subtraction circuit executes (2's complement of B) +1, the circuit scale increases as the number of address bits increases. Further, in addition to this subtraction circuit, two decoders, a flag register, and an AND circuit as shown in FIG. 10 (b) are required one by one, and it is assumed that the subtraction result becomes 0 after -1. An overflow occurrence notifying circuit for detecting an overflow by detection, two decoders, a flag register, and an AND circuit as shown in FIG. 10C are required one by one. It is also necessary to provide an empty generation notifying circuit for detecting the empty state by detecting the occurrence of the empty state.

Further, after an overflow of the buffer memory occurs, it is necessary to retransmit the write data until the transfer is stopped in order to notify the stop of the transfer of the write data. However, there is a problem that data loss occurs due to overwriting to the data. Incidentally, a cell buffer control circuit disclosed in Japanese Patent Application Laid-Open No. 8-223168 has already been developed as a device capable of solving such a problem, and is reproduced in FIG. FIG. 11 shows the configuration of the cell buffer control circuit disclosed in Japanese Patent Application Laid-Open No. 8-223168. In FIG. 11, a decoder 105 with an enable for decoding a write-side bank address 101 and a read-side bank address 103 are shown. Decoder 106 with an enable for decoding the data, information holding means 1091 to 109n for holding information indicating whether or not there is cell data in each bank corresponding to each bank; An addition circuit 112 for adding 1, and information holding means 1091 to 109 based on the value of the addition circuit 112
selector 1 for selecting outputs 1101 to 110n from n
14, an addition circuit 113 for adding 1 to the value of the read-side bank address 103, and outputs 1101 to 11 from the information holding means 1091 to 109n according to the value of the addition circuit.
0n and an abnormal state detecting means 116 for detecting an abnormal state of the cell buffer.

The cell buffer control circuit shown in FIG. 11 is constructed by dividing the entire cell buffer (not shown) into n banks, and has a write-side or read-side address corresponding to each bank, and information corresponding to the number of banks. Holding means 10
When the decoder 105 detects the end of the writing of the cell data to each bank using the write-side bank address 101 and the bank write end signal 102, the data is written to the information holding means corresponding to the corresponding bank. The end is input, thereby setting a flag indicating the presence of cell data. Also, the decoder 106 uses the read-side bank address 103 and the bank read end signal 104 to release the flag held in the information holding means corresponding to the bank at the end of reading cells from each bank. By doing so, each information holding means can indicate whether the cell data is written and exists in the corresponding bank, or read and indicates whether the cell data does not exist.

The selector 114 uses the value obtained by adding 1 to the write-side bank address 101 by the adding circuit 112 as a control signal for the selector 114, and the selector 114
Since the outputs 1101 to 110n of 1 to 109n are selected, the selector 114 selects an information holding unit corresponding to a bank one bank ahead of the bank to which writing is currently performed. Therefore, the output signal 11 of the selector 114
When 7 is H, the cell buffer has overflowed, and this signal can be used as a write inhibit signal for the cell buffer.

Further, a value obtained by adding 1 to the read-side bank address 103 by the adding circuit 113 is supplied to the selector 115.
Selector 115 is the information holding means 10
Since the outputs 1101 to 110n of 91 to 109n are selected, the selector 115 selects the information holding unit corresponding to the bank one bank ahead of the bank from which the current reading is to be performed. Therefore, the output signal 11 of the selector 115
When 7 is L, it means that the cell buffer is empty, so that an inverted signal of this signal can be used as a read inhibition signal from the cell buffer.

[0014]

However, this conventional cell buffer control circuit controls overflow and underflow by checking the information of the next information holding means of the bank currently being written. Yes,
For this reason, the bank that is currently writing immediately outputs an inspection result indicating that overflow or underflow has occurred at the time of starting writing to the bank.
For this reason, as the number of banks becomes smaller, the capacity of the cell buffer cannot be effectively used, and overflow and underflow detection results are output. For example, when the number of banks is two, the total number of banks in the cell buffer is reduced. Only half of the capacity can be utilized. Therefore, when data transfer control is performed using the overflow / underflow detection result output from the cell buffer control circuit,
There was a problem that transfer efficiency was not good. In addition, there is a problem that this conventional cell buffer control circuit can cope only with a fixed-length bank area.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. When used for data transfer control, the transfer efficiency is high and the overflow of the buffer memory is detected without increasing the circuit scale. It is an object of the present invention to provide a buffer memory control device capable of detecting an overflow of a buffer memory in advance or transmitting the overflow to a partner.

[0016]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems and attain the object, and a buffer memory control device according to the invention of claim 1 of the present application comprises a plurality of data units by an address. A buffer memory divided into a memory area of a cell unit, a write address generating circuit for outputting a write address of the buffer memory, a read address generating circuit for outputting a read address of the buffer memory, and decoding the write address To output a flag signal indicating a write address before the end of data writing for each cell unit.
A data discriminating circuit for discriminating the presence / absence of data in cell units in the buffer memory based on the flag signal, and performing read control of the buffer memory; and reading data in cell units by decoding the read address. A second register that indicates the end, outputs a flag reset signal for resetting the flag signal, and an overflow occurrence notifying circuit that notifies the occurrence of an overflow in the buffer memory by the flag signal. Buffer memory read control is performed, write data transfer stop is notified before the buffer memory overflows, and data is transferred in units of cells to prevent data loss. Divided into cell units and data for each cell unit Feeding was carried out, the loss of cell data can be prevented by controlling the overflow and empty. Further, since the overflow of the buffer memory is detected without using the comparison circuit, the circuit scale can be reduced.

According to a second aspect of the present invention, there is provided the buffer memory control device according to the first aspect of the present invention, wherein a flag signal is input and the buffer memory has no data in a unit of cell in the buffer memory. A pseudo data generation circuit that outputs a pseudo data selection signal and pseudo data in units of cells at the same time as performing read control of the data, and a selection circuit that selects one of the pseudo data and the read data of the buffer memory based on the pseudo data selection signal Since there is no problem that the entire cell is discarded at the transfer destination,
Cell data loss can be prevented.

According to a third aspect of the present invention, there is provided a buffer memory control device according to the first aspect, wherein a register capable of setting an address value from the outside, and a register value and a write address which are externally set. It has a first match detection circuit for detecting a match and a second match detection circuit for detecting a match between the register value and the read address so that the memory area of the buffer memory can be divided into arbitrary units. Therefore, an overflow in the memory area of the buffer memory divided into arbitrary units can be detected.

A buffer memory control device according to a fourth aspect of the present invention outputs a buffer memory divided into a plurality of memory areas in units of cells, which are a plurality of data units, and a write address of the buffer memory. A write address generation circuit, a read address generation circuit that outputs a read address of the buffer memory,
A first register that outputs a flag signal indicating a write address at or before the writing of data in each cell unit by decoding the write address, and a cell unit in the buffer memory according to the flag signal. A data discriminating circuit for discriminating the presence / absence of data and performing a read control of the buffer memory; and a flag reset signal for indicating the end of reading of data for each cell unit by decoding the read address and resetting the flag signal. A second register to be output, and an overflow occurrence detection circuit that receives a flag signal and a write address, and notifies a stop of write data transfer before an overflow occurs due to the flag signal and the write address; Read the buffer memory by the circuit The buffer memory is divided into a certain cell unit because the transfer of write data is notified before the buffer memory overflow occurs, and the data transfer is performed in cell units to prevent data loss. However, by performing data transfer on a cell-by-cell basis and controlling overflow and empty, loss of cell data can be prevented. Further, the overflow of the buffer memory can be detected in advance.

According to a fifth aspect of the present invention, there is provided the buffer memory control device according to the fourth aspect of the present invention, wherein a flag signal is input, and when there is no cell unit data in the buffer memory, A pseudo data generation circuit that outputs a pseudo data selection signal and pseudo data in units of cells at the same time as performing read control of the data, and a selection circuit that selects one of the pseudo data and the read data of the buffer memory based on the pseudo data selection signal Since there is no problem that the entire cell is discarded at the transfer destination,
Cell data loss can be prevented.

According to a sixth aspect of the present invention, in the buffer memory control device according to the fourth aspect of the present invention, there is provided a buffer memory control device, comprising: a register capable of setting an address value from the outside; It has a first match detection circuit for detecting a match and a second match detection circuit for detecting a match between the register value and the read address so that the memory area of the buffer memory can be divided into arbitrary units. Therefore, an overflow in the memory area of the buffer memory divided into arbitrary units can be detected.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. (Embodiment 1) In Embodiment 1, a write address and a read address of a buffer memory are decoded by a decoder to set or reset a plurality of flag registers corresponding to a cell, and an AND of outputs of these flag registers is set. Thus, the overflow of the buffer memory can be detected with a small circuit scale.

FIG. 1 is a block diagram showing a configuration of the buffer memory control device according to the first embodiment of the present invention. In FIG. 1, 1 indicates three cells (1 cell = 53 bytes, 1
A buffer memory (8-bit data input / output, 8-bit read / write address input, read / write enable input) having a capacity equivalent to a byte (8 bits), which may be constituted by one memory. , A plurality of memories.

Reference numeral 2 denotes a write address generation circuit for generating a write address of the buffer memory 1, 3 denotes a write address generated by the write address generation circuit 2, 4 denotes write data to be written to the buffer memory 1, and 5
Is a write enable for setting the buffer memory 1 to a writable state, 6 is a read address generation circuit for generating a read address of the buffer memory 1, 7 is a read address generated by the read address generation circuit 6, and 8 is a read address. Read data 9 read from the buffer memory 1 is a read enable for setting the buffer memory 1 in a readable state, and these are the same as those in FIG. 6 of the conventional example.

Next, reference numerals 10 to 12 decode the write addresses generated by the write address generation circuit 2, and these are decoded into memory areas 1a to 1 of the buffer memory 1 in units of cells.
a write address decoder for detecting whether or not the address matches the highest address of c; 13 to 15 are flag registers set by the write address decoders 10 to 12;
Reference numerals 18 to 18 decode the read address generated by the read address generation circuit 6 and detect whether or not the read address matches the highest address of the memory areas 1a to 1c of the buffer memory 1. A flag reset register, which is set by the address decoders 16 to 18 and indicates that the corresponding memory area 1a to 1c is empty when set, is output from the flag register 13 to 15 and corresponds to an H level. A flag signal indicating that the memory areas 1a to 1c are full and resetting the flag reset register when the level is low is output from the flag reset registers 19 to 21. When the level is high, the corresponding memory area 1a is output. 1c is empty, and the flag register 13 Flag reset signal for resetting the 5, 28 consists of three input AND circuit, a flag signal 22
An overflow occurrence notifying circuit for notifying that an overflow has occurred in the buffer memory 1 when all of the signals H to H become H. At least one of the flag signals 22 to 24 is provided.
This is a data discrimination circuit that discriminates that one has become H and generates a read enable 9 at that time, and can be constituted by an exclusive OR circuit.

FIG. 2 is a circuit diagram showing an example of the configuration of the decoder of FIG. 1. Here, the case of decoding 52, 105, and 158 is shown as an example. In FIG. 2A, 10 ₁ is the data “1” and the fifth address of the write address 3.
A logical product circuit for calculating the logical product of bit 3 ₅ , 10 ₂ is a logical product circuit for calculating the logical product of data “1” and the fourth bit 3 ₄ of write address 3, and 10 ₃ is a logical product circuit for calculating data “0” and write address 3 AND circuit for calculating the logical product of the third bit 3 ₃ , 10
₄ is data “1” and second bit 3 ₂ of write address 3
AND circuit taking the logical product, logical product circuit ₁₀₅ takes the first bit 3 ₁ logical product of the write address 3 and data "0", 10 ₆ 0th write address 3 and data "0"
AND circuit which takes the logical product of the bit 3 _0, 10 ₇ is a logical product circuit for taking a logical product of the AND circuit 10 ₁ to 10 _6.

When the data inputted to the write address 3 coincides with 52, this decoder circuit expands the data into binary numbers "1", "1", "0", "1", "0",
"0" is the fifth bit 3 ₅ of the AND circuit 10 ₁ to 10 ₆ write address 3, the fourth bit 3 _4, the third bit 3
_3, the second bit 3 _2, the first bit 3 _1, zeroth bit 3 ₀
Is input, this AND circuit 10 ₁ to 10 ₆ data "1" is given in advance to "1", "0",
Since "1", "0", and "0" all match, the outputs of the AND circuits 10 ₁ to 10 ₆ all become H, whereby the output of the AND circuit 10 ₇ becomes H, and the write address 3 It can be detected that the input data matches 52.

FIG. 2 (b) shows a configuration similar to that of FIG. 2 (a).
2 is a decoder that can detect that the data input to the write address 3 matches 105.
(b), the logical product circuit 11 ₁ takes the logical product of the sixth bit 3 ₆ of the write address 3 and data "1", 11 ₂
AND circuit which is a logic product circuit for taking a logical product of the fifth bit 3 ₅ of the write address 3 and data "1", 11 ₃ ANDing the fourth bit 3 ₄ of the write address 3 and data "0", 11 logical product _{circuits 4} ANDing the third bit 3 ₃ of the write address 3 and data "1", 11 ₅ logical to take the second bit 3 ₂ logical product of the write address 3 and data "0" circuit, the logical product circuit 11 ₆ takes the first bit 3 ₁ logical product of the write address 3 and data "0", 11
₇ is the data “1” and the 0th bit 3 ₀ of the write address 3
A logical product circuit for calculating a logical product of the logical product circuit 11 ₈ is a logical product circuit 11 ₁
To a logical product circuit for taking a logical product of 11 _7.

FIG. 2 (c) shows a configuration similar to that of FIG.
FIG. 2 is a decoder that can detect that the data input to the write address 3 matches 158.
In (c), 12 ₁ is AND circuit which takes the logical product of the seventh bit 3 ₇ of the write address 3 and data "1", 12 ₂
AND circuit, 12 ₃ AND circuit taking the logical product of the fifth bit 3 ₅ of the write address 3 and data "0" which is the logical product of the sixth bit 3 ₆ of the write address 3 and data "0", 12 ₄ aND circuit taking the logical product of the fourth bit 3 ₄ of the write address 3 and data "1", 12 ₅ logical ANDing of the third bit 3 ₃ of the write address 3 and data "1" circuit, 12 an aND circuit _{which 6} takes the second bit 3 ₂ logical product of the write address 3 and data "1", 12
₇ is data “1” and first bit 3 ₁ of write address 3
AND circuit taking the logical product, 12 ₈ The data "0" the AND circuit taking the logical product of the zeroth bit 3 ₀ of the write address 3, 12 ₉ a logical product of the AND circuit 12 ₁ to 12 ₈ This is a logical product circuit.

The operation of the buffer memory control device configured as described above will be described below. As shown in FIG. 1, when the write enable 5 is at the L level, the buffer memory 1 writes the write data 4 to the write address 3 output from the write address generation circuit 2 in synchronization with a write clock (not shown). In the write address generation circuit 2, when the write enable 5
At the level, addresses 0 to 158 are sequentially output from 0 in synchronization with the write clock, and this is repeated.

Write address decoders 10, 11, 12
Decodes the write address 3, which is the value 52, 105 indicating the highest address of one cell of the buffer memory 1,
When each of the values matches 158, an H level signal is output. Therefore, the write address decoders 10, 11, 12
When the data of one cell is written in the buffer memory 1, that is, when the address indicated by the write address 3 starts writing from 0, and the writing to the addresses 52, 105, and 158 is completed, the decoding starts. The corresponding H level signals are respectively stored in the corresponding flag registers 13, 1
Output to 4 and 15. Then, the flag registers 13, 1
4 and 15 set the respective flag signals 22, 23 and 24 to H
Level.

On the other hand, when the read enable 9 is at the L level, the buffer memory 1 reads the read data 8 from the read address 7 output from the read address generation circuit 6 in synchronization with a read clock (not shown). When the read enable 9 is at the L level, the read address generation circuit 6 sets addresses 0 to 158 to 0 in synchronization with the read clock.
And then repeat this.

Read address decoders 16, 17, 18
Decodes the read address 7, which is the value 52, 105, 1 indicating the highest address of one cell of the buffer memory 1.
When they match with each other, an H level signal is output.
Therefore, the read address decoders 16, 17, 18
When one cell of data is read from the buffer memory 1, that is, when the address indicated by the read address 7 is 0
, The decoded H-level signals are stored in the corresponding flag reset registers 1 only after the reading up to the addresses 52, 105, and 158 is completed.
Output to 9, 20, 21.

Then, the flag reset registers 19, 2
0 and 21 are the corresponding flag registers 13 and 1 respectively.
Flag reset signal 2 for resetting 4 and 15
5, 26 and 27 are set to the H level. The flag reset registers 19, 20, and 21 output the flag reset signals 25, 26, and 27 at the H level until the corresponding flag registers 13, 14, and 15 are reset, and reset the flag registers 13, 14, and 15 after resetting the flag registers 13, 14, and 15, respectively. Level.

If the flag signals 22, 23, 24 output from the flag registers 13, 14, 15 are at H level, the corresponding memory areas 1a, 1 of the buffer memory 1
Since data writing to b and 1c has been completed, the data discriminating circuit 29 outputs the read enable 9 only when at least one of the flag signals 22, 23 and 24 is at the H level.

Thus, the flag signals 22, 23, 24
Data determination circuit 29 only when at least one of
Thus, data in the buffer memory 1 can be read, so that data can be transferred in units of cells. For this reason, if the data in the buffer memory 1 is interrupted during the transfer of a cell, the entire cell is discarded at the transfer destination in order to form a cell by inserting pseudo data after the interrupted data at the transfer source. The cell data can be prevented from being lost.

If the flag signals 22, 23, and 24 are all at the H level, the data writing to the corresponding memory areas 1a, 1b, and 1c of the buffer memory 1 has been completed. The overflow of the buffer memory 1 can be detected by using a three-input logical product.

Therefore, for example, when the present buffer memory control device is applied to an ATM, the write address decoder 1
The values to be decoded by 0, 11, and 12 are
When the buffer memory control device is constituted by a synchronous circuit as shown in FIG. 1, that is, 47, 100, and 153, which are smaller by 5, respectively, the value is smaller than 5, 158. When the buffer memory control device is configured, overflow of the buffer memory 1 can be detected in advance by setting the buffer memory controller to 48, 101, or 154, which is smaller by 4 than the aforementioned 52, 105, or 158.

As described above, according to the first embodiment, the write address input to the buffer memory is decoded in units of cells, the flag register is set, and the read address input to the buffer memory is decoded in units of cells. The flag reset register is set, the flag register is reset by the output of the flag reset register, and the overflow of the flag register is detected when the output of the flag register becomes H level corresponding to all cells in the buffer memory. As a result, when used for data transfer control, transfer efficiency is high, and a circuit can be configured by an address decoder, a register, and an AND circuit. Changes from -1 to 0 or from +1 to 0
The circuit size can be made smaller than that of detecting the change in the data, and the presence or absence of data in the buffer memory can be detected in units of cells. Furthermore, by setting the address to be decoded by the write address decoder to an address before the highest address of the cell, it is possible to detect an overflow before this actually occurs.

(Embodiment 2) In Embodiment 2, a write address and a read address of a buffer memory are decoded by a decoder, and a plurality of flag registers corresponding to a memory area are set or reset. All outputs become H except one,
The decoder detects that the write address of the memory area corresponding to the remaining one flag register is about to overflow, so that the overflow of the buffer memory can be detected in advance before this actually occurs.

FIG. 3 is a block diagram showing a configuration of the buffer memory control device according to the second embodiment of the present invention. 3, a buffer memory 1, a write address generator 2, a write address 3, write data 4, a write enable 5, a read address generator 6, a read address 7, a read data 8, a read enable 9, and write address decoders 10 to 12 are shown. , Flag registers 13 to 15,
The configurations of the read address decoders 16 to 18, the flag reset registers 19 to 21, the flag signals 22 to 24, the flag reset signals 25 to 27, and the data discrimination circuit 29 are substantially the same as those of the first embodiment shown in FIG. Is the same as Reference numeral 30 denotes a decoder similar to that shown in FIG. 2, in which the flag signals 22 to 24 become H level except one during writing, and the write address of the memory area corresponding to one of the flag signals 22 to 24 is set in the memory area. When decoding that a predetermined address close to the highest address is reached,
An overflow occurrence detection circuit for notifying in advance that an overflow has occurred in the buffer memory 1.

The operation of the buffer memory control device configured as described above will be described below. FIG.
When the write enable 5 is at the L level, the buffer memory 1 writes the write data 4 to the write address 3 output from the write address generation circuit 2 in synchronization with a write clock (not shown). When the write enable 5 is at the L level, the write address generation circuit 2 outputs addresses 0 to 158 in order from 0 in synchronization with the write clock, and repeats this.

Write address decoders 10, 11, 12
Decodes the write address 3, which is the value 52, 105, 1 indicating the highest address of one cell of the buffer memory.
When they match with each other, an H level signal is output.
Therefore, the write address decoders 10, 11, and 12 start writing when the data of one cell is written in the buffer memory 1, that is, when the address indicated by the write address 3 starts from 0, and write the addresses 52, 105, and 158. Only after the writing to the corresponding flag registers 13, 14, 1
Output to 5 Then, the flag registers 13, 14, 1
5 sets each flag signal 22, 23, 24 to H level.

On the other hand, when the read enable 9 is at the L level, the buffer memory 1 reads the read data 8 from the read address 7 output by the read address generation circuit 6 in synchronization with the read clock.

When the read enable signal 9 is at the L level, the read address generation circuit 6 sequentially starts from 0 to 158 from 0 to 158 in synchronization with a read clock (not shown) from the read address 7 generated by the read address generation circuit 6. Output and repeat.

Read address decoders 16, 17, 18
Decodes the read address 7, which is the value 52, 105, 1 indicating the highest address of one cell of the buffer memory 1.
When they match with each other, an H level signal is output.
Therefore, the read address decoders 16, 17, 18
When the data of one cell is read from the buffer memory 1, that is, when the address indicated by the read address starts reading from 0 and the reading up to the addresses 52, 105, and 158 is completed, the decoded H level Flag reset register 1 corresponding to each signal
Output to 9, 20, 21.

Then, the flag reset registers 19, 2
0 and 21 are the corresponding flag registers 13 and 1 respectively.
Flag reset signal 2 for resetting 4 and 15
5, 26 and 27 are set to the H level. The flag reset registers 19, 20, and 21 output the flag reset signals 25, 26, and 27 at the H level until the corresponding flag registers 13, 14, and 15 are reset, and reset the flag registers 13, 14, and 15 after resetting the flag registers 13, 14, and 15, respectively. Level. Only when at least one of the flag signals 22, 23, 24 is at the H level, the data discriminating circuit 29
Is output.

As described above, the flag signals 22, 23, 24
Data determination circuit 29 only when at least one of
By making the data of the buffer memory 1 readable, data transfer on a cell basis becomes possible. For this reason, if the data in the buffer memory 1 is interrupted during the transfer of a cell, the entire cell is discarded at the transfer destination in order to form a cell by inserting pseudo data after the interrupted data at the transfer source. There is no problem that it will
Cell data loss can be prevented.

Also, when any two of the flag signals 22, 23, and 24 are at the H level, the overflow address detection circuit 30 sets the highest address in the memory area to which a certain address value of the memory area currently being written corresponds. Is decoded before the buffer memory 1 overflows, it is possible to issue an overflow notification before the buffer memory 1 overflows, and the transfer of the write data can be stopped. Can be eliminated.

For this reason, for example, the flag signals 23 and 24
Is at the H level, and the write address is 47, which is five before the highest address 52 of the memory area 1a currently being written.
Is reached, the overflow occurrence detection circuit 30 composed of a decoder is connected to the circuit shown in FIG.
, The occurrence of overflow can be detected in advance, and loss of write data can be prevented.

As described above, according to the second embodiment, the write address input to the buffer memory is decoded in units of cells, the flag register is set, and the read address input to the buffer memory is decoded in units of cells. The flag reset register is set, the flag register is reset by the output of the flag reset register, and the output of the flag register becomes H level by one less than all the cells of the buffer memory, and corresponds to the remaining one cell. By decoding that the write address is a value before reaching the maximum value of the corresponding address, the overflow is detected, so the presence or absence of data in the buffer memory can be detected in units of cells. When used for data transfer control, the transfer efficiency is good, and Bafuro it is possible to advance detect.

(Third Embodiment) In a third embodiment, a write address and a read address of a buffer memory are decoded by a decoder to set or reset a plurality of flag registers corresponding to a memory area. All outputs become H except one,
In addition, the decoder detects that the write address of the memory area corresponding to the remaining one flag register is about to overflow, and if all the outputs of these flag registers are L, the pseudo data discarded at the transfer destination is deleted. By transmitting the data, the overflow of the buffer memory can be detected in advance before the overflow actually occurs, and the transmission of erroneous data can be prevented.

FIG. 4 is a block diagram showing a configuration of a buffer memory control device according to the third embodiment of the present invention. 4, a buffer memory 1, a write address generation circuit 2, a write address 3, write data 4, a write enable 5, a read address generation circuit 6, a read address 7, a read data 8, a read enable 9, a write address decoders 10 to 12 , Flag registers 13 to 15,
Read address decoders 16-18, flag reset registers 19-21, flag signals 22-24, flag reset signals 25-27, overflow occurrence detection circuit 30
Is substantially the same as the corresponding part of FIG. 3 shown in the second embodiment, and reference numeral 31 denotes flag signals 22, 23, and 24.
Read enable 9 only when at least one of them is at H level
To output data, and a pseudo data generation circuit for generating pseudo data to be discarded at the transfer destination only when all of the flag signals 22, 23, and 24 are at the H level. Pseudo data generated by the circuit 31; 34 is a selection circuit for selecting the read data 8 from the buffer memory 8 and the pseudo data 32;
Is a pseudo data selection signal for selecting the selection circuit 34,
Reference numeral 35 denotes transfer data selected by the selection circuit 34 and transferred to the transfer destination.

The operation of the buffer memory control device configured as described above will be described below. As shown in FIG. 4, when the write enable 5 is at the L level, the buffer memory 1 writes the write data 4 to the write address 3 output from the write address generation circuit 2 in synchronization with a write clock (not shown). When the write enable 5 is at the L level, the write address generation circuit 2 outputs addresses 0 to 158 in order from 0 in synchronization with the write clock, and repeats this.

Write address decoders 10, 11, 12
Decodes the write address 3, which is the value 52, 105, indicating the highest address of one cell of the buffer memory 1.
When each of the values matches 158, an H level signal is output. Therefore, the write address decoders 10, 11, 12
When the data of one cell is written to the buffer memory 1, that is, when the address indicated by the write address 3 starts writing from 0, and the writing to the addresses 52, 105, and 158 is completed, the decoding The corresponding H level signals are stored in the corresponding flag registers 13, 1
Output to 4 and 15. Then, the flag registers 13, 1
4 and 15 set the respective flag signals 22, 23 and 24 to H level.
Level.

On the other hand, when the read enable 9 is at the L level, the buffer memory 1 reads the read data 8 from the read address 7 output by the read address generation circuit 6 in synchronization with a read clock (not shown).

When the read enable 9 is at the L level, the read address generation circuit 6 sets the read address 9 to 0 in synchronization with the read clock.
158 are sequentially output from 0, and this is repeated.

Read address decoders 16, 17, 18
Decodes the read address 7, which is the value 52, 105, 1 indicating the highest address of one cell of the buffer memory 1.
When they match with each other, an H level signal is output.
Therefore, the read address decoders 16, 17, 18
When one cell of data is read from the buffer memory 1, that is, when the address indicated by the read address 7 is 0
, And the decoded H level signals are not stored in the corresponding flag reset register 1 until the read up to the addresses 52, 105, and 158 is completed.
Output to 9, 20, 21.

Then, the flag reset registers 19, 2
0, 21 are the corresponding flag registers 13, 1,
Flag reset signal 2 for resetting 4 and 15
5, 26 and 27 are set to the H level. The flag reset registers 19, 20, and 21 output the flag reset signals 25, 26, and 27 at the H level until the corresponding flag registers 13, 14, and 15 are reset, and reset the flag registers 13, 14, and 15 after resetting the flag registers 13, 14, and 15, respectively. Level. Only when one or more of the flag signals 22, 23, and 24 is at the H level, the pseudo data generation circuit 31 outputs the read enable 9 to enable data reading.

As described above, the flag signals 22, 23, 24
By reading the data in the buffer memory 1 only when at least one of them is at the H level, data transfer in cell units becomes possible. For this reason, if the data in the buffer memory 1 is interrupted during the transfer of a cell, the entire cell is discarded at the transfer destination in order to form a cell by inserting pseudo data after the interrupted data at the transfer source. The cell data can be prevented from being lost.

When all of the flag signals 22, 23 and 24 are at the L level, for example, the ATM (Asynchronous)
Transfer Mode: Asynchronous transfer mode) Pseudo data called empty cells, that is, pseudo data 32 in cell units to be discarded at the transfer destination is output by the pseudo data generation circuit 31 and a pseudo data selection signal 33 at the same time. And the selector 34 switches the transfer data 35 from the read data 8 to the pseudo data 32, thereby outputting the pseudo data 32 to the transfer destination.

After transferring the empty cell, the pseudo data generating circuit 31 again detects whether or not one or more of the flag signals 22, 23, 24 is at the H level. Read, and if all are at L level, empty cells are transferred again, and this operation is repeated. Thereby, transfer of erroneous data can be prevented.

Also, when any two of the flag signals 22, 23, and 24 are at the H level, the overflow address detection circuit 30 sets the highest address in the memory area to which a certain address value of the memory area currently being written corresponds. Is decoded before the buffer memory 1 overflows, it is possible to issue an overflow notification before the buffer memory 1 overflows, and the transfer of the write data can be stopped. Can be eliminated.

Therefore, for example, the flag signals 23 and 24
Is at the H level, and the write address is 47, which is five before the highest address 52 of the memory area 1a currently being written.
Is reached, the overflow occurrence detection circuit 30 composed of a decoder is connected to the circuit shown in FIG.
, The occurrence of overflow can be detected in advance, and loss of write data can be prevented.

As described above, according to the third embodiment, the write address input to the buffer memory is decoded in units of cells, the flag register is set, and the read address input to the buffer memory is decoded in units of cells. The flag reset register is set, the flag register is reset by the output of the flag reset register, and the output of the flag register becomes H level by one less than all the cells of the buffer memory, and corresponds to the remaining one cell. By decoding that the write address is a value before reaching the maximum value of the corresponding address, it is detected that an overflow has occurred,
When all the outputs of the flag registers are at the L level, pseudo data is transferred to the transfer destination, so that the presence or absence of data in the buffer memory can be detected in units of cells and used for data transfer control. Good transfer efficiency
It is possible to prevent erroneous data transfer and to detect an overflow in advance.

As shown in FIG. 5, the overflow occurrence notifying circuit may be constituted by an AND circuit 28 as shown in FIG. 1. In this case, the write address decoders 10, 11, and 12 are connected to each other. Memory areas 1a, 1b, 1
If the highest address of c is set to, for example, 52, 105, 158, overflow cannot be detected in advance, but the presence or absence of data in the buffer memory can be detected on a cell-by-cell basis to prevent erroneous data transfer. Is possible. Therefore, from this, for example, 4 before 5
7, 100, 153, it is possible to detect the overflow in advance, and when the output of the flag register corresponding to two of the three memory areas 1a, 1b, 1c is at the H level. Data can be read from one memory area as long as it is.

(Embodiment 4) In Embodiment 4, a plurality of addresses corresponding to a memory area are detected by detecting a match between a write address and a read address of a buffer memory and arbitrary setting data set in an address setting register. Set or reset the flag registers, and confirm that all but one of the outputs of these flag registers are H, and that the write address of the memory area corresponding to the remaining one flag register is about to overflow.
This is detected by decoding this and the setting data set in the address setting register, and when at least one of the outputs of these flag registers is at H, the buffer memory can be read out, thereby overflowing the buffer memory. Can be detected before this actually occurs, the buffer memory is divided into an arbitrary number of cells, and the presence or absence of data in the buffer memory can be detected in units of the divided cells.

FIG. 6 is a block diagram showing a configuration of the buffer memory control device according to the fourth embodiment of the present invention. 6, a buffer memory 1, a write address generator 2, a write address 3, a write data 4, a write enable 5, a read address generator 6, a read address 7, a read data 8, a read enable 9, flag registers 13 to 15, Flag reset registers 19 to 21,
Flag signals 22 to 24, flag reset signals 25 to 2
7. The configurations of the data discriminating circuit 29 and the overflow occurrence detecting circuit 30 are substantially the same as the corresponding portions in FIG. 2 shown in the second embodiment, and 36 to 38 comprise exclusive OR circuits and the like. A match detecting circuit for detecting a match between the address 3 and the address set in the address setting register. Reference numerals 39 to 41 each include an exclusive OR circuit or the like, and determine whether the read address 7 matches the address set in the address setting register. Match detection circuits for detection, 42 to 44 are address setting registers in which addresses where a match is detected by the match detection circuits 36 to 41 are set, and 45 to 47 are setting data set in the address setting registers 42 to 44,
9 to 51 are address setting registers for setting addresses set in the overflow detection circuit 30, and 48 are these address setting registers 42 to 44 and 49 to 51.
The external input data 55, which is the setting data to be set, is constituted by a CPU or the like, and is an address setting means for setting the external input data.

The operation of the buffer memory control device configured as described above will be described below. As shown in FIG. 6, the buffer memory 1 has a write enable 5
Is at the L level, the write data 4 is written to the write address 3 output from the write address generation circuit 2 in synchronization with a write clock (not shown). When the write enable 5 is at the L level, the write address generation circuit 2 outputs addresses 0 to 158 in order from 0 in synchronization with the write clock, and repeats this.

The address setting registers 42, 43 and 44 respectively store the external input data 4 from the address setting means 55.
8 and indicates the highest address of each memory area 1a, 1b, 1c. Therefore, the match detection circuits 36, 3
7, 38 are address setting registers 42, 4
The write data 3 matches the setting data 45, 46, 47 set in the memory areas 1a, 1b,
When the writing to the highest address of 1c is completed, the H level signal is set to the corresponding flag register 13, 1
Output to 4 and 15. Then, the flag registers 13, 1
4 and 15 set the respective flag signals 22, 23 and 24 to H level.
Level.

On the other hand, the buffer memory 1 reads the read data 8 from the read address 7 output from the read address generation circuit 6 when the read enable 9 is at the L level in synchronization with a read clock (not shown). When the read enable 9 is at the L level, the read address generation circuit 6 outputs addresses 0 to 158 in order from 0 in synchronization with the read clock, and repeats this.

In the address setting registers 42, 43, and 44, as described above, the highest addresses of the memory areas 1a, 1b, and 1c, for example, 40, 110, and 158 are set. , 41, the read address 7 matches the setting data 45, 46, 47 set in the corresponding address setting registers 42, 43, 44, and the read up to the highest address of the memory areas 1a, 1b, 1c is performed. When the processing is completed, the H level signals are output to the corresponding flag reset registers 19, 20, and 21, respectively.

When the flag reset registers 19, 20, and 21 are set, the flag reset signals 25, 26, and 27 are output at H level until the corresponding flag registers 13, 14, and 15 are reset. After the flag registers 13, 14, and 15 are reset, they go low.

The data discriminating circuit 29 outputs the read enable 9 only when at least one of the flag signals 22, 23, 24 is at the H level. Thus, the flag signal 2
Only when at least one of 2, 23 and 24 is at H level, the data in the buffer memory 1 is read by the data discriminating circuit 29 so that the address setting register 42 to
It is possible to transfer in arbitrary cell units set to 44,
Cell data loss can be prevented.

When any two of the flag signals 22, 23, and 24 are at the H level, the overflow occurrence detection circuit 30 sets the address value of the memory area currently being written to the highest address in the corresponding memory area. Two are at the H level, and
In order that the write address during writing matches the address setting registers 49 to 51 by the external input data 48,
The overflow occurrence detection circuit 30 comprising a decoder
Is set, and an address before the highest address of the memory areas 1a, 1b, 1c of the buffer memory 1 is set in the address setting registers 49 to 51, whereby an overflow of the buffer memory 1 can be detected in advance.

For example, when the highest addresses of the memory areas 1a, 1b, and 1c of the buffer memory 1 are 40, 110, and 158, the setting data 52 to 54 are set to 35, 106, and 153, which are five places before this. By doing so, the overflow occurrence detection circuit (decoder) 30 can detect the overflow of the buffer memory 1 in advance in an arbitrary cell unit.

As described above, according to the fourth embodiment, by detecting a match between the write address and the read address of the buffer memory and the arbitrary setting data set in the address setting register, a plurality of addresses corresponding to the memory area are detected. Set or reset the flag registers, and confirm that all but one of the outputs of these flag registers are H, and that the write address of the memory area corresponding to the remaining one flag register is about to overflow.
This is detected by decoding the setting data set in the address setting register and the setting data set in the address setting register, and when at least one of the outputs of the flag registers is at H, the buffer memory can be read. Overflow can be detected before it actually occurs, and when used for data transfer control, a transfer efficiency can be obtained.In addition, the buffer memory is divided into an arbitrary number of cells, and the divided cells are divided. Can be used to detect the presence or absence of data in the buffer memory.

As shown in FIG. 7, the overflow occurrence notifying circuit may be constituted by an AND circuit 28 as shown in FIG. 1. In this case, the address setting registers 49, 50, 51 Memory area 1a, 1b, 1c
, For example, 40, 110, 158, the overflow of the buffer memory cannot be detected in advance, but the overflow can be detected in arbitrary cells. Therefore, if the address setting registers 49, 50, and 51 are set to 35, 106, and 153, for example, 5 ahead of each other, overflow can be detected in advance, and the same as in the fourth embodiment. It works.

The buffer memory control device can further divide the memory area of the buffer memory into arbitrary units by increasing the number of flag registers, flag reset registers, coincidence detection circuits, and address setting registers. It becomes possible to transfer data and detect overflow in advance on a cell-by-cell basis. Furthermore, when the detection values of the coincidence detection circuit are all set to, for example, 158, it is possible to detect the presence or absence of overflow of the entire buffer memory without dividing the buffer memory.

[0080]

As described above, according to the buffer memory control device according to the first aspect of the present invention, a buffer memory divided into a plurality of data units, i.e., a cell-based memory area by an address; A write address generation circuit that outputs a write address of a memory; a read address generation circuit that outputs a read address of the buffer memory; and a write address before the end of data writing for each cell unit by decoding the write address. A first register for outputting a flag signal indicating the presence of the data, a data discriminating circuit for discriminating presence / absence of data in a unit of cell in the buffer memory based on the flag signal, and performing a read control of the buffer memory; Indicates the end of reading data for each cell unit, A second register for outputting a flag reset signal for resetting a lag signal; and an overflow occurrence notifying circuit for notifying the occurrence of an overflow in the buffer memory by the flag signal. The buffer memory is divided into a certain cell unit because the stop of the write data transfer is notified before the buffer memory overflow occurs, and the data transfer is performed in the cell unit to prevent the data loss. By performing data transfer on a cell-by-cell basis and controlling overflow and empty, loss of cell data can be prevented. Further, since the overflow of the buffer memory is detected without using the comparison circuit, the circuit scale can be reduced.

Further, according to the buffer memory control device of the present invention, when a flag signal is input and there is no data in cell units in the buffer memory, A pseudo data generation circuit that outputs a pseudo data selection signal and pseudo data in cell units at the same time as performing read control of the buffer memory, and selects one of the pseudo data and the read data of the buffer memory by the pseudo data selection signal. Since the selection circuit is provided, there is no problem that the entire cell is discarded at the transfer destination, and there is an effect that loss of cell data can be prevented.

According to a third aspect of the present invention, there is provided the buffer memory control device according to the first aspect, wherein a register capable of setting an address value from the outside, a value of the register, and a value of the register are written. A first match detection circuit for detecting a match between addresses; and a second match detection circuit for detecting a match between the value of the register and the read address, so that the memory area of the buffer memory can be divided into arbitrary units. Therefore, an overflow of the memory area of the buffer memory divided into arbitrary units can be detected.

According to the buffer memory control device of the present invention, the buffer memory divided into a plurality of memory areas in units of cells, which is a plurality of data units, and the write address of the buffer memory is stored in the memory area. A write address generating circuit for outputting, a read address generating circuit for outputting a read address of the buffer memory, and a write address at the time of completion of writing of data for each cell unit or a write address before this by decoding the write address. A first register for outputting a flag signal indicating the data, a data discriminating circuit for discriminating presence / absence of data in a unit of cell in the buffer memory based on the flag signal, and performing read control of the buffer memory; and decoding the read address. Completes reading data for each cell And a second register for outputting a flag reset signal for resetting the flag signal, a flag signal and a write address being input, and stopping transfer of write data before an overflow occurs due to the flag signal and the write address. An overflow occurrence detection circuit for notifying the buffer memory, performing read control of the buffer memory by the data discrimination circuit, notifying stop of write data transfer before an overflow of the buffer memory occurs, and performing data transfer in cell units. Since the data loss is prevented, the buffer memory is divided into certain cell units, data transfer is performed for each cell unit, and overflow and empty are controlled to prevent cell data loss. Also, there is an effect that the overflow of the buffer memory can be detected in advance.

According to the buffer memory control device of the present invention, when a flag signal is input and there is no data in cell units in the buffer memory, A pseudo data generation circuit that outputs a pseudo data selection signal and pseudo data in cell units at the same time as performing read control of the buffer memory, and selects one of the pseudo data and the read data of the buffer memory by the pseudo data selection signal. Since the selection circuit is provided, there is no problem that the entire cell is discarded at the transfer destination, and there is an effect that loss of cell data can be prevented.

According to the buffer memory control device of the present invention, in the buffer memory control device according to the fourth aspect, a register capable of setting an address value from the outside, and writing and reading of the register value A first match detection circuit for detecting a match between addresses; and a second match detection circuit for detecting a match between the value of the register and the read address, so that the memory area of the buffer memory can be divided into arbitrary units. Therefore, an overflow of the memory area of the buffer memory divided into arbitrary units can be detected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a buffer memory control device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a decoder of the buffer memory control device according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a buffer memory control device according to a second embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a buffer memory control device according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing another configuration example of the buffer memory control device according to the third embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of a buffer memory control device according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing another configuration example of the buffer memory control device according to the fourth embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a conventional buffer memory control device.

FIG. 9 is a schematic diagram showing an overflow / underflow detection operation of the conventional buffer memory control device.

FIG. 10 is a schematic diagram showing a configuration of an address comparison circuit, an overflow occurrence notification circuit, and an empty occurrence notification circuit of a conventional buffer memory control device.

FIG. 11 is a schematic diagram showing a configuration example of a conventional cell buffer control circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Buffer memory 1a, 1b, 1c Memory area 2 Write address generation circuit 3 Write address 4 Write data 5 Write enable 6 Read address generation circuit 7 Read address 8 Read data 9 Read enable 10-12 Write address decoder 13-15 Flag register 16 To 18 read address decoder 19 to 21 flag reset register 22 to 24 flag signal 25 to 27 flag reset signal 28 overflow occurrence notifying circuit (logical product) 29 data discriminating circuit 30 overflow occurrence detecting circuit 31 pseudo data generating circuit 32 pseudo data 33 pseudo Data selection signal 34 Selection circuit 35 Transfer data 36-41 Match detection circuit 42-44, 49-51 Address setting register 45-47 Setting data 48 External input data

Claims (6)

[Claims] 1. A buffer memory divided into a plurality of memory areas in cell units, which are data units, by a address, a write address generation circuit for outputting a write address of the buffer memory, and outputting a read address of the buffer memory. A read address generation circuit, a first register that decodes the write address, and outputs a flag signal indicating a write address before the end of data writing for each cell unit, and stores the flag signal in the buffer memory by the flag signal. A data discriminating circuit for discriminating presence / absence of data in a cell unit and performing read control of the buffer memory; a flag reset for indicating completion of reading of data in each cell unit by decoding the read address and resetting the flag signal A second register for outputting a signal; An overflow occurrence notifying circuit for notifying the occurrence of an overflow of the buffer memory by the flag signal, and performing read control of the buffer memory by the data discriminating circuit, and stopping transfer of write data before an overflow of the buffer memory occurs. A buffer memory control device for notifying and transferring data in cell units to prevent data loss. 2. The buffer memory control device according to claim 1, wherein a flag signal is input, read control of the buffer memory is performed when there is no cell unit data in the buffer memory, and a pseudo data selection signal and a cell unit A buffer memory control device, comprising: a pseudo data generation circuit that outputs pseudo data; and a selection circuit that selects one of the pseudo data and the read data of the buffer memory based on the pseudo data selection signal. 3. The buffer memory control device according to claim 1, wherein: a register capable of externally setting an address value; a first match detection circuit for detecting a match between the value of the register and a write address; A buffer memory control device, comprising: a second match detection circuit for detecting a match between a value and a read address, wherein a memory area of the buffer memory can be divided into arbitrary units. 4. A buffer memory divided into a plurality of memory areas in units of cells as data units by an address, a write address generating circuit for outputting a write address of the buffer memory, and outputting a read address of the buffer memory. A read address generation circuit, a first register that outputs a flag signal indicating a write address at a point in time when data writing for each cell is completed or earlier by decoding the write address, and a first register that outputs the flag signal according to the flag signal. A data discriminating circuit for discriminating the presence / absence of data in cell units in the buffer memory and performing read control of the buffer memory; and indicating completion of reading of data in cell units by decoding the read address. Output a flag reset signal 2; a flag signal and a write address; and an overflow detection circuit for notifying a stop of write data transfer before an overflow occurs due to the flag signal and the write address. A buffer memory control device for performing read control of a buffer memory, notifying stop of write data transfer before an overflow of the buffer memory occurs, and transferring data in units of cells to prevent data loss. . 5. The buffer memory control device according to claim 4, wherein a flag signal is input, and when there is no data in a cell unit in the buffer memory, read control of the buffer memory is performed, and at the same time, a pseudo data selection signal and a cell unit A buffer memory control device, comprising: a pseudo data generation circuit that outputs pseudo data; and a selection circuit that selects one of the pseudo data and the read data of the buffer memory based on the pseudo data selection signal. 6. The buffer memory control device according to claim 4, wherein: a register capable of externally setting an address value; a first match detection circuit for detecting a match between the register value and a write address; A buffer memory control device, comprising: a second match detection circuit for detecting a match between a value and a read address, wherein a memory area of the buffer memory can be divided into arbitrary units.