JPH1164452A - Tester-facilitating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily test a board without using a logic circuit in an original circuit and to accurately create test data quickly by inputting a test signal to a group of input pins and testing the board, based on the logic value of the output signal of a test output pin. SOLUTION: For packaging a logic large-scale integrated circuit(LSI) 1 on a printed circuit board and performing the connection test of the logic LSI 1 and the printed circuit board, namely performing the board test easily, the output of an input circuit 21 immediately after all groups of input pins in the logic LSI 1 is inputted to an original circuit 20 and at the same time is branched and is connected to a test output circuit 31 of a multiple-input logic OR circuit and then the output signal is outputted to a test output pin 13. Also, an output circuit 30 of a 2-input logic OR circuit is connected to input immediately near a group of all output pins 12 of the original circuit 20 of the logic LSI 1 and the output of a board test pin 11 is connected to one input of all output circuits 30, thus fixing a group of output pins 12 on execution of a board test to a logic '1' regardless of the output state of the original circuit 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test facilitating circuit, and more particularly to a test facilitating circuit for mounting a logic large-scale semiconductor integrated circuit (LSI) on a printed circuit board to facilitate a board test.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional test facilitation circuit. When testing the connection state between the input terminals IN1 and IN2 and the printed board, the signal A is input from the terminal TE1 and the multiplexers 1a and 1b are connected to the input terminals IN1 and IN1.
The signal of IN2 is selected. Input terminals IN1,
A high level or a low level is input to IN2, and a test clock CK is input from the SCK terminal, so that the input terminals IN are input to the flip-flops 4a and 4b.
1. The input level of IN2 is held. Thereafter, the held data is sequentially shifted to the flip-flops 4a to 4d by the test clock CK and output to the output terminal TOD. Here, if the input terminals IN1 and IN2 have an open defect or a short-circuit defect with another terminal, a level different from the level given to the input terminals IN1 and IN2 is output. In this case, it is determined to be defective. .

To test the connection between the output terminals OUT1 and OUT2 and the printed circuit board, a signal A is input from the terminal TE1 and the multiplexer 1a selects the test data input from the TID terminal.
b selects the output data S1 of the flip-flop 4a. Thereby, the flip-flops 4a to 4d
Has a shift register structure, and the level given to the TID terminal is the test clock CK input from the SCK terminal.
, And an arbitrary level is set to the flip-flops 4c and 4d for the output terminals OUT1 and OUT2.

[0004] The levels set in the flip-flops 4c and 4d are output to output terminals OUT1 and OUT2 via multiplexers 5a and 5b, respectively. Here, if the output terminals OUT1 and OUT2 have an open defect or a short-circuit defect with another terminal, a level different from the expected value is output, and in this case, it is determined to be defective.

As described above, in the conventional circuit, the flip-flops 4a to 4
By sharing d with the circuit board test circuit, the influence on the actual operation timing of the actual operation logic unit 6 can be reduced.

[0006]

However, in the above-mentioned conventional circuit, an extra load is increased for the outputs of the flip-flops 4a to 4d, and it is necessary to adopt a circuit configuration in which a circuit delay is taken into consideration. A circuit which can switch the actual operation signal and the test signal must be provided at each of the data input and clock input portions by extracting the operation logic flip-flop.

Further, in the conventional circuit, the flip-flops used in the actual operation logic are connected in series to set the test state, so that a switching circuit for transmitting the logical value in the test state in series is unnecessary. The clock signal is used to operate the flip-flops to output the test logic state, and the test data is sequentially propagated through the flip-flops and test data is created until the logic states of all flip-flops reach the test output pins It takes time.

[0008] The present invention has been made in view of the above points,
An object of the present invention is to provide a test facilitation circuit which can be realized by a simple gate circuit so that a circuit is not originally output to an output pin.

It is another object of the present invention to provide a test facilitating circuit which outputs a test state of an input pin to a test output pin through a simple gate circuit without passing through a circuit.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a board for a logic integrated circuit which has a built-in circuit connected between an input pin group and an output pin group and is mounted on a printed circuit board. In the test facilitation circuit for testing,
A test output circuit for branching and inputting a signal originally input to the circuit from the input pin group, performing a predetermined logical operation, and outputting to a test output pin provided on the logic integrated circuit, and a board provided on the logic integrated circuit The test pin and the board test signal from the board test pin are input in common,
An output signal which is originally output from the circuit and supplied to each output pin constituting an output pin group is input, and a predetermined logical operation is performed on these input signals to constitute each output pin constituting the output pin group. And an output circuit provided for each output pin. During a board test, a signal of a preset logical value is input to the board test pin to fix the output signal of the output pin group to a predetermined logical value. , A test signal is input to an input pin group, and a board test is performed based on a logical value of an output signal of a test output pin.

According to the present invention, a signal of a preset logic value is input to a board test pin during a board test, so that the output signals of the output pin group are fixed to a predetermined logic value regardless of the logic operation of the circuit. The logic value corresponding to the input logic value of the input pin group can be output to the test output pin via the test output circuit, bypassing the circuit.

[0012]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a test facilitation circuit according to the present invention. In this embodiment, in order to easily implement a connection test between the logic LSI 1 and the printed board, that is, a board test by mounting the logic large-scale integrated circuit (LSI) 1 on a printed board, all the input pins in the logic LSI 1 are required. The output of the input circuit 21 immediately after the group (excluding the test input pin) 10 is originally input to the circuit 20 and is branched and connected to the test output circuit 31 of the multi-input OR circuit. 13 is output.

The output circuit 30 of a two-input OR circuit is connected to the nearest input of all output pin groups (excluding test output pins) 12 of the original circuit 20 of the logic LSI 1, and a board test pin 11 is connected to one of the inputs of all the output circuits 30 so that the output pin group 12 can be fixed to logic “1” regardless of the output state of the circuit 20 when the board test is executed.

Next, the operation of this embodiment will be described in detail with reference to FIG. At the time of performing the board test, a logic level for bringing the output pin group 12 of the logic LSI 1 into a test state is given to the board test pin 11 of the logic LSI 1. As a result, the output circuit 30 in the logic LSI 1 becomes valid, the output signal of the circuit 20 is suppressed, and the test state logic level of the board test pin 11 is output to the output pin group 12 and connected to the output pin group 12. A board test can be easily performed by checking a logic state at an input pin of a logic circuit on a board.

To perform a board test with a logic circuit on a board connected to the input pin group 10 of the logic LSI 1, only one pin of the input pin group 10 has a logic "0".
Level, and all other input pins are logic "1"
By setting the level, the logical level appears on the test output pin 13 through the test output circuit 31 as it is, and the connection of the pin to which the logical “0” level in the input pin group 10 is given can be confirmed.

Next, the logic "in the input pin group 10"
When the pin set to 0 "is set to logic" 1 ", the test output pin 13 is set to logic" 1. "This is sequentially repeated for all the pins of the input pin group 10, thereby
A board test for the input pin group 10 of the logic LSI 1 can be performed.

As described above, in this embodiment, a logic "1" level is given to the board test pin 11 at the time of executing the board test, and the output pin group 12 is set to the logic "1" irrespective of the output state of the circuit 20. In this way, it is possible to fix the state in a short time and accurately in the logic circuit on the board connected to the output pin group 12 in a short time.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An input circuit 21 is not provided for a test facilitating circuit, but is provided as a normal circuit. The test output circuit 31 is configured by a multi-input OR circuit. The output circuit 30 is a circuit provided for the test facilitating circuit. Each of the output circuits 30 includes a two-input OR circuit, and is provided in a one-to-one correspondence with a plurality of output pins constituting the output pin group 12.

The present invention is not limited to the above embodiments and examples. For example, the output circuit 30 and the test output circuit 31 are not OR circuits but AND circuits.
The same test can be executed even if the logic level is set to a value opposite to that of the embodiment and the example.

[0021]

As described above, according to the present invention,
At the time of executing the board test, the output of the original circuit in the logic LSI is fixed to a predetermined logical value, and the logical value corresponding to the input logical value of the input pin group is bypassed to the original circuit to the test output pin via the test output circuit. Because the output is made, the board test can be easily executed without using the logic circuit in the circuit, and the state of the input pin and the output pin can be Test data for a board test can be created accurately in a short time.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Logical large-scale integrated circuit (LSI) 10 Input pin group 11 Board test pin 12 Output pin group 13 Test output pin 20 Original circuit 21 Input circuit 30 Output circuit 31 Test output circuit

Claims (3)

[Claims] 1. A test facilitating circuit for performing a board test of a logic integrated circuit mounted on a printed circuit board, the test facilitating circuit including a primary circuit connected between an input pin group and an output pin group. A test output circuit that is branched and input signals that are originally input to the circuit, performs a predetermined logical operation, and outputs to a test output pin provided in the logic integrated circuit; and a board test pin provided in the logic integrated circuit. A board test signal from the board test pin is commonly input, and an output signal which is output from the original circuit and is supplied to each output pin constituting the output pin group is input. An output circuit provided for each of the output pins for performing a predetermined logical operation on the output pins to output the output pins constituting the output pin group. A signal of a preset logical value is input to the board test pin to fix the output signal of the output pin group to a predetermined logical value, and a test signal is input to the input pin group to output the test signal of the test output pin. A test facilitation circuit characterized in that a board test is performed based on a logical value. 2. The test output circuit inputs a signal of a first logical value only to one input pin of a plurality of input pins constituting the input pin group, and supplies a second signal to all of the remaining input pins. 2. The test facilitation circuit according to claim 1, wherein when a logical value signal is input, a signal of a predetermined logical value is output to the test output pin when the connection is normal. 3. When the board test signal input from the board test pin is a signal having the predetermined logic value, the output circuit is configured to output the predetermined logic signal irrespective of the logic value of the output signal of the circuit. 3. The signal according to claim 1, wherein a signal of a value is output, and when the board test signal is a signal having a logical value different from the preset logical value, an output signal of the original circuit is output. 4. Test facilitation circuit.