JPH1145226A - Bus controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently use a common bus while suppressing the complexing of wiring constitution between each bus master and a bus controller. SOLUTION: In this bus controller provided with the common bus 10, bus masters 20a to 20d which transfer data by using it and bus controller 30 which arbitrates the use of the common bus 10 at a request, the respective bus masters 20a to 20d send the common bus use request and information attached thereto by using one of signal lines 41a to 41d and the bus controller 30 arbitrates a conflicting common bus use request using the attached information as one of conditions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control device having a function of arbitrating a common bus shared by a plurality of bus masters when the use requests conflict with each other.

[0002]

2. Description of the Related Art A bus control device is used in a computer system or the like, and includes a common bus, a memory and an input / output (I / O) connected to the common bus.
A device such as an apparatus and a CPU (Central Processing Unit) or DMA (Direct
A bus master such as a memory access controller, and a bus controller that arbitrates requests for using a common bus from a plurality of bus masters.

Conventionally, in such a bus control device,
Each bus master transmits a bus use request signal to the bus controller when requesting use of the common bus. Further, when the bus use request signals from the respective bus masters compete with each other, the bus controller responds to each use request in accordance with a priority determined in advance for each bus master, a round robin method in which the priority changes in a time division manner, or the like. Mediation is performed.

However, a simple arbitration method such as a fixed priority for each bus master or a round robin method may not be able to efficiently control the use of the common bus. For example, some bus masters change the urgency of a request to use a common bus according to the operation state inside and outside the bus master. However, a data transfer error between devices may occur without sufficiently waiting for the arbitration result by the bus controller, and as a result, the common bus cannot be used efficiently.

For this purpose, for example, Japanese Patent Application Laid-Open No. Hei 6-23634
Japanese Patent Application Laid-Open No. 7-313873 has a means for inputting an operation state of a device under the jurisdiction of the bus master or the bus master itself to the bus controller. Which can be dynamically changed according to the operating state of the bus master, that is, the operating state inside and outside the bus master.

[0006]

However, in the technique disclosed in Japanese Patent Application Laid-Open No. 6-236347, the communication between each bus master and the bus controller is limited.
In addition to the signal line for transmitting the bus use request signal, a signal line for inputting an operation state inside and outside the bus master from each bus master to the bus controller is required. Therefore, when there are many bus masters, a large number of signal lines are required between each bus master and the bus controller, which complicates the wiring (circuit) configuration of the entire device. As a result, the size of the apparatus is increased.

Further, with the complicated wiring configuration between each bus master and the bus controller, it is not easy to cope with a case where a new bus master is to be additionally connected to the bus controller. As a result, it becomes difficult to secure versatility and expandability.

Accordingly, the present invention is to minimize the complexity of the wiring configuration between each bus master and the bus controller,
An object of the present invention is to provide a bus control device capable of realizing efficient use of a common bus.

[0009]

SUMMARY OF THE INVENTION The present invention is a bus control device devised to achieve the above object, comprising: a common bus;
A plurality of devices connected to the common bus, a plurality of bus masters for transferring data between the plurality of devices using the common bus, and a bus controller for arbitrating a common bus use request from the plurality of bus masters Wherein the plurality of bus masters comprises:
Each of the plurality of bus masters includes information transmitting means for transmitting a common bus use request and accompanying information accompanying the common bus use request to the bus controller using a single signal line. When the common bus use requests from the above conflict, the arbitration means for arbitrating the common bus use requests is provided on condition that the accompanying information accompanying each common bus use request is one of the conditions.

[0010] According to the bus control device having the above-described configuration, the priority order when the bus controller performs arbitration is dynamically changed by the bus master transmitting the accompanying information, for example, according to the operation state inside and outside the bus master. It becomes possible. In addition, the accompanying information is transmitted on one signal line accompanying the common bus use request, so that the bus master and the bus controller transfer the accompanying information separately from the signal line for the common bus use request. It is not necessary to newly provide a signal line for inputting to the controller.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A bus control device according to the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is an explanatory diagram of a bus request signal transmitted in the bus control device of the present embodiment, and FIG. 2 is a schematic diagram of the bus control device of the present embodiment. FIG. 3 is a block diagram illustrating a configuration.

As shown in FIG. 2, the bus control device according to the present embodiment includes a common bus 10 and devices (not shown) such as a memory and an I / O device connected to the common bus 10.
And a plurality of bus masters 20a, 20b, 20 connected to the common bus 10 and performing data transfer between devices.
c, 20d, and each bus master 20a, 20b, 20c,
And a bus controller 30 for arbitrating the use request of the common bus 10 from the communication device 20d. Here, the case where the number of bus masters is four will be described as an example, but this is not intended to limit the number of bus masters to four.

Each bus master 20a, 20b, 20c, 2
0d and the bus controller 30 are connected by bus use request signal lines 41a, 41b, 41c, 41d and bus use permission signal lines 42a, 42b, 42c, 42d. Bus use request signal lines 41a, 41b, 41
c, 41d are bus masters 20a, 20b, 20c,
20d to the bus controller 30 for transmitting a bus request signal described in detail later. The bus use permission signal lines 42a, 42b, 42c, 42d are transmitted from the bus controller 30 to the respective bus masters 20a, 20b, 20c,
The bus permission signal is transmitted to 20d as a result of arbitration for the use request of the common bus 10.

Here, each bus master 20a, 20b, 2
The bus request signal transmitted from 0c and 20d to the bus controller 30 will be described with reference to FIG. The bus request signal is a signal including a use request signal for requesting use of the common bus 10 and accompanying information accompanying the use request signal and information for inputting the operation state of the bus master to the bus controller 30. It is.

More specifically, as shown in FIG. 1A, the bus request signal is at "H (high) level" when there is no request for use of the common bus 10 and the bus is in an idle state. Is requested, first, the signal goes to the "L (low) level" for one system clock to indicate the start of the request. The bus masters 20a, 20a
It is assumed that b, 20c, 20d and the bus controller 30 share a system clock of a predetermined frequency, and each of them operates in synchronization with the system clock.

Subsequent to the "L level" for one clock indicating the start of a request, accompanying information is located. This means that if high-speed processing in the system is required, the accompanying information is transmitted to the bus controller 3 before the use request signal for the common bus 10.
0 should be transmitted.

As shown in FIG. 1B, the accompanying information is composed of a 3-bit serial code individually corresponding to the content indicating the operation state of the bus master. The information specifies the allowable waiting time from when the use of the common bus 10 is requested to when the use is permitted. For example, if the serial code is “010” (see FIG. 1A), it corresponds to the content of “I want to get the right to use the bus within 20 clocks after the request”.

In the accompanying information, priorities are determined in advance among several types of serial codes. For example, the higher the request in the upper row in the figure, that is, the shorter the allowable waiting time, the higher the priority. It has become.

In the bus request signal, a use request signal for requesting use of the common bus 10 is located from the next clock of the accompanying information, and is maintained at “L level”, thereby using the common bus 10. It is indicated that the request is being made.

A bus request signal including such a use request signal and accompanying information is transmitted from a bus master, for example, the bus master 20a, via the bus use request signal line 41a when the bus master 20a tries to use the common bus 10. And transmitted to the bus controller 30. That is, each bus master 20a, 20b, 20c, 20d has a function of transmitting a bus request signal including a use request signal and accompanying information to the bus controller 30 using the bus use request signal lines 41a, 41b, 41c, 41d. Have. This function is provided by each of the bus masters 20a, 20b, 20c, 20d.
Is realized by executing a predetermined program.

Next, the internal configuration of the bus controller 30 to which the above bus request signal is transmitted will be described. As shown in FIG. 3, the bus controller 30 includes a serial / parallel conversion unit 31 and a priority determination unit 32.

The serial-to-parallel converter 31 includes bus request signals 51a to 51d transmitted from the bus masters 20a, 20b, 20c, and 20d via the bus use request signal lines 41a, 41b, 41c, and 41d, respectively.
a, 20b, 20c, and 20d, and the shared system clock 52, and outputs one bus request code 53a to 53d per bus master to the priority determination unit 32. That is, the serial-parallel conversion unit 31 performs parallel conversion on the serial signals input as the bus request signals 51a to 51d.

The priority determining unit 32 receives the bus request codes 53a to 53d from the serial / parallel conversion unit 31 and, based on the bus request codes 53a to 53d, outputs a bus request signal having the highest priority when a conflict occurs. The use permission of the common bus 10 is given to the transmitted bus master. This use permission is determined by the priority determination unit 32.
Are the bus use permission signal lines 42a, 42b, 42c, 42
bus permission signals 54a to 54d transmitted by using
By asserting it to “L level”, it is given to any of the bus masters 20a, 20b, 20c, 20d.

Here, an example of the processing operation when the bus controller 30 having such an internal configuration receives the bus request signals 51a to 51d will be described. In the serial / parallel converter 31 of the bus controller 30, as shown in FIG. 4, each bus use request signal line 41a, 41b, 41
c and 41d are constantly monitored, and bus request signals 51a to 51d are monitored.
When 51d is asserted to "L level" (step 1)
01, the steps are abbreviated as S), and the serial / parallel conversion is performed on the subsequent 3-bit accompanying information (S10).
2). For example, in the case of the accompanying information in FIG. 1A, a bus request code of “010” is obtained by serial-parallel conversion.

Then, the serial / parallel conversion unit 31
The converted bus request codes 53a to 53d are transmitted to the priority determination unit 32 (S103). Then, the bus request signal 5
When 1a to 51d are negated to “H level” (S1
04), the serial / parallel converter 31 sets the bus request code to “111”, thereby notifying the priority determining unit 32 that the corresponding bus master has finished using the common bus 10 (S105).

On the other hand, as shown in FIG. 5, the priority order judging section 32 judges whether each of the bus masters 20a, 20b, 20c, 20
d, the bus request signal is transmitted (S20).
1) If they conflict with each other, a bus request code, which is a conversion result of the bus request signal, is received from the serial / parallel converter 31 and the priority of the bus request code is checked. Note that this priority is determined in advance as described above, and the one with the shorter allowable waiting time is given priority.

Then, the priority determining unit 32 checks whether or not there are a plurality of received bus request codes having the highest priority (S202), and if not, determines the highest bus request code. Common bus 1 for the bus master that sent
A use permission of 0 is given (S203), and if there is more than one, use permission of the common bus 10 is given to any one of them in a predetermined order (for example, in ascending order of numbers given in advance) (S204).

That is, when the bus request signals 51a to 51d from the respective bus masters 20a, 20b, 20c and 20d compete with each other, the priority determining unit 32 determines that each bus request signal 51
The bus request codes 53a to 53d for the a to 51d, that is, the accompanying information included in each of the bus request signals 51a to 51d is one of the conditions,
To 51d.

For example, a bus request code 53a from a certain bus master 20a is "001", a bus request code 53b from another bus master 20b is "010", and a bus request code 53b from another bus master 20c, 20d. When the request signals 51c and 51d are not transmitted, the priority determining unit 32 gives the bus master 20a permission to use the common bus 10. In another case, the bus master 20
a, 20b, the bus request code 53a, 53b is "00".
If the bus request codes 53c and 53d from the bus masters 20c and 20d are "010", the priority order of the bus master 20a and the bus master 20b is the same. For example, the use permission of the common bus 10 is given to the bus master 20a having the smaller number.

Thereafter, when the use of the common bus 10 is notified by the bus request code from the serial / parallel conversion unit 31 (S205), the priority determination unit 32
Determines whether a bus request signal has been transmitted from any of the bus masters 20a, 20b, 20c, and 20d (S201). If a bus request signal has been transmitted, the above steps are repeated.

As described above, in the bus control device of the present embodiment, each of the bus masters 20a, 20b, 20c, 20d
When each of them attempts to use the common bus 10, each of them transmits a bus request signal including a use request signal and accompanying information to the bus controller 30 using the bus use request signal line 41a. At this time, each bus master 20
Each of a, 20b, 20c, and 20d transmits, as incidental information, information on an allowable waiting time after requesting use of the common bus 10, and encodes the incidental information into a serial signal and transmits the serial signal. I have.

On the other hand, in the bus controller 30, when the bus request signals from the bus masters 20a, 20b, 20c, and 20d compete with each other, for example, the allowable waiting time is determined based on the accompanying information included in each bus request signal. Arbitration is performed using the accompanying information as one of the conditions, such as giving permission to use the common bus 10 in preference to shorter ones.

Therefore, in this bus control device, the priority order at which the bus controller 30 performs arbitration is determined according to the internal or external operating state of each of the bus masters 20a, 20b, 20c, 20d, specifically, the allowable waiting time. Arbitration can be appropriately performed even when the operation state is different every time the use of the common bus 10 is requested, and the efficiency of the entire apparatus can be improved. It is possible to realize efficient and smooth processing.

However, in the bus control device according to the present embodiment, between the bus masters 20a, 20b, 20c, 20d and the bus controller 30, both the use request signal and the accompanying information are transmitted through the bus use request signal line 41a. , 41
b, 41c and 41d. Thereby, each bus master 20a, 20b, 20
c, 20d and the bus controller 30, signal lines for inputting accompanying information to the bus controller 30 are provided.
There is no need to provide a new one, and it is possible to dynamically change the priority order, and to minimize the complexity of the wiring configuration. Further, since the complexity of the wiring configuration can be suppressed as much as possible, additional connection of a new bus master is facilitated, and versatility and expandability are secured.

This is realized by encoding the accompanying information into a serial signal and transmitting it together with the use request signal.

Further, in this embodiment, since each of the bus masters 20a, 20b, 20c, and 20d transmits information on the permissible waiting time as accompanying information, the bus controller 30 responds to the conflicting bus request signal. Therefore, it is possible to perform appropriate arbitration in accordance with the operation state of each bus master 20a, 20b, 20c, 20d,
As a result, each bus master 20a, 20b, 20c, 20
It is possible to perform efficient and smooth processing according to the operation state of d.

[Second Embodiment] Next, a second embodiment of the bus control device according to the present invention will be described.
However, here, only the differences from the above-described first embodiment will be described.

In the bus control device of this embodiment, as in the case of the first embodiment, each of the bus masters 20a, 20a
6b, 20c and 20d transmit a bus request signal as shown in FIG. 6A, that is, a bus request signal including accompanying information encoded in a serial signal to the bus controller 30.

However, unlike the case of the first embodiment, this accompanying information contains information on the number of data to be transferred using the common bus 10, as shown in FIG. For example, "01
A serial code of "0" corresponds to the content of "the data to be transferred is four words". It should be noted that “1 word” is a value corresponding to the bit width of the common bus 10, and is a value that is the minimum transfer unit and the minimum number of data transfers when performing data transfer. That is,
If the common bus 10 is 32 bits wide, the minimum value of the number of data transfers, that is, "1 word" corresponds to 32 bits.

Priorities among these serial codes are determined in advance. For example, the higher the request in the upper row in the figure, that is, the larger the number of data transfers, the higher the priority.
It is arbitrated as a high priority. This is because, when the common bus 10 is used, the transfer efficiency is better if data transfer is performed continuously.

Therefore, in the priority order determination section 22 of the bus controller 30, each of the bus masters 20a, 20b, 20
When the bus request signals from c and 20d conflict, based on the accompanying information included in each bus request signal, for example, the use of the common bus 10 is given priority over the one with the larger number of data transfers. Arbitration is performed using the accompanying information as one of the conditions.

As described above, in the bus control device according to the present embodiment, each bus master 20a, 20b, 20c, 20d
Transmits information on the number of data transfers as accompanying information, so that the bus controller 30 can perform arbitration according to the number of data transfers, and as a result, efficient data transfer, Bus 10
Can be used efficiently.

[Third Embodiment] Next, a third embodiment of the bus control device according to the present invention will be described.
However, here, only differences from the above-described first and second embodiments will be described.

In the bus control device of the present embodiment, as shown in FIG. 7, four devices 1, 2, 3, 4 and three bus masters A, B, C are connected to a common bus 10 Each of the bus masters A, B, and C has its own device 1,
The data transfer between 2, 3, and 4 is controlled. However, this is not intended to limit the number of bus masters or devices.

Of these bus masters A, B and C, it is assumed that the bus master A is composed of a CPU, and that each of the bus masters B and C is a DMA controller. Device 1 is a memory, Device 2 is a hard disk drive,
The device 3 is a parallel I / O device, and the device 4 is an IOT (Image Output Terminal) such as a printer engine.

In the bus control device having such a configuration,
When requesting use of the common bus 10, each of the bus masters A, B, and C transmits a bus request signal to a bus controller (not shown). However, each of the bus masters A, B, and C transmits a bus request signal as shown in FIG. 8A, that is, a bus request signal including accompanying information encoded in a serial signal to the bus controller. I have.

As shown in FIG. 8B, the accompanying information specifies information relating to the type of a device to which data is to be transferred among a plurality of devices 1, 2, 3, and 4. For example, a serial code of "010" corresponds to the content that "devices to be accessed are 1 and 2", that is, data is transferred between a memory and a hard disk device. Note that a priority order is predetermined between these serial codes.

Here, the priority order will be described.
Of the plurality of devices 1, 2, 3, and 4, as for the device 4, that is, the IOT, the IOT cannot perform printing properly unless a predetermined amount of data is transferred within a certain period of time. , The system may not function properly. Therefore, with respect to a data transfer request to the IOT, the use of the common bus 1 is permitted with the highest priority. On the other hand, the other devices 1, 2, and 3, that is, the memory, the hard disk device, and the parallel I / O device do not have such a restriction, so that the priority may be determined from the viewpoint of system performance.

Therefore, here, as shown in FIG. 9, when data is transferred from the memory to the IOT, that is, when “devices to be accessed are 1 and 4”, the priority is the highest, and hereinafter “access is performed”. The priority is made lower in the order of “the device is only 1”, “the devices to be accessed are 1 and 2”, and “the devices to be accessed are 1 and 3”.

In the bus controller, when the bus request signals from the bus masters A, B, and C conflict, the first
Alternatively, as in the case of the second embodiment, the data transfer from the memory to the IOT is given the highest priority, for example, based on the accompanying information included in each bus request signal.
For example, arbitration is performed using the accompanying information as one of the conditions, such as giving permission to use 0.

As described above, in the bus control device of the present embodiment, each of the bus masters A, B, and C transmits information on the type of the device to which data is to be transferred as accompanying information. The bus controller can perform arbitration in accordance with the arbitration, and the efficiency of the system can be improved, that is, the common bus 10 can be used efficiently.

In this embodiment, the case where the accompanying information is a 3-bit serial signal has been described as an example. However, the present invention is not limited to this, and the serial signal having other bits is used. However, it is feasible.

[0054]

As described above, according to the bus control device of the present invention, both the use request of the common bus and the accompanying information accompanying the common bus are one signal line between the bus master and the bus controller. It is not necessary to provide a new signal line for inputting the accompanying information to the bus controller, and it is possible to minimize the complexity of the wiring configuration, and to send the accompanying information to the bus controller. By inputting, appropriate arbitration in accordance with the operation state of the bus master or the like becomes possible, so that efficient and smooth processing can be performed as a whole device.

[Brief description of the drawings]

FIGS. 1A and 1B are explanatory diagrams of a bus request signal according to a first embodiment of the present invention, wherein FIG. 1A is a diagram showing a configuration of a bus request signal, and FIG. It is a figure showing contents.

FIG. 2 is a block diagram illustrating a schematic configuration of an example of an embodiment of a bus control device according to the present invention.

FIG. 3 is a block diagram illustrating an example of an internal configuration of a bus controller.

FIG. 4 is a flowchart illustrating a processing operation example of a serial-parallel conversion unit when a bus controller receives a bus request signal.

FIG. 5 is a flowchart illustrating a processing operation example of a priority determination unit when a bus controller receives a bus request signal.

FIGS. 6A and 6B are explanatory diagrams of a bus request signal according to the second embodiment of the present invention, wherein FIG. 6A is a diagram showing a configuration of the bus request signal, and FIG. It is a figure showing contents.

FIG. 7 is a block diagram showing a configuration of a bus master and devices according to a third embodiment of the present invention.

FIG. 8 is an explanatory diagram of a bus request signal according to the third embodiment, where (a) is a diagram showing a configuration of the bus request signal;
(B) is a diagram showing the contents of accompanying information included in the bus request signal.

FIG. 9 is a diagram illustrating a priority order of accompanying information included in a bus request signal according to the third embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Common bus, 20a, 20b, 20c, 20d ... Bus master, 30 ... Bus controller, 31 ... Serial / parallel conversion part, 32 ... Priority determination part, 41a, 41
b, 41c, 41d... bus use request signal lines

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Yoshinobu Terui 2274 Hongo, Ebina-shi, Kanagawa Fuji Xerox Co., Ltd. Inside

Claims (5)

[Claims] 1. A common bus, a plurality of devices connected to the common bus, a plurality of bus masters performing data transfer between the plurality of devices using the common bus, and a common bus from the plurality of bus masters A bus controller that performs arbitration for a bus use request, wherein each of the plurality of bus masters transmits, to the bus controller, a common bus use request and accompanying information accompanying the common bus use request; An information transmitting means for transmitting using a single signal line, wherein when the common bus use requests from the plurality of bus masters compete with each other, the bus controller sets, as one of the conditions, the accompanying information attached to each common bus use request And a arbitration means for arbitrating the common bus use request. 2. The bus control device according to claim 1, wherein said information transmitting means encodes the accompanying information into a serial signal and transmits the serial signal. 3. The information transmitting means transmits, as the accompanying information, information on an allowable waiting time from a request to the bus controller to use the common bus to a permission to use the common bus. The bus control device according to claim 1, wherein the bus control device performs the operation. 4. The information transmitting unit according to claim 1, wherein the information transmitting unit transmits, as the accompanying information, information on the number of data to be transferred using the common bus. Bus controller. 5. The information transmitting unit according to claim 1, wherein the information transmitting unit transmits, as the accompanying information, information regarding a type of a device to which data is to be transferred among the plurality of devices. 3. The bus control device according to 2.