JPH1141564A - Interpolation processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To unnecessitate high-speed processing while suppressing the expansion of the circuit scale by using a delay circuit in common for a signal generating circuit and a contour correcting circuit. SOLUTION: An interpolate signal generating circuit for performing average value interpolation inputs a current signal f(t) of a video signal corresponding to an interlace, is composed of a delay circuit 2, adder 6 and coefficient multiplier circuit 10 and outputs a 1st interpolate signal VH1 . The contour correcting circuit for performing contour emphasis is composed of delay circuits 2 and 3, coefficient multiplier circuits 11-13 and adder 7. A contour extracting circuit 4 extracts a contour component in the current signal f(t). A contour correction amount control circuit is composed of the contour extracting circuit 4, low-pass filter 5 and multiplier 8. The output of the contour correction amount control circuit is added to the output signal of the adder 7 as the output of the contour correcting circuit by an adder 9 and outputted as a 2nd interpolate signal VH2 .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for converting a video signal compatible with interlaced scanning into a video signal compatible with non-interlace, and in particular, outputs an interpolation signal for performing scanning line interpolation. And an interpolation processing circuit.

[0002]

2. Description of the Related Art Video signals from a normal TV receiver or the like are displayed in an interlaced manner. When displaying an interlaced video signal on a non-interlaced display device such as a personal computer display, it is necessary to convert the scanning method.

[0003] When converting an interlaced video signal into a non-interlaced video signal, scanning line interpolation is performed. The scanning line interpolation includes a line interpolation and a field interpolation. In these, the horizontal frequency is doubled without changing the field frequency (vertical frequency), and one screen (1
This is an interpolation method for doubling the number of scanning lines per frame to 525.

In order to double the number of scanning lines, it is necessary to insert an interpolation signal between the original scanning lines. As a method of inserting a signal for interpolation, for example, a video signal for each scanning line is written into a memory, and a writing speed of 2 is set.
There is a method of reading the same video signal twice at twice the speed.
By doing so, a video signal compatible with interlace can be converted into a video signal compatible with non-interlace, and the pixel density in the vertical direction can be improved.

Next, the scanning line interpolation method will be described in detail.

As described above, there are two types of scanning line interpolation: line interpolation and field interpolation. Line interpolation is a line correlation (the shape of the signals on the scanning lines that are vertically adjacent to each other is similar)
Is a two-dimensional scanning line interpolation method for obtaining a signal for interpolation by using a two-dimensional writing interpolation in which a video signal of the same scanning line is output twice continuously, and a video signal of a vertically adjacent scanning line is output. There is an average value interpolation using an average value as an interpolation signal.

On the other hand, the field interpolation is a three-dimensional scanning line interpolation method for obtaining a signal for interpolation by utilizing a field correlation (the shape of the video signal of the preceding and succeeding fields is similar). Are used as interpolation signals.

As a conventional example of such a scanning line interpolation,
For example, there is JP-A-62-135081 (contour correction circuit).

In general, when performing scanning line interpolation on a moving image, the interpolation processing is performed using only line interpolation or a combination of line interpolation and field interpolation.

In the case where scanning line interpolation is performed by combining line interpolation and field interpolation, generally, an area with a large amount of image movement uses line interpolation, and an area with a small amount of image movement uses field interpolation. As described above, processing is performed by appropriately switching between line interpolation and field interpolation for each arbitrary region in the screen according to the motion of the image.

On the other hand, field interpolation is generally used for still images. In the field interpolation, the video signal of the immediately preceding field (hereinafter, referred to as a previous field) is used as a signal for interpolation of a current field (hereinafter, referred to as a current field), so that the resolution in the vertical direction does not deteriorate.

However, when field interpolation is used for a moving image, the time between the previous field and the current field is 1 /
Since the images shifted by 60 seconds are displayed at the same time, an afterimage or a double image is generated, which deteriorates the image quality.

On the other hand, in line interpolation, two consecutive
Since the interpolation process is performed using the video signal of one scanning line, the influence of the time lag is reduced. However, it is difficult to obtain a line correlation for a signal having a high frequency component in the vertical direction, such as a contour portion of an image, so that it is difficult to obtain an accurate interpolation signal.

FIG. 7 is a block diagram showing a configuration of an interpolation signal generating circuit for performing average value interpolation.

In FIG. 7, an interpolation signal generating circuit 101
Is a current signal f which is a video signal corresponding to interlace.
Delay circuit 102 for delaying (t) by one horizontal scanning period
And an adder 106 for adding the current signal f (t) to the output signal of the delay circuit 102, and halving the output signal of the adder 106
And a coefficient doubling circuit 110 for doubling.

In such a configuration, average value interpolation is performed.
Signal from the interpolation signal generation circuit 101 for
Current signal V_GAnd an interpolation signal which is an output signal of the coefficient multiplication circuit 110.
Issue V _HIs output.

FIG. 8 is a block diagram showing a configuration of an interpolation signal generating circuit for performing twice writing interpolation.

In FIG. 8, an interpolation signal generation circuit 111
Has a delay circuit 112 for period delay of one horizontal scanning current signal f (t), the current signal V _G and the delay circuit in the input signal from the interpolation signal generation circuit 111 for performing double write interpolation 112 is an output signal of the interpolation signal V _H is outputted.

[0019] Here, as shown in FIG. 9 receives the current signal V _G and the interpolation signal V _H output from the interpolation signal generation circuit to the time base converting circuit 120, noninterlaced by performing time axis conversion Can be obtained as the output signal g (t).

The time axis conversion circuit 120 is, for example, a line
And the current signal V _GAnd the interpolation signal V_HWhen
Write at the same time, clock twice as fast as writing
By reading the current signal and the interpolation signal alternately, one frame
Configure the team.

When line interpolation is performed, the resolution in the vertical direction deteriorates. Therefore, image processing is performed by combining not only interpolation signal generation processing and time axis conversion, but also vertical contour correction. Hereinafter, this method will be described with reference to FIG.

FIG. 10 is a diagram showing a procedure for converting an interlaced video signal to a non-interlaced video signal.

As shown in FIG. 10A, when the contour correction is performed after the generation of the interpolation signal and then the time axis correction is performed,
Contour correction must be performed on each of two signals (current signal and interpolation signal). Therefore, such a processing procedure has a disadvantage that the scale of the contour correction circuit becomes large.

As shown in FIG. 10 (b), when the time axis conversion is performed after the generation of the interpolation signal, and then the contour correction is performed, the contour correction is performed for the non-interlaced video signal so that the contour correction is performed accurately. Can be corrected. However, since the contour correction must be performed at twice the speed of the interpolation signal generation processing, high-speed processing is required for the contour correction circuit.

Further, as shown in FIG. 10C, when only the time axis conversion is performed after the generation of the interpolation signal, the outline correction is not performed, so that it can be used for a simple system. However, when the line interpolation is used as the scanning line interpolation, the vertical resolution surely deteriorates.

Next, the difference between the original image and the image after the interpolation processing will be described using the display image shown in FIG. 11 as an example.

FIG. 11 is a diagram showing an example of a display image in which the luminance has changed across the diagonal lines. FIG. 12 is an enlarged view of the vicinity of the oblique line of the display image shown in FIG.
FIG. 4B shows an original image, FIG. 4B shows an image subjected to average value interpolation, and FIG. 5C shows an image subjected to twice writing interpolation. FIG.
1 is a monochrome image, and FIG.
2 is the scanning line position between the current field (current signal) and the previous field (previous signal), or the current field (current signal)
And the position of the scanning line of the interpolation signal. Further, the difference in the thickness of the line indicates the difference in the luminance, the thick line indicates black, and the thin line indicates white. In FIG. 12A, when one frame of the original image is configured by alternately arranging the scanning lines of the current signal and the scanning lines of the previous signal, it can be seen that oblique lines are clearly displayed.

On the other hand, when the average value interpolation is performed as shown in FIG. 12B, the luminance near the oblique lines of the interpolation signal becomes an intermediate value between the luminances of the vertically adjacent scanning lines, and is blurred in the vertical direction. Is displayed.

Further, as shown in FIG. 12 (c), when the writing interpolation is performed twice, the resolution in the vertical direction is deteriorated because the video signal of the same scanning line is written twice. . Note that the resolution of the twice writing interpolation is half the resolution that can be expressed by all the scanning lines.

That is, the vertical frequency characteristic is lowered by the interpolation signal generated by performing the line interpolation, and the vertical resolution is deteriorated.

FIG. 13 is a block diagram showing a configuration of a contour correction circuit for performing contour enhancement.

In FIG. 13, a contour correction circuit includes a first delay circuit 14 for delaying an input signal by one horizontal scanning period.
2, a second delay circuit 143 for delaying the output signal of the first delay circuit 142 by one horizontal scanning period, a first coefficient multiplication circuit 151 for multiplying the input signal by k, and a first delay circuit 1
A second coefficient multiplying circuit 152 for multiplying the output signal of C.42 by (1-2k), a third coefficient multiplying circuit 153 for multiplying the output signal of the second delay circuit 143 by k, and a first coefficient multiplying circuit 151 ,
Second coefficient multiplier 152 and third coefficient multiplier 153
And an adder 147 that adds the respective output signals of the two. Note that k is given a number from 0 to -0.5.

FIG. 14 is a frequency characteristic diagram showing an impulse response when a signal having an amplitude of 1 is input to the contour correction circuit shown in FIG.

The contour correction circuit shown in FIG. 13 corrects a signal that changes in the vertical direction on the screen in a direction to emphasize the contour. The transfer function of the contour correction circuit shown in FIG. 14 is as follows.

H (z) = k + (1-2k) z ^-1 + kz ^-2
(Z ^-1 corresponds to a delay time for one horizontal scanning period.)

[0036]

However, in the above-described conventional interpolation processing circuit, when performing interpolation processing on a still image, a vertical resolution close to the original image can be obtained by performing field interpolation. In the case where line writing or twice-value interpolation or average value interpolation is performed, the resolution in the vertical direction is degraded.

In particular, when line interpolation is performed on a moving image, the vertical frequency characteristics are reduced, so that when a diagonal line is displayed, the resolution of the contour portion is significantly deteriorated.

For this reason, the contour correction for enhancing the contour is performed, but there is a problem that the circuit scale becomes large. Also,
If the contour correction is performed after the time axis conversion, the contour correction requires twice as fast processing.

The present invention has been made in order to solve the above-mentioned problems of the conventional technology, and it is possible to suppress an increase in the circuit scale, to eliminate the need for high-speed processing, and to reduce the contour correction. It is an object of the present invention to obtain an interpolation processing circuit in which the deterioration of the resolution is reduced.

[0040]

In order to achieve the above object, an interpolation processing circuit according to the present invention is adapted to convert an interlaced video signal into a non-interlaced video signal. An interpolation processing circuit for outputting an interpolation signal for performing a scanning line interpolation of a video signal, comprising: a current signal which is a video signal corresponding to the interlace; and a delay delayed by one horizontal scanning period from the current signal. An interpolation signal generation circuit that outputs an average value of the signals as a first interpolation signal; a first delay circuit that delays the current signal by one horizontal scanning period; and an output signal of the first delay circuit that is 1
A second delay circuit that delays by the horizontal scanning period,
A contour correction circuit that enhances a vertical contour of an image by multiplying the current signal, the output signal of the first delay circuit, and the output signal of the second delay circuit by a predetermined coefficient, and then adding the multiplied coefficients. And extracting a vertical contour component of the image from the current signal, the output signal of the first delay circuit, and the output signal of the second delay circuit, and outputs the contour component in a changeable manner. A contour correction amount control circuit, an adder that adds an output signal of the contour correction circuit and an output signal of the contour correction amount control circuit, and outputs the added signal as a second interpolation signal;
It is characterized by having.

At this time, a delay signal used in the interpolation signal generation circuit may be obtained from an output signal of the first delay circuit.

The interpolation processing circuit configured as described above
The average value interpolation processing by the interpolation signal generation circuit and the contour enhancement processing by the contour correction circuit are performed simultaneously.

In such a circuit configuration, peaking is performed around the frequency 525/4 with respect to the vertical frequency characteristic, so that the vertical frequency characteristic of 525/4 or less is improved, and the vertical frequency component and the horizontal frequency component are reduced. It is possible to obtain an appropriate contour correction amount according to the above.

[0044]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an interpolation processing circuit according to the present invention. FIG. 2 is a block diagram showing a circuit configuration when the interlaced video signal is converted into a non-interlaced video signal using the interpolation processing circuit shown in FIG.

The interpolation processing circuit according to the present embodiment is a circuit for simultaneously processing interpolation signal generation and contour correction. In FIG. 1, an interpolation signal generating circuit that performs average value interpolation receives a current signal f (t), which is a video signal corresponding to interlace, and delays the current signal f (t) by one horizontal scanning period. No. 1 delay circuit 2, a first adder 6 for adding the current signal f (t) to the output signal of the first delay circuit 2, and the output signal of the first adder 6 is halved. First coefficient multiplying circuit 10
And outputs a first interpolation signal V _H1 .

The contour correction circuit for enhancing the contour includes a first delay circuit 2, a second delay circuit 3 for delaying the output signal of the first delay circuit 2 for one horizontal scanning period, and a current signal. a second coefficient multiplying circuit 11 for multiplying f (t) by k, a third coefficient multiplying circuit 12 for multiplying the output signal of the first delay circuit 2 by (1-2k), and a second delay circuit A fourth coefficient multiplying circuit 13 for multiplying the output signal of No. 3 by k times, a second coefficient multiplying circuit 11,
It comprises a second adder 7 for adding the output signals of the third coefficient multiplying circuit 12 and the fourth coefficient multiplying circuit 13, respectively.

Here, the current signal f (t), the output signal of the first delay circuit 2, and the output signal of the second delay circuit 3 are input to the contour extraction circuit 4, respectively. Contour extraction circuit 4
Is a fifth coefficient multiplying circuit 41 for making the output signal of the second delay circuit 3 -1/2 times, and a sixth coefficient multiplying circuit 42 for making the input signal f (t) -1/2 times. , Fifth coefficient multiplying circuit 41
, The output signal of the sixth coefficient multiplying circuit 42, and the output signal of the first delay circuit 2, and the output signal of the third adder 44 is halved. And a seventh coefficient multiplying circuit 43 for extracting the contour component in the current signal f (t).

The output signal of the contour extraction circuit 4 is input to a low-pass filter 5, where high-frequency components are removed. The output signal of the low-pass filter 5 is input to the multiplier 8 and multiplied by a contour correction coefficient k _H for changing the size of the contour component. The contour extraction circuit 4, the low-pass filter 5, and the multiplier 8 constitute a contour correction amount control circuit for controlling the contour correction amount.

The output signal of the contour correction amount control circuit is added by a fourth adder 9 to the output signal of the second adder 7 which is the output of the contour correction circuit, and is output as a second interpolation signal V _H2. . With such a configuration, the contour correction amount can be controlled by the contour correction coefficient k _H.

It should be noted that the interpolation processing circuit 1 of the present embodiment
Since the first delay circuit 2 is commonly used by the delay signal generation circuit and the contour correction circuit, an increase in circuit scale can be suppressed.

In FIG. 2, the first interpolation signal V _H1 and the second interpolation signal V _H2 output from the interpolation processing circuit 1 are
The signals g input to the time axis conversion circuit 20 and corresponding to the non-interlace by the time axis conversion circuit 20
(T).

The time axis conversion circuit 20 is constituted by, for example, a line memory or the like, and simultaneously writes the first interpolation signal V _H1 and the second interpolation signal V _H2, and outputs the first interpolation signal V _H1 and the second interpolation signal V _H2 at a clock speed twice as fast as the writing. One frame is formed by alternately reading out one interpolation signal V _H1 and second interpolation signal V _H2 .

In such a configuration, the interpolation signal generation circuit including the first delay circuit 2, the first adder 6, and the first coefficient multiplication circuit 10 is the same as the interpolation signal generation circuit shown in FIG. A first interpolation signal V _{H1 as} an output signal of the circuit is a signal of an average value of video signals of vertically adjacent scanning lines.

On the other hand, the first delay circuit 2, the second delay circuit 3, the second coefficient multiplier 11, the third coefficient multiplier 12, the fourth coefficient multiplier 13, and the second adder 7 Is a circuit that performs contour emphasis in the same manner as the contour correction circuit shown in FIG. Here, the value of k is a negative value,
This shows the strength of contour enhancement.

The contour extraction circuit 4 includes a third adder 4
4 is -1/2 times, 1 time and -1/2 times, the sum of the coefficients for those input signals becomes zero, and the signal of the difference of the video signal for each scanning line Output the components. The low-pass filter 5 removes high frequency components from the output signal of the contour extraction circuit 4 and can suppress vertical contour enhancement that occurs when displaying a signal having a large change. That is, it is possible to make the degradation in resolution that occurs when displaying oblique lines or the like inconspicuous.

For example, in the case of an NTSC video signal,
When displaying black and white vertical lines, the horizontal frequency is about 2 MHz,
When displaying black and white diagonal lines, the low-pass filter 5 has a characteristic of about 1 MHz.
It may be set to about z to 2 MHz.

The contour correction coefficient k_HIs zero, the first
Interpolation signal V_H1And the second interpolation signal V _H2Time-converted
The characteristic of vertical contour correction when the first coefficient multiplication circuit
11, third coefficient multiplying circuit 12, and fourth coefficient multiplying circuit 1
It is determined by a coefficient k of 3.

The transfer function in the vertical direction at this time is as follows.

H (z) = k + (1/2) z ⁻¹ + (1-2)
k) z ⁻² + (１ ／) z ⁻³ + kz ⁻⁴ Here, the characteristics of gain versus vertical frequency when k = −0.2 and contour correction coefficient k _H = 0 are shown in FIG. Become like When the circuit shown in FIG. 1 is actually used, the value of k is determined so that the screen display is easy to see.

Incidentally, the transfer function of the interpolation signal generating circuit for performing the double writing interpolation is represented by H (z) = 1 + z ^-1 and its frequency characteristic is as shown in FIG.

The transfer function of the interpolation signal generating circuit for performing the average value interpolation is represented by H (z) = 1 + {(1/2) + (1/2) z ^-1 }, and its frequency characteristic is shown in FIG. As shown in FIG.

When an NTSC video signal is displayed by interlacing, the vertical frequency (cycle / cycle) of one field is displayed.
The image height) is 525/4 (= 131.25).

As shown in FIG. 4, the vertical frequency 525/4
The gain of the interpolation signal generating circuit for performing the double writing interpolation in the above is about 0.7, and the gain of the interpolation signal generating circuit for performing the average value interpolation is 0.5 as shown in FIG.

On the other hand, as shown in FIG. 3, the gain at the vertical frequency 525/4 of the interpolation processing circuit 1 of the present invention is 0.9.
(K = −0.2, contour correction coefficient k _H = 0).

When the circuit shown in FIG. 1 is actually used, the frequency characteristics vary depending on the value of k. However, in the interpolation processing circuit 1 of the present invention, the vertical frequency 525/4
Since the peaking is performed around the vicinity, the vertical frequency characteristic of 525/4 or less is improved. The vertical frequency characteristic of the contour extraction circuit 4 is as shown in FIG. 6, and the center of the characteristic peaking exists at a frequency of 525/4 or more.

Therefore, an appropriate contour correction amount can be obtained according to the vertical frequency component and the horizontal frequency component, so that good contour correction can be performed, and deterioration in resolution after the interpolation processing is reduced.

Also, the first interpolation signal V _H1 output from the interpolation signal generation circuit and the second interpolation signal V _H1 output from the fourth adder
When an image is formed by performing time-axis conversion using the interpolation signal V _H2 , an image with less discomfort can be obtained.

[0069]

Since the present invention is configured as described above, the following effects can be obtained.

An interpolation signal generating circuit for outputting, as a first interpolation signal, an average value of a current signal, which is a video signal corresponding to interlace, and a delay signal delayed by one horizontal scanning period from the current signal; Is delayed by one horizontal scanning period.
And a second delay circuit for delaying the output signal of the first delay circuit by one horizontal scanning period, the current signal, the output signal of the first delay circuit, and the output of the second delay circuit. A contour correction circuit for enhancing a vertical contour of an image by multiplying each signal by a predetermined coefficient and adding the current signal, a current signal, an output signal of a first delay circuit, and an output signal of a second delay circuit A contour correction amount control circuit that extracts a vertical contour component of an image from the image and outputs the size of the contour component so as to be changeable, an output signal of the contour correction circuit and an output signal of the contour correction amount control circuit are added, and By providing an adder for outputting as an interpolation signal of 2, an appropriate amount of contour correction can be obtained according to the vertical frequency component and the horizontal frequency component, so that good contour correction can be performed. Of the image resolution is reduced.

The circuit scale can be reduced by obtaining the delay signal used in the interpolation signal generation circuit from the output signal of the first delay circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an interpolation processing circuit according to the present invention.

FIG. 2 is a block diagram showing a circuit configuration in a case where an interlaced video signal is converted to a non-interlaced video signal using the interpolation processing circuit shown in FIG. 1;

FIG. 3 is a frequency characteristic diagram illustrating a relationship between a gain and a vertical frequency of the interpolation processing circuit illustrated in FIG. 1;

FIG. 4 is a frequency characteristic diagram illustrating a relationship between a gain and a vertical frequency of an interpolation signal generation circuit that performs twice-write interpolation;

FIG. 5 is a frequency characteristic diagram illustrating a relationship between a gain and a vertical frequency of an interpolation signal generation circuit that performs average value interpolation.

FIG. 6 is a frequency characteristic diagram showing a relationship between gain and vertical frequency of the contour extraction circuit shown in FIG. 1;

FIG. 7 is a block diagram illustrating a configuration of an interpolation signal generation circuit for performing average value interpolation.

FIG. 8 is a block diagram illustrating a configuration of an interpolation signal generation circuit that performs twice-write interpolation.

FIG. 9 is a block diagram showing a conventional circuit configuration for converting a video signal compatible with interlace into a video signal compatible with non-interlace.

FIG. 10 is a diagram showing a procedure for converting an interlaced video signal to a non-interlaced video signal.

FIG. 11 is a diagram showing an example of a display image in which the luminance has been changed across a diagonal line.

12 is an enlarged view of the vicinity of the boundary of the display image shown in FIG. 11, wherein FIG. 12 (a) is an original image, FIG. 12 (b) is an image subjected to average value interpolation, and FIG. Is an image on which writing and interpolation have been performed twice.

FIG. 13 is a block diagram illustrating a configuration of a contour correction circuit that performs contour emphasis.

14 is a frequency characteristic diagram illustrating an impulse response when a signal having an amplitude of 1 is input to the contour correction circuit illustrated in FIG. 13;

[Explanation of symbols]

 Reference Signs List 1 interpolation processing circuit 2 first delay circuit 3 second delay circuit 4 contour extraction circuit 5 low-pass filter 6 first adder 7 second adder 8 multiplier 9 fourth adder 10 first coefficient multiplication Circuit 11 Second coefficient multiplier circuit 12 Third coefficient multiplier circuit 13 Fourth coefficient multiplier circuit 20 Time axis conversion circuit 41 Fifth coefficient multiplier circuit 42 Sixth coefficient multiplier circuit 43 Seventh coefficient multiplier circuit 44 Adder of 3

Claims (2)

[Claims] An interpolation process for outputting an interpolation signal for performing a scan line interpolation of a video signal corresponding to the interlace in order to convert a video signal corresponding to the interlace into a video signal corresponding to the non-interlace. A circuit, the current signal being a video signal corresponding to the interlace,
An interpolation signal generation circuit that outputs an average value of a delay signal delayed by one horizontal scanning period from the current signal as a first interpolation signal; and a first delay circuit that delays the current signal by one horizontal scanning period. And a second delay circuit for delaying the output signal of the first delay circuit by one horizontal scanning period.
A contour correction circuit for enhancing a vertical contour of an image by multiplying an output signal of the first delay circuit and an output signal of the second delay circuit by a predetermined coefficient, and adding the multiplied signals; Contour correction amount control for extracting a vertical contour component of an image from a signal, an output signal of the first delay circuit, and an output signal of the second delay circuit, and outputting the image so that the size of the contour component can be changed; An interpolation processing circuit comprising: a circuit; and an adder that adds an output signal of the contour correction circuit and an output signal of the contour correction amount control circuit and outputs the result as a second interpolation signal. 2. The interpolation processing circuit according to claim 1, wherein a delay signal used in the interpolation signal generation circuit is obtained from an output signal of the first delay circuit.