JPH1141241A - Atm switch and cell output priority control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently perform the priority control of output cells at an ATM switch and further to guarantee the output bands of respective classes. SOLUTION: The cells are held in a cell buffer 2 in the order of input for each output port and each class. A priority control register 13 holds plural kinds of priority for the respective classes. As for the class having the cell to be held in the cell buffer 2 and high in priority, a priority change/cell read control circuit 6 outputs the first inputted cell from the output port according to the selected priority of the priority control register 13. An output queue counter/round robin table control part 12 counts the output cells in each cycle for each class of the port and when the count value gets equal with a set value, the switching of the round robin table 15 is controlled so as to select the priority, which does not include the class of the output port, from the priority control register.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for performing output control by assigning priorities to cells output from a switch in an ATM switch.

[0002]

2. Description of the Related Art A conventional cell output priority control method in an ATM switch will be described with reference to FIG.

In FIG. 16, an ATM switch includes a cell multiplexing unit 100 for multiplexing cells, a cell buffer 101 for holding cells, a cell separating unit 102 for separating cells for each output port, a cell routing destination and a A routing / priority class identification circuit 103 for identifying a class indicating a defined priority, a cell write control circuit 104 for controlling writing to the cell buffer 101, and a cell reading control circuit for controlling reading from the cell buffer 101 105, and a management table 106 for managing a write address and a read address to the cell buffer. This ATM switch is an output buffer type switch system that outputs cells input from N input ports to N output ports. The class is
Priorities are determined in advance, and cells of higher classes are preferentially output, and when cells of lower classes are output, cells of higher classes than that class are not held. In such a case, the control is performed by a strict priority control method for outputting cells of the class.

[0004] A cell buffer 101 is divided into classes for each output port and holds cells in the order of input.
The configuration of a FIFO buffer that outputs data in the order of earlier input is adopted. Further, the management table 106 has, for each output port, areas for the number of classes of output priority (four classes from A to D in the example shown in FIG. 16). The write address and read address of the cell are held. The address of the cell buffer 101 is managed by a cell write control circuit 104 and a cell read control circuit 105.

In a cell write operation, a routing destination / priority class identification circuit 103 identifies a cell input to an input port as an output port and a priority class. Thereafter, the cell write control circuit 104 refers to the management table 106, obtains a write address to the cell buffer 101 from the corresponding class area of the identified corresponding port, designates a write address, and specifies the write address.
Write cell to Also, the cell write control circuit 104
+1 (addition) the write address value of the management table
By doing so, the next write address is specified in the management table. By repeating the above operation at each cell write timing, a write operation to the cell buffer 101 is performed.

Next, when the cell read control circuit 105 reads a cell, it refers to the management table for each port, and holds the class in the cell buffer 101 for all classes from the difference between the write address and the read address. The number of cells is determined for each class, and the cell input first is read by indicating the read address of the class having the highest priority and having the cell to be held. At the time of reading, the cell read control circuit 105 increments the read address of the relevant port and the relevant class in the management table by +1.
By performing (addition), the next read address is specified in the management table. The same process is performed for the next port. By performing the above processing, cells are output in accordance with the priority order.

[0007]

In the above-mentioned prior art method of realizing priority control of an output cell, the cell buffer 101 is used.
At the time of reading, it is necessary to access the areas of all the classes in the management table to read the write address and the read address, and determine the number of cells to be held in the cell buffer 101 from the difference between the write address and the read address. You need to ask for each class. Therefore, the frequency of accessing the management table increases, and the number of classifications is limited due to the processing time.

Further, since the priority control method is the complete priority control and the priority is fixed to one certain pattern, there is a possibility that only the class having the higher priority is output when reading out the cell buffer 101. is there. Also,
The output band of each class cannot be set to a fixed band. For this reason, cells may be output beyond the desired band.

An object of the present invention is to enable efficient priority control of output cells and to classify (priority)
An object of the present invention is to provide an ATM switch and a cell output priority control method thereof, which do not increase the processing time even when the number increases.

It is another object of the present invention to provide an ATM switch capable of setting an output band of each class for each output port and guaranteeing the output band, and a cell output priority control method therefor. .

[0011]

According to the present invention, a cell is input, and the cell is output from an output port corresponding to a destination according to a predetermined class indicating the type of service added to the input cell. An ATM switch for storing the cells in the order of input for each of the output ports and for each of the classes; and the cell holding means for each of the output ports and for each of the classes. Management means for managing whether or not there is a cell held in the class, priority holding means for holding a plurality of priorities of the class, and selecting means for selecting any one priority from the priority holding means And for each of the output ports,
In the priority order selected by the selection unit, a higher class, and the class that is managed by the management unit as having a cell held in the cell holding unit, the cell input first, Read control means for outputting the cell held in the holding means from the port, the selecting means switches the type to be selected at every predetermined time, and Monitor the output band of the cell of the class, and when the monitored output band becomes the set value of the output band of the class of the output port, the priority order not including the class for the output port, Select from priority holding means.

More specifically, a plurality of input ports, a plurality of output ports, and an output port corresponding to a destination added to a cell input from the plurality of input ports,
An identification circuit for identifying a class indicating the type of service added to the cell, a cell buffer for holding input cells, and input cells for each output port, and for each class A write control circuit for instructing a write address of the cell buffer in order to hold the cell buffer in the order in which the cells are input; and a higher-priority class for each of the output ports. If there is a cell that has been written, for the class, the first input, the cell held in the cell buffer, to output from the port, a read control circuit that indicates a read address, the write address and the write address A management table that holds a read address for each of the output ports and for each of the classes; A priority control register that retains the priority of the species, and a selection circuit that selects any one of the priorities from the priority control register, wherein the selection circuit performs the selection at predetermined time intervals. The type is switched, and the output band of the cell of each class for each output port is monitored. When the monitored output band becomes the set value of the output band of the class of the output port, the output port Can be selected from the priority control register.

According to the present invention, a plurality of services (quality)
The cells in the cell buffer divided for each class can be efficiently read from those having the highest priority. At the time of cell read processing, the class to be read can be easily recognized, and the access to the management table storing the cell read address is limited to the area corresponding to the class to be output. The increase does not affect the processing time.

According to the present invention, the output bandwidth of the cell of each class for each output port is monitored, and when the monitored output bandwidth becomes the set value of the output bandwidth of the class of the output port. Since the priority of the output port that does not include the class is selected from the priority holding means, the output bandwidth can be guaranteed. Also, by setting a predetermined time for switching the type of priority to be selected, band division can be realized, and output of only one class can be avoided.

[0015]

FIG. 1 shows a first embodiment of the present invention.
This will be described with reference to FIG.

In FIG. 11, the ATM switch includes a cell multiplexing unit 1 for multiplexing cells, a cell buffer 2 for holding cells, and a cell separating unit 3 for separating cells for each output port.
A routing destination / priority class identification circuit 4 for identifying a routing destination and a priority class of a cell; a cell write control circuit 5 for controlling writing to the cell buffer 2;
A cell read control circuit 90 for controlling reading from the cell buffer 2, four priority control registers 92 (a) to (d) for holding the priority of output, a round robin table 91, and four priority controls A priority control register selection unit 93 for selecting which priority control register to use among the registers, and for each output port,
A port management table 8 indicating whether or not there is a cell held in the cell buffer 2 for each class by a flag (hereinafter referred to as a queue flag), and a write address and a read address of the cell buffer 2 for each output port. And a queue management table 9 held for each class. The ATM switch according to the embodiment of the present invention includes:
This is an output buffer type switch system that outputs cells input from N input ports to N output ports. The priority of a class is determined by a priority control register (in this embodiment, a priority sequence is simply referred to as a priority), cells of a class having a higher priority are output with priority, and cells of a lower class are output with priority. When a cell is output, control is performed by a strict priority control method in which a cell of a class higher than the class is output when the cell is not held. Further, by using the round robin table to periodically circulate the priority control registers used among the plurality of types of priority control registers, the bias of the cell output class due to the full priority control is eliminated, and band division is realized.

In this embodiment, an example is given in which the number of quality classes is four, from class A to class D. FIG. 2 shows the configuration of the port management table 8.

As shown in FIG. 2, the port management table 8 stores queue flag information indicating whether or not there is a queue (waiting state) of cells classified into four classes for each output port. Stores bit by bit. For this reason, the capacity of the entire table has a capacity of 4 bits × n (the number of ports) bits. The queue flag is stored in cell buffer 2
Is set to 1 when there is a cell held in the cell buffer (when there is a queue), and is reset to 0 when there is no cell held in the cell buffer 2 (when there is no queue).

As shown in FIG. 11, the queue management table 9 has an area for each class (class A to class D) for each port, and the cell buffer 2 of each class for each port. Write position information (write address), read position information (read address), and a queue value (the number of cells held in the cell buffer 2) which is a value obtained by subtracting the read address value from the write address value.
Are stored. The total capacity of the table is 4 (number of classes)
Bits × n (number of ports) bits × (number of bits of cell write address + number of bits of read address + number of bits of queue value).

The cell buffer 2 has a configuration of a FIFO buffer that is divided into classes for each output port, holds the data in the order of input, and outputs the data in the order of input. The address of the cell buffer 2 is managed by the cell write control circuit 5 and the cell read control circuit 90, and the address value is indicated so that a FIFO buffer is provided for each output port and for each class. Is a sequential number and the address
It shall be stored in order from 1.

Routing destination / priority class identification circuit 4
Analyzes the cell header information added to the cell and identifies the output port corresponding to the destination included in the cell header information and the class indicating the output priority.

The cell write control circuit 5 inputs the input cell by referring to the queue management table 9 in accordance with the output port and class of the cell identified by the routing destination / priority class identification circuit 4. In this order, the write address of the cell buffer 2 is designated, and the input cell is held in the cell buffer 2. Further, the cell write control circuit 5 sets the queue flag of the port management table 8 of the corresponding class of the output port of the written cell, and sets the write address of the queue management table 9 of the corresponding class of the output port of the written cell. +1 (addition) to indicate the next write address. Further, the queue value of the queue management table 9 of the corresponding class of the output port of the written cell is incremented by +1 (addition).

The priority control register 92 holds the priority of each class. For example, classes A, B,
When C and D are present, the priorities are stored in the order of A, B, C, and D in descending order of priority. The priority control register 92 is rewritable,
Can indicate the priority of the class, and the priority control register 92 can hold the priority.

The priority control register selector 93 is a selector for selecting any one of the four priority control registers (a) to (d). The round robin table 91 is a selection signal generation unit that generates a selection signal indicating which of the priority control registers (a) to (d) is selected by the priority control register selection unit 93. (A) to (d) of the round robin table 15 indicate priority control registers (a) to (d), respectively, and (a) → (b) →
(C) → (d)... → (a) → (b). The cell read control circuit 90 refers to the priority control register during the cell buffer read processing, and reads cells according to the priority. If the priority of the priority control register is 1
If it is fixed to one pattern, there is a possibility that only a cell of a class having a higher priority is output for each read request. On the other hand, in the first embodiment, the cell read control circuit 90 The priority control register to be searched can be circulated. In this case, the selection signal (a),
Any of the four priority control registers (a) to (d) can be used by any of (b), (c), and (d).

For example, when the value of the round robin table 91 is "(a)" at a certain read timing, the priority control register searched by the cell read control circuit 90 is the priority control register (a). The priority order of the read cells is in the order of class A, class B, class C, and class D. If the value of the round robin table 91 is “(C)” at another read timing, the cell read control circuit 90
Is a priority control register (C), and the priority of the read cell is class C,
The order is class D, class A, and class B. As a result, it is possible to avoid a biased readout of cells of a class having a higher priority, to provide an output opportunity to each class, and to perform band division. The round robin table can be changed, for example, for each cell output for all ports.

The cell read control circuit 90 sequentially stores the port management table 8 in the port management table 8 in order from the class having the highest priority, which is selected by the priority control register selector 93 and held by the priority control register 92, for each output port. By referring to the queue flag, the cell input earlier than the class corresponding to the queue flag indicating that there is a cell held in the cell buffer 2 is designated by referring to the queue management table 9 to specify the read address. Output from the output port. Further, the read address held by the queue management table 9 is incremented by +1 (added) so as to indicate the read address of the cell input next to the output cell. Further, the queue value in the queue management table 9 of the class of the output port that caused the output is subtracted by -1 (subtraction), and when the queue value is 0, that is,
If there is no cell held in the cell buffer 2, the queue flag of the port management table 8 of the class of the output port that has been output is reset.

Next, referring to FIG.
The operation of writing to and reading from the memory will be described.

In FIG. 11, cells input from each input port are multiplexed by the cell multiplexing unit 1 on a cell basis.
The routing / priority class identification circuit 4 analyzes the cell header information added to the cell. The cell header information includes the identification information of the output destination port and the identification information of the class of the cell. The routing destination / priority class identification circuit 4 recognizes the output port of the cell included in the cell header information, identifies the class indicating the priority of the output of the input cell, and outputs the identification result to the cell write control circuit 5. I do.

After the output port and the priority class are identified by the routing destination / priority class identification circuit 4, the cell write control circuit 5 sets a queue flag in the corresponding port and the corresponding class area of the port management table ( The logical value is set to “1”, the write address to the cell buffer 2 is obtained by referring to the corresponding class area of the corresponding port in the queue management table 9, and the write address is designated, so that the cell information is stored in the cell buffer 2. Write. In addition, the cell write control circuit 5 instructs to indicate the next write address by adding (adding) the write address of the queue management table 9 of the corresponding class of the output port of the written cell to +1. Further, in the queue management table 9 of the corresponding class of the output port of the written cell,
+1 (addition) the queue value.

The above operation is repeated at each cell write timing to perform a write operation to the cell buffer 2.

When reading a cell, the cell buffer 2
The timing for reading out cells from the ports periodically arrives from port 1 to port N, respectively. First, the cell read control circuit 90 searches the port management table 8 and recognizes each queue flag of a predetermined port from class A to class D. Next, the priority control registers 92 in which the priorities of the classes A to D are set in advance are searched to recognize the read priority of the cells. Next, the cell read control circuit 90 obtains a read address from the queue management table 9 for the class of the logic “1” of the corresponding class of the corresponding output port in the port management table according to the priority order, and obtains the read address. By instructing, cell information is read from the cell buffer 2. Further, the read address held by the queue management table 9 is incremented by +1 (added) so as to indicate the read address of the cell input next to the output cell. Further, the queue value in the queue management table 9 of the class of the output port that caused the output is set to -1.
When the queue value after the subtraction is 0, the queue flag of the port management table 8 of the class of the output port that has been output is reset.

Thus, the cell read control circuit 9
0 indicates a cell read address from the queue management table 9 in the order of priority class for the class whose queue flag is "1", and sequentially designates a read address in the cell buffer 2 where the cell is stored; The cell is read from the cell buffer 2. The cell separation unit 3 separates the cells read from the cell buffer memory for each output port.

In a read operation, when one cell of a certain class is output from a certain port, the process proceeds to the next port, and the same processing is performed. The processing from port 1 to port N is repeated.

Next, the detailed operation of the cell read control circuit 90 will be described with reference to FIGS. FIG. 13 shows a cell buffer read flow in the cell read control circuit 90. FIG. 12 shows an example of a queue flag in the port management table. As shown in FIG. 12A, the queue flag of each class of the output port 1 is set as follows.
The class A is "1", the class B is "0", the class C is "0", the class D is "1", and the value of the round robin table 91 is "(a)", that is, the priority control register. The priority control register selected by the selection unit 93 is (a), and the priority information set in the priority control register (a) is stored in the order of classes A, B, C, and D (class A is the priority order). Is the highest and class D has the lowest priority) with reference to FIG.

In FIG. 13, first, the cell read control circuit searches the area of port 1 in the port management table 8 (step 40), and recognizes information of A = 1, B = 0, C = 0, D = 1. (Step 41). Next, the cell read control circuit searches the priority control register 92 (a) and recognizes that the priority of each class is in the order of classes A, B, C, and D (step 42). Step 4
The order of subsequent processing in class units is determined by 1 and 42. As shown in FIG. 13, in this case, an actual read operation from class A to the cell buffer 2 is performed (step 45). In this example, in the class A, since the queue flag is already “1”, in the queue flag state determination (step 95), the process proceeds to the branch 47 after the determination, and
The read address of the cell buffer 2 is obtained by referring to the class A area of the port 1 in the queue management table 9, and the read address is indicated at the read timing of the cell buffer 2, whereby the cell information is read from the cell buffer 2. Output. Next, the cell read control circuit 90 adds 1 to the read address of the class A cell buffer 2 to obtain the next read address (step 48). Since the queue value in the port management table is a value obtained by subtracting the read address from the write address, the cell read control circuit 90 reduces the class A queue value of port 1 by -1 (subtraction).
(Step 49). Next, the cell read control circuit 9
If the queue value is 0, it is determined whether the queue value is 0 or not (step 50). If the queue value is "0", it is determined that there is no cell to be output.
The queue flag of the class A area is set to "0" (step 51). If it is other than "0", the queue flag is already "1", and the process proceeds to the next process (branch 52).

Class A read from cell buffer 2
Are output to the output port 1 through the cell separation unit 3. When a class A cell is output to port 1,
Next, the process proceeds to the cell reading process of port 2 (branch 53).
Thereafter, read processing from port 2 to port n is performed in the same manner. After the reading process of the port n, the process returns to the port 1, and the processes from the port 1 to the port n are repeatedly performed.

Next, when returning to the read processing of the port 1 again, as shown in FIG. 12B, the queue flags of each class of the output port 1 and the class A “0”, class B is “0”, class C is “0”, class D is “1”, and the value of the round robin table 91 is (b), that is, the priority control register selecting unit 93 selects Is switched to (b), and the priority information set in the priority control register is changed to the order of classes B, C, D, and A (class B has the highest priority, and class A has the highest priority). With reference to FIG. 14, an example in which a cell of class D is read out (when the priority is the lowest) will be described.

The cell read control circuit 90 searches the port 1 area of the port management table 8 in the same manner as described above (step 40), and recognizes information of A = 0, B = 0, C = 0, and D = 1. (Step 41). Next, the cell read control circuit 90 searches the priority control register 92 (b) and recognizes that the priority of each class is the order of the classes B, C, D, and A (step 42). Next, the processing shifts to the class B cell reading processing 55 from the priority order, and since the queue flag of the class B cell is “0”,
In the queue flag state determination (step 95), the class B read operation is not performed through the branch 54. That is, when there is no cell to be read, the process shifts to the process of the cell of the next priority class (class C) without accessing the queue management table 9.

Next, in the read operation step 56, similarly for the class C cell having the second priority, the queue flag of the class C cell is "0" similarly to class B, so that the queue flag state determination is performed. After the judgment in,
The process moves to the process (step 57) for the cell of the next priority class (class D). Since the queue flag state of the class D cell is "1", the process proceeds to the reading process of the cell buffer 2 in the queue flag state determination (step 95), and refers to the class D area of port 1 in the queue management table 9. Thus, the read address of the class D cell buffer of the cell buffer 2 is obtained, and at the read timing of the cell buffer, the cell buffer 2 outputs cell information by designating the read address. Next, the cell read control circuit 90 adds 1 to the read address of the class D cell buffer 2 to obtain
This is the next read address. (Step 48). Further, since the queue value in the port management table 9 is obtained by subtracting the read address from the write address, the cell read control circuit 90 subtracts -1 (subtracts) the queue value of the class D of the port 1 (step). 49).
Next, the cell read control circuit 90 determines whether the value of the queue is 0 or not (step 5).
0), if "0", it is determined that there is no cell to output,
The queue flag of the class D area of port 1 in the port management table 8 is set to "0" (step 51). If it is other than "0", the queue flag is already "1", and the process proceeds to the next process (branch 52).

The class D cells read from the cell buffer are output to the output port 1 via the cell separation unit 3. After that, the process goes to the next port 2 reading process via the branch 53.

Next, when returning to the read processing of the port 1 again, the queue flags of the respective classes of the output port 1 are set as shown in FIG. “0”, class B is “1”, class C is “0”, class D is “0”, and the value of the round robin table 91 is (c), that is, the priority control register selection unit 93 selects The priority control register is switched to (c), and the priority information set in the priority control register is changed to the order of classes C, D, A, and B (class C has the highest priority and class B has the highest priority). An example in which a cell of class B is read when the priority is the lowest) will be described with reference to FIG.

The cell read control circuit 90 searches the port 1 area of the port management table 8 in the same manner as described above (step 40), and recognizes information of A = 0, B = 1, C = 0, and D = 0. (Step 41). Next, the cell read control circuit 90 searches the priority control register 92 (c) and recognizes that the priority of each class is the order of the classes C, D, A, and B (step 42). Next, the process proceeds to the class C cell reading process 56 from the priority order, and since the queue flag of the class C cell is “0”,
In the queue flag state determination (step 95), the read operation is not performed through the branch 54. Class D and A cells are the same as class C cells.
Since the queue flag is “0”, no cell is output, and the process proceeds to the next class B cell reading process.

The queue flag state of the class B cell is
Since it is “1”, the queue flag state determination (step 9
In 5), the process proceeds to the cell buffer read processing, and the read address of the class B cell buffer of the cell buffer 2 is obtained by referring to the class B area of the port 1 in the queue management table 9 and the read timing of the cell buffer. The cell buffer 2 outputs cell information by designating the read address. Next,
The cell read control circuit 90 adds one to the read address of the class B cell buffer 2 to make it the next read address (step 48). Further, the queue value in the port management table 9 is obtained by subtracting the read address from the write address, which is the queue value.
The cell read control circuit 90 decrements the class B queue value of port 1 by -1 (step 49). Next, the cell read control circuit 90 determines whether the value of the queue is 0 or not (step 50), and “0”.
If so, it is determined that there is no cell to output, and the queue flag of the class B area of port 1 in the port management table 8 is set to "0" (step 51). If it is other than "0", the queue flag is already "1", and the process proceeds to the next process (branch 52).

The class B cells read from the cell buffer are output to the output port 1 via the cell separation unit 3.

By performing the processing as described above, it is possible to output a cell of a higher priority class for each port. According to the mode of the first embodiment, it is possible to recognize the class in which the cell to be output exists by judging the state of the queue flag. Conventionally, when a class to be output is determined, it is necessary to determine whether or not there is a queue and to determine a class to be output by referring to all classes in a queue management table holding an address (a few bits of information). However, according to the present embodiment, it is possible to output a cell of a class having a higher priority by referring to the queue flag (1-bit information) of each class. In addition, since access to the queue management table storing the cell read position address is required only in the area corresponding to the class to be output, the processing time is not affected even if the number of classes is increased. That is, the number of accesses to the queue management table and the processing time thereof can be reduced, so that the number of classifications can be easily increased. For this reason, the number of classifications can be expected to be ten and several times larger than in the past.

According to the first embodiment,
By periodically circulating the priority control registers to be used among a plurality of types of priority control registers, it is possible to eliminate the bias of the cell output class due to the full priority control and realize band division.

Further, by using the priority control register 92 as a microcomputer interface, a rewritable mechanism is provided.
Arbitrary change of the priority order is possible.

The time during which the priority control registers are selected by the output of the selection signal of the round robin table may be the same for all the priority control registers, or may be different for each priority control register. You may do so. For example, the priority control register (a) has 20 cell outputs, the priority control registers (b) and (c) have 10 cell outputs, and the priority control register (d) has 20 cell outputs. It can be different, such as 5 cells.

Next, a second embodiment will be described.

In the band division method of the first embodiment, the minimum transmission band can be guaranteed, but no consideration is given to fixing the output band for each class. For example, when cells are always stored in buffers of four quality classes, the bandwidth of the output port can be accurately divided. However, when one or more classes of buffers are temporarily emptied, the band division is performed. It is not fixed. In addition, since the band division is determined by the ratio of the priority control registers set on the round robin table, if the output band of each class is to be set finely, the round robin table becomes large and a large amount of information storage memory is required. Becomes Further, in order to divide the bandwidth at a different rate for each output port, a round robin table is required for the number of output ports, and the memory capacity needs to be increased. Also, when one class, for example, class A, is to be output with the highest priority,
The first priority of all priority control registers will be class A, in which case the other classes cannot guarantee even the lowest transmission bandwidth.

The second embodiment aims at correcting the above problem. A second embodiment will be described with reference to FIG.

In FIG. 1, the ATM switch includes a cell multiplexing unit 1 for multiplexing cells, a cell buffer 2 for holding cells, and a cell separating unit 3 for separating cells for each output port.
A routing destination / priority class identification circuit 4 for identifying a routing destination and a priority class of a cell, a cell write control circuit 5 for controlling writing to the cell buffer 2, and a priority change / cell for controlling reading from the cell buffer 2 A read control circuit 6 and 32 priority control registers 13 (1) to 13 (32) for holding the output priority;
15 round robin tables 15 (a) to 15 (o), a priority control register selection unit 14 for selecting which priority control register among 32 priority control registers to use, and 15 rounds A round robin table selecting unit 16 for selecting which round robin table to use from among the robin tables, and a signal for counting the number of output cells and selecting the round robin table so as not to exceed the set output band of each class. An output queue counter / round robin table control unit 12 for creating
For each output port, a port management table 8 indicating whether or not there is a cell held in the cell buffer 2 for each class by a queue flag, and a write address and a read address of the cell buffer 2 for each output port. A queue management table 9 for each class, and a full priority indication register 10 for holding full priority indication information.
And a cell insertion instruction register 11 for an empty slot that holds cell insertion instruction information for an empty slot. The ATM switch according to the second embodiment of the present invention
This is an output buffer type switch system that outputs cells input from N input ports to N output ports.
Each class is prioritized by a priority control register, and for cells of the higher priority class,
When priority is given to output cells of a lower class, control is performed by a strict priority control method of outputting cells of the class when cells of a class higher than the class are not held. . Further, by rounding the priority control registers used among a plurality of types of priority control registers periodically by the round robin table, the bias of the cell output class due to the full priority control is eliminated, and band division is realized. By changing a plurality of round robin tables, control can be performed so as not to exceed the output bandwidth set for each port and each class. Further, a full priority instruction indicating the order of use of each class for each port in preference to the priority indicated by the priority order control register 13, and when the output bandwidth of a certain class exceeds the other class, When inserting an empty cell without a queue, it is possible to issue an empty cell insertion instruction instructing to permit the output of a cell of a class whose output band has exceeded. In the present embodiment, an example in which the number of quality classes is four from class A to class D will be described.

The port management table 8, queue management table 9, cell buffer 2, routing destination / priority class identification circuit 4, and cell write control circuit 5 have the same configuration as that described in the first embodiment. Performs the same operation.

The priority control register 13 holds the priority of each class. For example, classes A, B,
There are C and D, and A → B → C →
In the case of D, A, B, C,
D. If the output band of class D is not less than the set value and the class D is not output, the A, B, C
And the fourth is empty. In the second embodiment, the output bandwidth of each class is managed, and the priority is changed for each output bandwidth of each class. In the second embodiment, as shown in FIG. 3, 32 priority control registers are prepared, 32 types of priorities are held, and the remaining except for the class in which the number of output cells exceeds the set band is excluded. Class division enables band division. For example, if the number of output cells of class A exceeds the set bandwidth,
By selecting the priority control registers of (5), (6) and (7), it is possible to arbitrarily divide the band between the classes B, C and D. Also, the priority control register 13
Can be rewritten, the instruction unit 18 can indicate the priority of the class, and the priority control register 13 can hold the priority.

The priority control register selector 14 has 32
The selection unit selects one of the priority control registers (1) to (32). The round robin table 15 is a selection signal generation unit that generates a selection signal indicating which of the priority control registers (1) to (32) is to be selected by the priority control register selection unit 14. Table 1 shows the contents of the round robin table.

[0056]

[Table 1]

In FIG. 3 and Table 1, in the case of the round robin table 15 (a), (1) to (4) indicate priority control registers (1) to (4), respectively, and (1) → (2)
→ (3) → (4)... → (1) → (2)... In this embodiment, the round robin table 15 is output every cell output from all ports.
(A) to (o) The selection of all priority control registers is switched. In addition, the round robin table selecting unit 16 includes 15 round robin tables (a) to
A selection unit for selecting one of (o). The priority change / cell read control circuit 6 refers to the priority control register 13 at the time of cell buffer read processing, and reads cells in accordance with the priority, and the priority control register has a priority. If the pattern is fixed to one pattern, there is a possibility that only cells of a class having a higher priority are output for each read request. On the other hand, in the second embodiment, priority change / cell The priority control register searched by the read control circuit 6 can be circulated by the round robin table 15. Round robin table selector 16
However, when the round robin table 15 (a) is selected, four priority control registers (1) to (4) are selected by one of the selection signals (1), (2), (3), and (4).
Can be used.

For example, if the value of the round robin table 15 (a) is "(1)" at a certain read timing, the priority control register searched by the priority change / cell read control circuit 6 stores the priority. This is the control register (1), and the priority of the read cells is in the order of class A, class B, class C, and class D. At another read timing, the value of the round robin table 15 (a) is "(3 ) ", The priority control register searched by the priority change / cell read control circuit 6 is the priority control register (3), and the priority of the read cells is class C, class D,
Class A and class B are in order. As a result, it is possible to avoid a biased readout of cells of a class having a higher priority, to provide an output opportunity to each class, and to perform band division.

The output queue counter / round robin table control unit 12 counts the number of output cells for each class of each port, and selects a round robin table 15 (a) to (o) according to the number of output cells. Create Figure 4
2 shows the configuration of the output queue counter / round robin table control unit 12. The operation of the output queue counter / round robin table control unit 12 will be described below with reference to FIG.

In FIG. 4, the output queue counter / round robin table control unit 12 includes a band setting register 20 for holding the band of each class for each port, an output cell number counter 23 for counting the number of output cells, and a set band. , A priority control cycle register 401 for holding a priority control cycle instructed by the instruction unit 400, a cycle counter 402 for counting clock signals of cells, and priority control. Priority control cycle held in cycle register 401 and cycle counter 4
And a comparator 403 that compares the value of H.02 and outputs a reset signal to the output cell number counter when they match. Here, the priority control cycle is a cycle for resetting the output cell number counter, and is a monitoring cycle for transmitting cells according to the priority order. For example, if the priority control cycle is 1
Assuming two cell times, the output cell number counter of each class is reset for every output of 12 cells (including empty cells). If the priority control cycle is long, for example, 120 cells, the output band of each class can be set more finely, but on the other hand, depending on the state of cell accumulation in the cell buffer of each class, priority There is a possibility that cells of a specific class are continuously output within the control cycle. The priority control cycle is instructed by the user from the instructing unit 400.

The band setting register 20 holds data indicating the output band of each class in each port. The information actually held is the number of cells that can be output within the priority control cycle. For example, if the output bandwidth of the port is 100 Mbit /
s, the output bandwidths of the four classes A, B, C, and D are all 25 Mbit / s. If the priority control cycle is 12 cell times, the set value in the register of each class is 12
Cell × 25M / 100M = 3 cells. Also, by instructing the output band from the instruction unit 22, the output band of each class can be set in the band setting register 20.

The output cell number counter 23 is a counter for counting the number of output cells of each port for each class. The output port and the class information are obtained from the priority change / cell read control circuit 6, and the number of output cells is counted for each output port and for each class. At the time of cell output, the output cell number counter 23 selects a port by the PORT selection signal 1 indicating the port number of the output cell instructed by the priority change / cell read control circuit 6, and changes the priority / cell read. Upon receiving an enable signal corresponding to the class output from the control circuit 6 at the time of cell output, the control circuit 6 counts up the class corresponding to the enable signal. The count value is reset by a reset signal output from the comparator 403 every priority control cycle. The comparator 403 compares the value of the cycle counter 402 that counts the clock signal of the cell with the value of the priority control cycle stored in the priority control cycle register 401, and outputs a reset signal to the output cell number counter if they match. I do.

Priority change / cell read control circuit 6
Enable the signal line corresponding to the output class at the time of cell output, and negate the other signal lines.

The band excess determining circuit 21 compares the set value of the band setting register 20 with the count value of the output cell number counter 23 for each class at the cell read timing of each port (instruction timing of the PORT selection signal 2). A round robin table selection signal is generated so as to select a round robin table that does not include a class whose count value exceeds a set value. PORT selection signal 2 is P
This is a signal obtained by delaying the ORT selection signal 1, and indicates the port number of the output cell. For example, with reference to FIG. 3, when the class A reaches the set value, the round robin table (b) not including the class A is selected.
Since the round robin table (b) circulates only the priority control registers (5), (6), and (7), the class A cells are not read. When the number of the round robin tables is 15, the round robin table selection signal is represented by 4 bits in the present embodiment, includes a signal line corresponding to each class, and, when the output band reaches a set value, The signal line corresponding to the class is enabled. As described above, the band excess determination circuit 21 monitors the output band of each port and each class, and can perform band control to select a round robin table so that the output band falls within the set value.

In FIG. 1, the complete priority indication register 10
, The priority of the class specified in the port is fixed,
This is used when performing full priority processing without using the round robin table 15. In a port, if there is a class to output preferentially when there is a queue, regardless of the priority information indicated by the priority control register 13, priority information in the port of the class is set. In the second embodiment, priority information is set for each output port and each output class as shown in FIG. The number of classes indicating the full priority can be arbitrarily set. For example, when it is desired to perform the full priority processing only on the class A at the port 1, the priority "1" is set in the area of the port 1 class A of the full priority instruction register 10. Otherwise, leave it unregistered. Also, two classes A and B are completely prioritized, and class A is
In the case of giving higher priority, the priority "1" is set in the class A area of the port 1 of the complete priority indication register 10, the priority "2" is set in the class B area, and the other classes are unregistered. . The setting of the priority information in the complete priority instruction register 10 is performed from the instruction unit 34.

Cell Insertion Instruction Register 1 to Empty Slot
In the case of 1, when the queues of the class that permits output are all “0” (when there are no cells to output) and there are no cells to output and empty slots are generated, the output bandwidth already exceeds the set value. If a class that has a queue is allowed to output cells to empty slots if there is a queue, the priority of the empty slot insertion priority information of the class for that port is changed to the corresponding area of the cell insertion instruction register 11 for empty slots. Set to. In the second embodiment, as shown in FIG. 5, priority information is set for each output port and each output class. In this register, similarly to the above-mentioned complete priority instruction register, the number of classes for which an insertion instruction is issued can be arbitrarily set. For example, when only the class D is vacant slot insertion processing at the port 1, “1” is set as priority information in the class D area of the port 1 of the cell insertion instruction register 11 to the vacant slot, and the other is unassigned. Register. When two classes C and D are subjected to empty slot insertion processing and class C is given priority over D, priority information is stored in the class C area of port 1 of the cell insertion instruction register 11 in the empty slot as priority information. "1" is set in the area of class D as "2" as priority information, and the other classes are unregistered. The setting of the priority information in the cell insertion instruction register 11 to the empty slot is performed by the instruction unit 35.
Do from.

Priority change / cell read control circuit 6
Has an output queue determination circuit 30, a cell read control circuit 33, and an output queue flag 32, as shown in FIG.

The output queue determination circuit 30 determines, for each output port, the priority held by the priority control register 13 selected by the priority control register selector 14 and the priority held by the full priority instruction register 10. ,
The priority is edited with reference to the priority held by the cell insertion instruction register 11 for the empty slot, and the edited priority and the queue flag of the port management table 8 are used to edit the priority.
Determine the output queue.

Specifically, first, the priority control register 1
3 is written into the priority edit register 31,
With reference to the order information of the register and the order information of the full priority instruction register 10, the order of the priority edit register 31 is rearranged by giving priority to the order of the full priority instruction register 10. However, classes that are not included in the priority control register 13 (classes whose output bandwidth is equal to or greater than the set value)
Are ignored even if there is an instruction in the complete priority indication register 10 to guarantee the allocated bandwidth.

Next, with reference to the rearranged order information of the priority order editing register 31 and the order information of the cell insertion instruction register 11 for an empty slot, a class which is not included in the order of the priority order editing register 31 will be described. If there is an empty slot insertion instruction, the priority order editing register 31 is set in accordance with the order of the cell insertion instruction register 11 for an empty slot.
Add a class to the ranking.

Further, for the class having the higher priority held by the priority editing register 31, the queue flag in the port management table 8 is referred to, and the queue flag indicating that there is a cell held in the cell buffer 2 is stored in the queue flag. The corresponding class is determined as the output queue, and the output queue flag 3
2 is set to "1".

Referring to FIG. 17, the operation of the output queue determining circuit will be described more specifically. In FIG. 17 (1),
The priority information selected by the priority control register selection unit 14 (hereinafter simply referred to as priority information of the priority control register) is stored in the order of classes C, D, and A (the priority of class C is the highest, A has the lowest priority), the instruction information of the complete priority instruction register is the order of classes B and A (the priority of class B is high), and the instruction information of the cell insertion instruction register in an empty slot is An example in which the order of classes C and B (the priority of class C is higher) will be described. For the sake of simplicity, the format of the information in the complete priority instruction register 10 and the cell insertion instruction register 11 in an empty slot is converted so that the class names are arranged in order of priority.

Hereinafter, a method of editing the priority order will be described.
The priority information of the priority control register is written into the priority editing register 31. Next, the class B having the highest priority in the complete priority instruction register is ignored because it is not included in the priority of the priority editing register 31, and the class A having the next highest priority is given the highest priority. By shifting the ranks of the 31 classes other than class A,
The priorities are classes A, C, and D. Referring to the rearranged priority of the priority editing register 31 and the cell insertion instruction register for an empty slot, first, for the class C having a higher priority in the cell insertion instruction register for the empty slot, When the classes are compared in order from the highest priority, the priority editing register 3
Since the class C is registered in the second priority of No. 1, the processing shifts to the process of the next priority class B. Since the class B is not registered in the priority order editing register 31, it is added to the order next to the classes A, C, and D, and the priority order of the priority order editing register 31 is in the order of classes A, C, D, and B. The queue flag of the port management table is referred to by the priority of the priority editing register 31, and the queue is in the class A. Therefore, the class of the output queue is A. The class A of the output queue flag 32 is set to “1”, and the processing of the output queue determination circuit ends.

If nothing is registered in the complete priority instruction register 10 and the cell insertion instruction register 11 for an empty slot, the priority of the priority control register 13 selected by the priority control register selecting unit 14 is used. The output queue is determined.

The cell read control circuit 33 refers to the output queue flag 32 for each port process, and refers to the queue management table 9 for cells input earlier than the class for which output is specified, and sets the read address. Instruct and output from the output port. Further, the read address held by the queue management table 9 is incremented by +1 (added) so as to indicate the read address of the cell input next to the output cell. Further, the queue value of the output port class of the output port in the queue management table 9 is decremented by -1 (subtraction), and when the queue value is 0, that is, when there is no cell held in the cell buffer 2, The queue flag in the port management table 8 of the class of the output port that has output is reset. After cell output,
The output queue flag 32 is reset.

Next, a read operation from the cell buffer 2 will be described with reference to FIG. For the write operation,
The operation is the same as that described in the first embodiment.

In FIG. 1, when reading a cell, the timing of reading the cell from the cell buffer 2 periodically arrives from port 1 to port N. First,
The priority change / cell read control circuit 6 stores the priority control register 13, the full priority instruction register 10, the cell insertion instruction register 11 into an empty slot, and the port management table 8 selected by the priority control register selection unit 14. The output queue is determined as described above, and the corresponding class of the internal output queue flag 32 is set to “1”.
To Next, for the class whose output queue flag 32 is “1”, the read address of the queue management table 9 is obtained, and the cell address is read from the cell buffer 2 by designating the read address. Further, the read address held by the queue management table 9 is incremented by +1 (added) so as to indicate the read address of the cell input next to the output cell.
Further, the queue value in the queue management table 9 of the class of the output port that has output is subtracted by -1 (subtraction). When the queue value after the subtraction is 0, the port management table 8 of the class of the output port that has output the output port 8 Reset the queue flag of After outputting the cell, the output queue flag 32 is reset.

In this way, the priority change / cell read control circuit 6 obtains the cell read address from the queue management table 9 for the class whose output queue flag is "1", and stores the cell. The read addresses in the cell buffer 2 are sequentially designated, and cells are read from the cell buffer 2. The cell separation unit 3 separates the cells read from the cell buffer memory for each output port.

In the read operation, when one cell of a certain class is output from a certain port, the process proceeds to the next port, and the same processing is performed. The processing from port 1 to port N is repeated. The selection signals of the priority control registers output from all the round robin tables (a) to (o) are switched from the port 1 to the port N after being output one cell at a time.

Next, the detailed operation of the priority change / cell read control circuit 6 will be described with reference to FIGS. FIG. 6 shows a cell buffer read flow in the priority change / cell read control circuit 6. For specific description, a case where the set values of the registers are as shown below is taken as an example. As shown in FIG. 12A, the queue flag of each class of the output port 1 is set to “1” for the class A,
Is "0", class C is "0", and class D is "1". The priority set in the complete priority instruction register 10 is changed to classes B and A as shown in FIG.
(Priority of B is higher). Also, the priority set in the cell insertion instruction register 11 for an empty slot is, as shown in FIG. 17A, the order of the classes C and B (the priority of C is higher). FIG.
As shown in (1), the round robin table selection unit 1
Round robin table 15 selected by 6
Is (c) (see FIG. 3), and the value of the round robin table 15 is “(9)”, that is, the priority control register selected by the priority control register selecting unit 14 is (9).
And the priority information set in the priority control register (9) is determined in the order of classes C, D, and A (class C has the highest priority, and class A has the lowest priority).
And

Referring to FIG. 6, first, the priority change / cell read control circuit 6
(Step 40), A = 1, B = 0, C
= 0 and D = 1 are recognized (step 41). Next, the priority change / cell read control circuit 6 searches the priority control register 13 (9) and recognizes that the priority of each class is the order of classes C, D, and A (step 42). ). Next, the full priority instruction register 10 and the cell insertion instruction register 11 for an empty slot are searched to recognize the instruction contents (step 43). By the steps 41, 42 and 43, the output class is determined to be A as shown in FIG.
Is set in the class A of. As shown in FIG. 6, an actual read operation from the cell buffer 2 is performed on the cell corresponding to class A (step 45). In this example, since the output queue flag of the class A is already "1", in the output queue flag state determination (step 46), the process proceeds to the branch 47 after the determination, and the area of the class A of the port 1 in the queue management table 9 is determined. , The read address of the cell buffer 2 is obtained, and at the read timing of the cell buffer 2, the cell buffer 2 outputs the cell information by designating the read address. Next, the priority change / cell read control circuit 6 adds 1 to the read address of the class A cell buffer 2 to obtain the next read address (step 48). Since the queue value in the port management table is obtained by subtracting the read address from the write address, the priority change / cell read control circuit 6 reduces the class A queue value of the port 1 by -1 (subtraction ) (Step 49). Next, the priority change / cell read control circuit 6 determines whether the queue value is 0 or not (step 5).
0), if "0", it is determined that there is no cell to output,
The queue flag of the class A area of port 1 in the port management table 8 is set to "0" (step 51). If it is other than "0", the queue flag is already "1", and the process proceeds to the next process (branch 52). Further, the output queue flag 32 is reset.

Class A read from cell buffer 2
Are output to the output port 1 through the cell separation unit 3. When a class A cell is output to port 1,
Next, the process proceeds to the cell reading process of port 2 (branch 53).
Thereafter, read processing from port 2 to port n is performed in the same manner. After the read processing of the port n (step 63),
The value of the round robin table 15 (c) is switched to (10), and the priority control register is switched to (10). Thereafter, the process returns to port 1 and the processing from port 1 to port n is repeated.

Next, an example will be described in which, when returning to the read processing of the port 1 again, the set values of the respective registers are as shown below. As shown in FIG. 12B, the queue flags of the classes of the output port 1 are set to "0",
Is "0", class C is "0", and class D is "1". Also, the output band of class A reaches the set value, and FIG.
As shown in FIG. 7 (2), the round robin table 1 selected by the round robin table selecting unit 16
5 is changed to (f), and the value of the round robin table (f) is (17), that is, the priority control register selected by the priority control register selector 14 is (17).
And the priority information set in the priority control register is the order of classes C and D (class C has a higher priority).

In FIG. 6, the priority change / cell read control circuit 6 searches the port 1 area of the port management table 8 in the same manner as described above (step 40), and A = 0, B
= 0, C = 0, and D = 1 are recognized (step 4).
1). Next, the priority change / cell read control circuit 6
Searches the priority control register 13 (17) and recognizes that the priority of each class is the order of classes C and D (step 42). Next, a complete priority instruction register 10 and a cell insertion instruction register 11 for an empty slot
Is retrieved, and the contents of the instruction are recognized (step 43). In steps 41, 42 and 43, the output class is determined to be D as shown in FIG. 17 (2), and the output queue flag is set. Next, cell read processing 45 of class A
Since the output queue flag of class A is "0", the read operation of class A is not performed through the branch 54 in the output queue flag state determination (step 46). That is, when there is no cell to be read, the process proceeds to the next class (class B) without accessing the queue management table 9.

Next, for the classes B and C, the output queue flags of the classes B and C are similarly "0" in the read operation steps 55 and 56 as in the case of the class A. Thereafter, the process proceeds to the next class (class D) processing (step 57). Since the state of the output queue flag of the class D cell is "1", in the output queue flag state determination (step 46), the process shifts to the reading process of the cell buffer 2 and the area of the class D of port 1 in the queue management table 9 , The read address of the class D cell buffer of the cell buffer 2 is obtained, and at the read timing of the cell buffer, the cell buffer 2 outputs cell information by designating the read address. Next, the priority change / cell read control circuit 6 adds 1 to the read address of the cell buffer 2 of class D,
This is the next read address. (Step 48). Since the queue value in the port management table 9 is obtained by subtracting the read address from the write address, the priority change / cell read control circuit 6 reduces the class D queue value of the port 1 by -1 (subtraction). ) (Step 49). Next, the priority change / cell read control circuit 6 determines whether the value of the queue is 0 or not (step 50). If "0", there is no cell to be output. Then, the queue flag of the class D area of the port 1 in the port management table 8 is set to “0” (step 51). If it is other than "0", the queue flag is already "1", and the process proceeds to the next process (branch 52). After the cell is output, the output queue flag 3
Reset 2

Class D read from cell buffer 2
Are output to the output port 1 through the cell separation unit. After that, the process goes to the next port 2 reading process via the branch 53. After the port n reading process is completed (step 63), the value of the round robin table 15 (f) becomes (1).
Switching to 8), the priority control register is switched to (18).

Next, a case where the set values of the registers are as follows when returning to the read processing of the port 1 again will be described as an example. As shown in FIG. 12 (c), the queue flags of the classes of the output port 1 are set to "0" for the class A,
Is “1”, class C is “0”, and class D is “0”. In addition, there is no selection change of the round robin table,
The value of the round robin table (f) is (18), that is, the priority control register selected by the priority control register selector 14 has been switched to (18), and the priority information set in the priority control register Is the order of the classes D and C (the priority of the class D is high), and there is no cell of the class D and C, and the cell of the class B is read.

In FIG. 6, the priority change / cell read control circuit 6 searches the port 1 area of the port management table 8 in the same manner as described above (step 40), and A = 0, B
= 1, C = 0 and D = 0 are recognized (step 4).
1). Next, the priority change / cell read control circuit 6
Searches the priority control register 13 (18) and recognizes that the priority of each class is the order of classes D and C (step 42). Next, the full priority instruction register 10 and the cell insertion instruction register 11 for empty slots are searched to recognize the instruction contents (step 43). In steps 41, 42, and 43, the output class is determined to be B as shown in FIG. 17C, and the output queue flag is set. Next, the process proceeds to the class A cell read processing 45, and since the output queue flag of the class A cell is “0”, the read operation is performed via the branch 54 in the output queue flag state determination (step 46). , And the process proceeds to a class B cell reading process.

The queue flag state of the class B cell is
Since it is “1”, the queue flag state determination (step 4
In 6), the process proceeds to the cell buffer read processing, and the read address of the class B cell buffer of the cell buffer 2 is obtained by referring to the class B area of the port 1 in the queue management table 9 and the read timing of the cell buffer. The cell buffer 2 outputs cell information by designating the read address. Next,
The priority change / cell read control circuit 6 adds 1 to the read address of the class B cell buffer 2 to make it the next read address (step 48).
Since the queue value in the port management table 9 is obtained by subtracting the read address from the write address, the priority change / cell read control circuit 6 decrements the class B queue value of the port 1 by -1 (subtraction). ) (Step 49). Next, the priority change / cell read control circuit 6 determines whether the value of the queue is 0 or not (step 50). If "0", there is no cell to be output. Then, the queue flag of the class B area of the port 1 in the port management table 8 is set to "0" (step 51). If it is other than "0", the queue flag is already "1", and the process proceeds to the next process (branch 52). After the cell is output, the output queue flag 3
Reset 2

The class B cells read from the cell buffer are output to the output port 1 via the cell separation unit 3. Thereafter, read processing from port 2 to port n is performed in the same manner. After the read processing of port n (step 6
3), the value of the round robin table 15 (f) is (1
Switching to 7), the priority control register is switched to (17). Thereafter, the process returns to port 1 and the processing from port 1 to port n is repeated.

Next, the priority control cycle is stored in the complete priority instruction register 10 and the cell insertion instruction register 11 in the empty slot.
, And four examples of different arrival cell patterns of each class arriving at the switch will be described with reference to FIGS. 7, 8, 9 and 10. However, this operation example will be described focusing on only port 1 among the processes repeatedly performed from port 1 to port N.

FIG. 7 shows that the output bandwidth per port is 100
Mbit / s, the output bandwidth of each class A to D is 2
An example of a cell output priority control operation in the case of 5 Mbit / s and not giving an all class full priority instruction and an empty slot insertion instruction is shown. For simplicity, the priority control cycle is set to 12
The number of cells that can be output in the priority control cycle of each class is 12 cells × 25/100 = 3 cells. Port 1 of the bandwidth setting register 20 in the output queue counter / round robin table control unit 12 shown in FIG.
The value of 3 is set in the area of each class. Also,
The arrival cell pattern of each class is arrival at equal intervals,
In addition, the number of arriving cells is assumed to be equal to the number of cells that can be output. As an initial state, it is assumed that the operation is started from a state where all class queues are not present. For the sake of explanation, the actual queue value (the number of cells held in the cell buffer 2) is used instead of the queue flag. The output timing of the cell is indicated by T0 to T12.

In FIG. 7, if cells A1, B1, C1, and D1 of four classes arrive at T0, the queue value of each class becomes "1". At this point, the number of output cells is 0, no class has reached the set band, and the round robin table selects a priority control register including all four classes (a) (see FIG. 3). At this time, the priority control register is (1), the output queue flag of class A having the highest priority and having a queue is set, and the cell of A1 is read from the cell buffer 2. After the reading, the queue of the class A is decreased by 1 to "0".

Next, at T1, there is no newly arrived cell.
Queues of classes other than class A remain at 1. According to the round robin table (a), the priority control register selected by the priority control register selector 14 is switched to (2), and the class B having the highest priority is selected.
B1 is read from the cell buffer 2. After the reading, the queue of the class B is decreased by 1 to "0".

Hereinafter, similarly, the priority control register (1) indicated by the round robin table (a),
(2), (3) and (4) are repeatedly used, and the cell reading process from T2 to T8 is performed according to the priority order.

When the cells of class A3 are read from the cell buffer 2 at T8, the number of output cells of class A becomes 3, and the output queue counter / round robin table control unit 12 determines that the number of output cells of class A is equal to the set bandwidth. And selects a priority control register that does not include class A in the round robin table (b) (see FIG. 3).
Switch to

At T9, the round robin table (b)
Is the priority control register indicated by (5), and the B3 cell of class B having the highest priority is stored in the cell buffer 2
Is read from. At this point, the number of output cells of class B is 3, and the output queue counter / round robin table control unit 12 recognizes that the number of output cells of class B has reached the set band, and changes the round robin table to class A, Switch to (f) for selecting a priority control register that does not include B.

Similarly, every time a class occurs in which the number of output cells reaches the set band, the round robin table is switched, and cells of a class having a queue are placed in accordance with the priority of the priority control register indicated by the round robin table. Read from the cell buffer.

After reading the twelfth cell D3 at T11, the output cell counter 23 in the output queue counter / round robin table control unit 12 is reset, and the round robin table selected at T12 is T
(A) which is the same as 0.

As described above, in the example shown in FIG. 7, it is understood that the band division is realized in the set band without bias of the cell output class.

FIG. 8 is similar to FIG. 7 except that the output bandwidth of each of the classes A to D is set to 25 Mbit / s, the all-class full priority instruction and the empty slot insertion instruction are not issued, and the arrival cell pattern of each class is different. An example of the cell output priority control operation in this case is shown. The difference from the example shown in FIG. 7 is that the arrival cell patterns are unequal in each class, and the number of arrival cells in classes A and B exceeds the output setting band.

In FIG. 8, first, at T0, cells A1 and B1 of classes A and B arrive, and
And the queue values of B become “1”. At this point, the number of all class output cells is 0, no class has reached the set bandwidth, and (a) is selected for the round robin table. At this time, the priority control register indicated by the round robin table (a) is (1), and the A1 cell of class A having the highest priority and having a queue is read from the cell buffer 2. After the reading, the queue of the class A is decreased by 1 to "0".

At T1, there is no newly arrived cell, and only class B has a queue. The priority control register indicated by the round robin table (a) is switched to (2), and the B1 cell of class B having the highest priority and having a queue is read from the cell buffer 2.
After the reading, the queue of the class B is decreased by 1 to "0".

Next, the cell A2 of class A arrives at T2, and the value of the queue of class A becomes "1". The priority control register pointed to by the round robin table (a) is switched to (3).
The second highest class D has no queue, and the A2 cell of the third priority class A is read from the cell buffer 2. After reading, the queue of class A is decreased by 1 to "0".
Becomes

The same processing is performed in T3 and T4.
, The cell of A3 is read from the cell buffer 2, the number of output cells of class A reaches the set value, and the output queue counter /
The round robin table control unit 12 switches the round robin table to (b).

Thereafter, every time a class in which the number of output cells reaches the set band occurs, the round robin table is switched, and the cells of the class with the queue are stored in the cell buffer according to the priority of the priority control register indicated by the round robin table. Is read out.

In the example shown in FIG. 8, although the number of arriving cells of classes A and B is larger than the number of cells that can be output, when the number of output cells reaches the set band, the round robin table is switched to reach the set band. Since the class is excluded from the priority, the cells of the classes A and B are not read out beyond the set band.

FIG. 9 shows a case where the output bandwidth of each of the classes A to D is 25 Mbit / s, no empty slot insertion instruction is given, and the priorities are set in the perfect priority instruction register in the order of classes A and B. 9 shows an example of a cell output priority control operation. In this case, the contents of the complete priority instruction register 10 have priority over the contents of the priority control register 13.

In FIG. 9, it is assumed that the cells C1 and D1 of the classes C and D arrive at the timing T0, and the queues of the classes C and D become "1". The priority of the priority control register (1) is edited by the full priority instruction of the full priority instruction register. In this case, the edited priority is the same as the priority of the priority control register (1). is there. The queue values of classes A and B are 0, and cells of class C1 are read from cell buffer 2.
After the reading, the queue of the class C is decreased by 1 to “0”.

At timing T1, cells A of classes A and B
1, B1 arrives, and the queues of classes A, B, and D become "1". Since there are full priority instructions in the order of classes A and B, the priorities of B, C, D and A, which are the priorities of the priority control register (2), are changed, and the highest priority A1 of class A is changed. The cell is read from the cell buffer 2. After the reading, the queue of the class A decreases by 1 and becomes “0”.

Next, at timing T2, there are no newly arrived cells, and there are queues in classes B and D. Similar to the timing T1, there are full priority instructions in the order of classes A and B.
The order of D, A, and B is changed in the order of A, B, C, and D. However, since there is no class A queue, the B1 cell of class B having the next highest priority is read from the cell buffer 2. . After the reading, the queue of the class B decreases by 1 and becomes “0”.

Similarly, the processing in which the classes A and B have the highest priority is performed until the number of output cells of each class reaches the set value.

In the example shown in FIG. 9, the cells of the class set in the strict priority indication register have the highest priority in the cell buffer 2.
, And the entire class output band is guaranteed.

FIG. 10 shows the cell output priority in the case where the output bandwidth of each of the classes A to D is 25 Mbit / s, the complete priority instruction is not issued, and only the class D is set in the cell insertion instruction register for an empty slot. 4 shows an example of a control operation.

In FIG. 10, at timing T0, cells A1, C1 and D1 of classes A, C and D arrive, and the queues of classes A, C and D become "1". At this time, (a) is selected as the round robin table, and the priority control register indicated by the round robin table (a) is (1). Since all the classes are included in the priority order of the priority order control register (1), the priority order does not change even if an empty slot insertion instruction is given at this time, the priority order is the highest, and there is a queue. The cell of class A1 is read from the cell buffer 2. After reading, the class A queue is decremented by 1. "
0 ".

Similarly, the cell reading process from T1 to T3 is performed according to the priority of the priority control register indicated by the round robin table (a).

Similarly, at timing T4, the processing is performed according to the priority of the priority control register (1) indicated by the round robin table (a).
Since there are no class queues, no output queue is set in the output queue flag. Therefore, no cell is read from the cell buffer 2, and an empty cell is output to the output port.

At timings T5 to T7, the above-mentioned T
0 to T3, and D3 at timing T7.
When the number of cells of class D is read, the number of output cells of class D reaches the set bandwidth, and the output queue counter / round robin table control unit 12 selects a round robin table and a priority control register that does not include class D. (E)
Switch to

At timings T8 and T9, the priority is added to the priority of the priority control registers (16) and (14) indicated by the round robin table (e) and the end of the priority added to the class D having the instruction to insert an empty slot. Edited. In this case, the priorities of the priority control registers (16) are C, A, B, and D, and the priorities of the priority control registers (14) are A, B, C, and D.

At this time, when the cell of C3 is read at the timing T9, the number of output cells of the class C reaches the set bandwidth, and the output queue counter / round robin table control unit 12 stores the round robin table in the class C, Switch to (k) to select a priority control register that does not include D.

At timing T10, the priority control register (27) indicated by the round robin table (k)
Are processed in accordance with the order of A, B, and D in which a class D having an empty slot insertion instruction is added to the end of the priority order. At timing T10, only the class D has a queue, and the class D
Since there is an instruction to insert an empty slot even if the number of output cells has reached the set value, the class D cell D4 is read from the cell buffer 2.

Similarly, at timing T11, the priority control register (2) indicated by the round robin table (k)
The cell reading process is performed in accordance with the priority of 8) and the priority determined by the empty slot insertion instruction.

As described above, in the example shown in FIG. 10, if there is no queue in a class in which the number of output cells is less than the set band, and if there is a queue in a class which has already reached the set band and has an instruction to insert an empty slot, Cell reading is performed from that class.

Note that each instruction unit may be constituted by one instruction unit.

By performing the processing as described above, according to the second embodiment, the priority control registers used among the plurality of types of priority control registers are periodically circulated by the round robin table. ,
It is possible to eliminate the bias of the cell output class due to the full priority control and realize the band division.

Further, the output queue counter / round robin table control unit 12 constantly monitors the number of output cells of each class and controls the switching of the round robin table so as not to exceed the set bandwidth. Does not exceed the set value.

Further, by using the full priority indication register, it is possible to give priority to the priority control method of some or all classes in the output port, and to provide a class of the full priority process and a class of the fixed output band. Can also be mixed.

Further, by using the register for instructing cell insertion into an empty slot, if a class that satisfies the set output band has no cells to be held in the cell buffer in another class (when an empty slot occurs), the cell is replaced. It is also possible to output.

According to the first and second embodiments, the cells in the cell buffer divided for each of the plurality of quality classes can be efficiently read from those having the highest priority. At the time of cell read processing, the class to be read can be easily recognized, and the access to the management table storing the cell read address is limited to the area corresponding to the class to be output. The increase does not affect the processing time.

According to the first and second embodiments, the ratio of the priority control registers to be allocated on the round robin table is changed.
Band division can be realized, and output of only one class can be avoided.

Further, according to the second embodiment, when cells temporarily disappear from a cell buffer of a certain class, cells of another class having a lower priority at that moment are output. Since the number of output cells is constantly monitored and controlled so as not to exceed the set bandwidth, the output bandwidth of each class does not exceed the set value. That is, the output bandwidth of each class can be set for each output port, and the minimum output bandwidth can be guaranteed.

When it is desired that the priority control system of all or some classes be given full priority at a certain output port, the priority is set in the full priority instruction register corresponding to the class to be given full priority. Priority can be realized.

Further, when there is no cell in a cell buffer of another class which does not satisfy the set output band (when an empty slot is generated), it is desired to output a cell of a class satisfying the already set output band. By setting the priority of the class to be inserted into the register for instructing cell insertion into a vacant slot of the corresponding class, cells can be transmitted in accordance with the priority.

Further, since the output band of each class is managed by the output queue counter / round robin table control unit, it is not necessary to strictly divide the band in the round robin table, and the size of the round robin table is reduced. be able to. That is, even if the round robin table is small, the output band of each class can be set finely.

Further, since the round robin table is shared by all output ports, the amount of memory can be significantly reduced.

The round robin table, the priority control register, the band setting register, the full priority instruction register, and the cell insertion instruction register for an empty slot are rewritable. And port settings can be changed.

[0137]

According to the present invention, priority control of output cells can be efficiently performed, and processing time does not increase even when the number of classifications (priorities) increases.

Further, the output bandwidth of each class can be set for each output port, and the output bandwidth can be guaranteed.

The setting of each class at each output port can be freely changed to either fixed output band or full priority, and a class that fixes the output band and a class that outputs cells by full priority control. Can be mixed.

Further, the class satisfying the set output band is
If there is no cell held in the cell buffer in another class, cell output becomes possible.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an output buffer type switch system according to a second embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a port management table used in the first and second embodiments of the present invention.

FIG. 3 is an explanatory diagram showing details of a priority order control register and a round robin table used in a second embodiment of the present invention.

FIG. 4 is an explanatory diagram showing details of an output queue counter / round-robin table control unit used in a second embodiment of the present invention.

FIG. 5 is an explanatory diagram showing details of a priority change / cell read control circuit, a complete priority instruction register, and a cell insertion instruction register to an empty slot used in the second embodiment of the present invention.

FIG. 6 is a flowchart for reading out a cell buffer according to a second embodiment of the present invention;

FIG. 7 is an explanatory diagram (1) showing the operation of the cell output priority control unit according to the second embodiment of the present invention.

FIG. 8 is an explanatory diagram (2) illustrating the operation of the cell output priority control unit according to the second embodiment of this invention.

FIG. 9 is an explanatory diagram (3) showing the operation of the cell output priority control unit according to the second embodiment of the present invention.

FIG. 10 is an explanatory diagram (4) showing the operation of the cell output priority control unit according to the second embodiment of the present invention.

FIG. 11 is a configuration diagram of an output buffer type switch system according to the first embodiment of the present invention.

FIG. 12 is a port management table used in the second embodiment of the present invention.

FIG. 13 is a flowchart (1) for reading out a cell buffer according to the first embodiment of the present invention.

FIG. 14 is a flowchart (2) for reading out a cell buffer according to the first embodiment of the present invention;

FIG. 15 is a flowchart (3) for reading out a cell buffer according to the first embodiment of the present invention;

FIG. 16 is an explanatory view showing a conventional technique.

FIG. 17 is an explanatory diagram showing an operation of the output queue determination circuit used in the second embodiment of the present invention.

[Explanation of symbols]

1.100 cell multiplexing unit, 2.101 cell buffer memory, 3.102 cell separation unit, 4.103 routing / priority destination class identification circuit, 5.104 cell writing control circuit, 6. priority Change / cell read control circuit, 7: memory interface, 8: port management table, 9: queue management table, 10: full priority instruction register, 11: cell insertion instruction register to empty slot, 12: output queue counter / round robin Table control unit, 13.92 ... priority control register,
14.93 ... Priority control register selection unit, 15.91
... Round robin table, 16 ... Round robin table selector, 17 ... Round robin table indicator, 1
8.94: Priority control register instructing unit, 20: Band setting register, 21: Band excess determining circuit, 22: Band setting register instructing unit, 23: Output cell number counter, 30: Output queue determining circuit, 31: Priority Edit register, 32
... output queue flag, 33 ... cell read control circuit, 3
4: Full priority instruction register designating unit, 35: Cell insertion instruction register designation unit to empty slot, 41: Queue state recognition processing of each class, 42: Priority determination processing of each class, 43: Full priority instruction, empty slot Insertion instruction recognition processing, 44 ... output class determination processing, 45 ... class A cell buffer read processing, 46 ... class A cell output queue presence / absence determination processing, 47 ... class A cell output queue flag is "1" 48: cell buffer read address update processing; 49: queue value subtraction (-1) processing; 50: queue value comparison with "0"; 51: queue flag "0" write Processing 52: Queue flag “1” write processing 53: Transition route to cell read processing of port 2 54: Queue flag of cell of class A “0” Transition route of time, 55: Class B cell buffer read process, 56: Class C cell buffer read process, 57: Class D cell buffer read process, 90: Cell read control circuit, 95: Class A cell queue Presence determination processing, 105: cell read control circuit (full priority control), 106: management table.

Claims (9)

[Claims] 1. An ATM switch for inputting a cell and outputting the cell from an output port corresponding to a destination according to a predetermined class indicating a type of service added to the input cell, For each output port, for each class, a cell holding unit for holding cells in the order of input, and for each output port, for each class, there is no cell held in the cell holding unit. Management means for managing the priority, priority holding means for holding a plurality of priorities of the class, selecting means for selecting any one of the priority from the priority holding means, for each of the output ports, In the priority order selected by the selection means, the class is higher and the management means manages that there is a cell held in the cell holding means. Read control means for outputting, from the port, a cell held in the cell holding means, which is input first, for the class, and wherein the selecting means selects the type to be selected at every predetermined time. And also monitors the output band of each class of cells for each output port, and when the monitored output band becomes the set value of the output band of the class of the output port, the output port is An ATM switch, wherein a priority not including said class is selected from said priority holding means. 2. The method according to claim 1, wherein the selecting unit further includes a plurality of types of patterns indicating the order of switching the types of priorities in order to switch the type to be selected at every predetermined time. When the monitored output band becomes the set value of the output band of the class of the output port, the priority is selected from the priority holding unit according to a pattern not including the class of the output port. An ATM switch, comprising: 3. The output band monitor according to claim 1, wherein said selection means monitors the output band by counting the number of cells output in a predetermined time of each class for each output port. ATM switch. 4. The full priority storage device according to claim 1, wherein in each class for each of said output ports, priority of at least one class for each of said output ports is given priority over priority of said priority storage device. Means, wherein the read control means causes the priority of the class held in the full priority holding means to be prioritized over the priority of the selected priority holding means, and causes the cell to be output. An ATM switch, characterized in that: 5. The method according to claim 1, wherein:
When the cell of the class whose output band is less than the set value is not held in the cell holding unit, when the cell of the class whose output band is the set value is held in the cell holding unit, Instruction means for permitting output of cells of the class is further provided, wherein the read control means sets the output band when the cells of the class whose output band is less than a set value are not held in the cell holding means. When the class that is the value is a class permitted by the instruction means and a cell of the class is held by the cell holding means, the cell of the class is output. ATM switch. 6. The ATM switch according to claim 1, further comprising a priority order indicating means for receiving said priority order from outside and holding said priority order received by said priority order holding means. 7. An ATM switch for inputting a cell and outputting the cell from an output port corresponding to a destination in accordance with a predetermined class indicating a type of service added to the input cell, For each output port, for each class, a cell holding unit for holding cells in the order of input, and for each output port, for each class, there is no cell held in the cell holding unit. Management means for managing the, priority holding means for holding a plurality of priorities of the class, and selecting one of the priorities from the priority holding means, and, for each predetermined time, Selecting means for switching the type to be selected; and in each class for each of the output ports, a priority is given to the priority of the priority holding means. A full priority holding unit that holds the priority of both classes, and, for each of the output ports, when there is a priority of the class held in the full priority holding unit, the priority is selected. Priority given to the given priority holding means, and in that priority,
For a class that is a higher class and is managed by the management unit as having a cell held in the cell holding unit, the cell that is input first and the cell held in the cell holding unit is An ATM switch, comprising: read control means for outputting from a port. 8. A plurality of input ports, a plurality of output ports, an output port corresponding to a destination added to a cell input from the plurality of input ports, and a type of service added to the cell An identification circuit for identifying a class indicating an input cell; a cell buffer for holding input cells; and an input cell for each of the output ports, and for each of the classes, holding the input cells in the cell buffer in the order of input. A write control circuit that instructs a write address of the cell buffer, and for each of the output ports, a class having a higher priority, and a class having a cell held in the cell buffer. In order to output the cell held in the cell buffer, which has been input first, from the port, a read instruction indicating a read address is performed. A control table that holds the write address and the read address for each of the output ports and for each of the classes; a priority control register that holds a plurality of priorities of the classes; Any one from the priority control register
A selection circuit for selecting one of the priorities, the selection circuit switches the type to be selected at every predetermined time, and monitors the output band of each class of cells for each of the output ports, When the monitored output band becomes the set value of the output band of the class of the output port, a priority not including the class of the output port is selected from the priority control register. Characteristic ATM switch. 9. A cell output priority control in an ATM switch for inputting a cell and outputting the cell from an output port corresponding to a destination in accordance with a predetermined class indicating the type of service added to the input cell. A method for holding cells in the order of input for each of the output ports and for each of the classes, and managing whether or not there are cells to be held for each of the output ports and for each of the classes And holding a plurality of priorities of the class in a register;
The output band of each class of cells for each output port is monitored, and when the monitored output band becomes the set value of the output band of the class of the output port, the class of the output port is not included. One of the priorities is selected from the register, the type to be selected is switched at predetermined time intervals, and for each of the output ports, the higher priority class in the selected priority order, A cell output priority control method comprising: outputting, from a port, a held cell, which has been input first, for a class managed to have a cell that has been stored.