JPH1141086A - Integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit in which the output level of a CMOS output circuit is decreased while keeping a high speed operation. SOLUTION: In the case of executing the initialization instruction of a 1-chip microcomputer, the state of a selection terminal is detected. When the selection terminal 5 is at a low level, selection data at a logical '0' are outputted from a CPU 12, latched by a latch circuit 14 and a CMOS output circuit consisting of a PMOS transistor(TR) 8 and an NMOS TR 7 connected in series between ground VSS and a 2nd power supply voltage VDD2 lower than a 1st power supply voltage VDD1 is turned on/off depending on output data and the output data going to a high level or a low level within a range of an amplitude (VDD2- VSS) are introduced from an output terminal 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit (such as a one-chip microcomputer) for outputting digital signals having different amplitudes.

[0002]

2. Description of the Related Art A one-chip microcomputer is indispensable as a control center of electronic equipment.
2. Description of the Related Art As the power supply voltage of electronic devices has been reduced, the power supply voltage of a one-chip microcomputer has been required to be reduced, and development for that purpose has been promoted.

[0003]

However, from the relationship between the power supply voltage of the one-chip microcomputer and the operating frequency, if the power supply voltage of the one-chip microcomputer is simply reduced, the operating speed of the one-chip microcomputer also decreases. Therefore, there is a problem how to reduce the power supply voltage while maintaining the high-speed operation.

Therefore, the present invention makes the power supply of the CMOS output stage for outputting a control signal (for example, 5 volt amplitude, 3 volt amplitude, etc.) for electronic equipment independent of the power supply of the entire integrated circuit, and In order to easily lower the voltage of the power supply of the CMOS output stage in accordance with the present invention.

[0005]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and has a first voltage having a different voltage value.
First and second power supply terminals to which a first and second power supply voltages are respectively applied, and a first and a second power supply terminals connected between the first power supply voltage and the ground.
A CMOS output circuit, a second CMOS output circuit connected between the second power supply voltage and ground, the first or second
A selection circuit for selecting one of the CMOS output circuits;
And an output terminal for deriving a different amplitude output of one of the first and second CMOS output circuits. Further, the selection circuit is constituted by a logic circuit for selecting one of the first and second CMOS output circuits according to selection data. Furthermore,
The first or second CMO for supplying to the selection circuit
It is characterized by including a register in which selection data for selecting one of the S output circuits is set. Furthermore,
A selection data according to a voltage setting state of a specific terminal is set in the register. Further, the power supply inputs of the first and second CMOS output circuits and the selection circuit are made independent.

Next, first and second power supply terminals to which first and second power supply voltages having different voltage values are applied, respectively,
Or a selection circuit for selecting and outputting one of the second power supply voltage and a CM connected between the output of the selection circuit and ground.
An OS output circuit and an output terminal for outputting a different amplitude output when the CMOS output circuit is connected to one of the first and second power supply voltages. In particular, the selection circuit is a mask switch.

Next, a power supply terminal to which the first power supply voltage is applied, a regulator for generating a second power supply voltage having a different voltage value, a CMOS output circuit connected between the output of the regulator and ground, An output terminal for deriving an amplitude output of the CMOS output circuit.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be specifically described with reference to the drawings. FIG. 1 is a circuit block diagram showing a first embodiment of the present invention, which is applied to a one-chip microcomputer. In FIG. 1, (1) is the first
The first where the power supply voltage VDD1 (for example, 5 volts) is applied
A power supply terminal, (2) is a second power supply terminal to which a second power supply voltage VDD2 (for example, 3 volts) is applied, and (3) is a ground VSS.
And a ground terminal connected to the terminal. (4) is (VDD1-V
This is an output terminal for outputting a high-level or low-level output signal with an amplitude of (SS) or (VDD2-VSS).
(5) is the first power supply voltage VDD1 or the second power supply voltage VDD
2 is a selection terminal for instructing selection of the first power supply voltage VD
When D1 is selected, the high-level voltage VDD1 is applied, and when the second power supply voltage VDD2 is selected, the low-level voltage VSS is applied.

[0009] PMOS transistor (6) and NMOS
The transistor (7) is connected to the first power supply voltage VDD1 and the ground VS.
And S in series to form a first CMOS output circuit. The PMOS transistor (8) and the NMOS transistor (7) are connected in series between the second power supply voltage VDD2 and the ground VSS to form a second CMOS output circuit.
That is, in the first and second CMOS output circuits, the NMO
The S transistor (7) is shared, and the PMOS transistors (6) and (8) operate complementarily.

The NAND gates (9) and (10) and the inverter (11) form a selection circuit. Selection data is inverted and applied to one input terminal of the NAND gate (9), output data is applied to the other input terminal, and the output terminal is connected to the gate of the PMOS transistor (8). Selection data is applied to one input terminal of the NAND gate (10), output data is applied to the other input terminal, and the output terminal is connected to the gate of the PMOS transistor (6). Output data is applied to the input terminal of the inverter (11), and the output terminal is connected to the gate of the NMOS transistor (7). Note that the selection circuit operates at the first power supply voltage VDD1.

Reference numeral (12) denotes a CPU for controlling the operation of the one-chip microcomputer. Only in the embodiment of the present invention, the CPU (12) includes a ROM (program memory), an ALU (arithmetic logic unit), an ACC
(Accumulator) and a general term including various registers. Note that the CPU (12) also operates at the first power supply voltage VDD1. For example, when executing the initialization instruction of the one-chip microcomputer, the CPU (12) captures the state of the selection terminal (5) via the buffer (13). That is, when the CPU (12) recognizes that the state of the selection terminal (5) is a high level, the logic (1) (high-level voltage V
The selection data of DD1) is output, and when the state of the selection terminal (5) is recognized as low level, the selection data of logic "0" (low-level voltage VSS) is output. Latch circuit (1
4) latches the selection data at this time and supplies it to one input terminal of the NAND gates (9) and (10) constituting the selection circuit. The CPU (12) also outputs output data to be derived from the output terminal (4) at an appropriate timing after the initialization instruction of the one-chip microcomputer. The latch circuit (15) latches the output data at this time and supplies it to the input terminal of the inverter (11) constituting the selection circuit. Therefore, when the selected data is logic "1", the NAND gate (10) opens, so that P
The MOS transistor (6) and the NMOS transistor (7) are turned on / off according to the output data, and an output that changes to a high level or a low level within the range of the amplitude (VDD1-VSS) is derived from the output terminal (4). On the other hand, when the selection data is logic "0", the NAND gate (9) opens, so that the PMOS transistor (8) and NM
The OS transistor (7) turns on and off according to the output data, and an output that changes to a high level or a low level within the range of the amplitude (VDD2-VSS) is derived from the output terminal (4). The detection of the state of the selection terminal (5) is not limited to the execution of the initialization instruction of the one-chip microcomputer, and the output data is output during the normal operation of the one-chip microcomputer according to the operating conditions of the electronic device. You can change the amplitude without any problem. Further, the amplitude of the output data derived from the output terminal (4) may be changed by a method other than detecting the state of the selection terminal (5).

As described above, since only the power supply of the second CMOS output circuit comprising the PMOS transistor (8) and the NMOS transistor (7) is made independent at a low voltage, the high-speed operation of the one-chip microcomputer is maintained.
Compatible with low voltage electronic equipment. Further, the PMOS transistor (6) and the NM can be switched at the timing intended by the user.
The operation can be switched from the first CMOS output circuit including the OS transistor (7) to the second CMOS output circuit. In addition, conventionally, a pull-up resistor was connected to an open-drain type NMOS transistor to output a high level. However, since the CMOS transistor is controlled to be on and off to output a high level or a low level, electronic devices are required. It has effects such as high-speed control.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention, and shows a case where the present invention is applied to a one-chip microcomputer. Note that the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 2, reference numeral (16) denotes a metal switch for performing mask switching, one switching input terminal is connected to the first power supply terminal (1) to which the first power supply voltage VDD1 is applied, and the other switching input terminal is connected to the first switching input terminal. It is connected to the second power supply terminal (2) to which the two power supply voltages VDD2 are applied, and the mask is switched to the switching input terminal side required by the user using a metal wiring or the like. The drain source path of the CMOS output circuit comprising the PMOS transistor (17) and the NMOS transistor (18) is connected in series between the switching output terminal of the metal switch (16) and the ground VSS, and the common drain is connected to the output terminal (4). Connected. The inverter (19) is driven by the first power supply voltage VDD1. Then, the output data is applied to a common gate of the PMOS transistor (17) and the NMOS transistor (18) via the inverter (19). Here, when compared with FIG. 1, one large-sized PMOS transistor constituting the CMOS transistor can be omitted.
Chip size can be reduced.

FIG. 3 is a circuit block diagram showing a third embodiment of the present invention, and shows a case where the present invention is applied to a one-chip microcomputer. In FIG. 3, reference numeral (20) denotes a regulator, which outputs a second power supply voltage VDD2 (<VDD1) from the first power supply voltage VDD1.
S transistor (17) and NMOS transistor (1
The drain source path of 8) is connected in series between the output of the regulator (20) and the ground VSS. Here, when compared with FIG. 2, the amplitude of the output data derived from the output terminal (4) is fixed to (VDD2-VSS), but one power supply terminal can be omitted. Of course, the inverter (19) is driven by the first power supply voltage VDD1.

[0015]

According to the present invention, the power supply of the CMOS output circuit and the power supply of other elements of the integrated circuit are made independent, and the CMOS
Since the power supply of the output circuit is set to a low voltage, it is possible to cope with a low voltage of the electronic device while maintaining the high-speed operation of the one-chip microcomputer. Further, the operation of the first CMOS output circuit and the operation of the second CMOS output circuit can be switched at a timing intended by the user. Further, conventionally, a pull-up resistor is connected to an open-drain type NMOS transistor to output a high level. However, since a CMOS output circuit is turned on and off to output a high level or a low level, an electronic device is output. Can be controlled at a high speed.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit block diagram showing a third embodiment of the present invention.

[Explanation of symbols]

 (1) First power supply terminal (2) Second power supply terminal (4) Output terminal (5) Select terminal (6) (8) (17) PMOS transistor (7) (18) NMOS transistor (9) (10) NAND Gate (14) (15) Latch circuit (16) Metal switch

Claims (8)

[Claims] A first power supply terminal to which first and second power supply voltages having different voltage values are respectively applied; and a first CMO connected between the first power supply voltage and a ground.
S output circuit; and a second CMO connected between the second power supply voltage and ground.
An S output circuit; a selection circuit that selects one of the first and second CMOS output circuits; and an output terminal that derives a different amplitude output from one of the first and second CMOS output circuits. An integrated circuit characterized by the above. 2. The selection circuit according to claim 1, wherein said selection circuit comprises a logic circuit for selecting one of said first and second CMOS output circuits in accordance with selection data.
An integrated circuit as described. 3. The method according to claim 1, further comprising the step of:
3. The integrated circuit according to claim 2, further comprising a register in which selection data for selecting one of the second CMOS output circuits is set. 4. The integrated circuit according to claim 3, wherein selection data according to a voltage setting state of a specific terminal is set in said register. 5. The integrated circuit according to claim 1, wherein power supply inputs of said first and second CMOS output circuits and said selection circuit are made independent. 6. A first and second power supply terminal to which first and second power supply voltages having different voltage values are respectively applied, a selection circuit for selecting and outputting one of the first and second power supply voltages, CMOS connected between the output of the selection circuit and ground
An integrated circuit, comprising: an output circuit; and an output terminal that derives a different amplitude output when the CMOS output circuit is connected to one of the first and second power supply voltages. 7. The integrated circuit according to claim 6, wherein said selection circuit is a mask switch. 8. A power supply terminal to which a first power supply voltage is applied, a regulator for generating a second power supply voltage having a different voltage value, and a CM connected between an output of the regulator and ground.
An integrated circuit, comprising: an OS output circuit; and an output terminal for deriving an amplitude output of the CMOS output circuit.