JPH1140813A - Semiconductor element and its manufacture, and treatment method after dry etching - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the OFF-state current of a semiconductor element and to enhance its electric characteristic by a method wherein, after an etching operation, the number of defect levels generated in the semiconductor element is reduced. SOLUTION: When a post-treatment is executed after a dry etching operation, a plasma surface treatment is executed by using a gas whose reactivity to a substrate 101 and a device 102 is low such as, e.g. N2 , Ar, He or the like, and an etching gas or a reaction product element which is stuck to the substrate 101 and the device 102 is removed. Thereby, the plasma surface treatment can be continued through an apparatus which performs a dry etching operation, and it is not required to especially install an apparatus which is used to remove the etching gas or the reaction product element which is stuck to the substrate 101 and the device 102. Consequently, after the etching treatment, the etching gas or the reaction product element can be removed by executing a plasma surface treatment by the gas whose reactivity to the substrate 101 and the device 102 is low, and the reliability of the device 102 can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a thin film transistor used for an active device such as an active matrix type liquid crystal display device or a contact type image sensor, and a method for manufacturing the same. The present invention relates to a processing method after dry etching for removing an etching gas element and a reaction product remaining on an object to be etched after dry etching performed at times.

[0002]

2. Description of the Related Art Conventionally, a thin film transistor (TFT:
Thin film transistors are most frequently used in active matrix liquid crystal display devices (AMLCD).
The basic structure of the TFT is staggered and inverted staggered TFT
However, here, an inverted stagger type TFT will be described.

The above-mentioned inverted stagger type TFT includes a) a channel protection type TFT and b) a back channel etching type TFT.
There is.

First, the structure and manufacturing method of a channel protection type TFT will be described below with reference to FIG.

First, on an insulating substrate 210 such as glass,
After laminating Al, Mo, Ta, and the like by a sputtering method, the gate electrode 220 and the gate wiring (not shown) are formed by patterning.

Next, plasma CVD (Chemical Vapor D)
A gate insulating film 230 is stacked so as to cover the gate electrode 220 by an eposition method.

[0007] Next, on the gate insulating film 230, T
An FT channel layer 240 is formed. This channel layer 2
A channel protection layer 290 serving as an etching stopper layer is formed in a portion corresponding to the channel region of No. 40.

After that, the source electrode 2 of the TFT is formed by an amorphous Si film or a microcrystalline Si film doped with n + -type impurities similarly formed by the plasma CVD method.
60b and the contact layer 2 of the drain electrode 260a
50 is formed, and both Si of the channel layer 240 and the contact layer 250 are patterned. At this time, since the channel layer 240 is protected by the channel protective layer 290 serving as an etching stopper layer, only the contact layer 250 is etched to form source and drain contact regions.

Then, after a Ta, Cr, Ti, ITO film or the like or a laminated film of these is formed, it is patterned along the shape of the contact layer 250 to form a drain electrode 260a, a source electrode 260b and a wiring. And a drain electrode 260a and a source electrode 260
A gap 280 is formed between the gap 280 and the gap b.

Finally, a TFT protective film 270 made of a SiN film formed by a plasma CVD method and a resin insulating film or a laminated film thereof is formed.

Next, a back channel etching type TFT
The structure and manufacturing method will be described below with reference to FIG.

The above back channel etching type TFT
Is a case where the channel protection layer 290 formed in the channel protection type TFT shown in FIG.
And a film to be a channel layer 240 and a contact layer 250
After the film to be formed is formed, both the Si films to be the channel layer 240 and the contact layer 250 are patterned into an island shape.

Next, a metal film such as Ta or Al is formed,
This metal film is patterned to form a drain electrode 260a,
A source electrode 260b and a wiring are formed.

Thereafter, an amorphous Si film or a microcrystalline Si film serving as a contact layer 250 on the channel layer 240 is formed.
The film is removed by etching to form a contact region between the drain electrode 260a and the source electrode 260b. At this time, since it is difficult to etch only the amorphous Si film or the microcrystalline Si film while leaving the film to be the channel layer 240, a part of the channel layer 240 (the part opposite to the interface forming the TFT channel). Portion) is etched away. Therefore, the channel layer 240 is formed as shown in FIG.
The channel layer 240 of the channel protection type TFT shown by 3
Is formed thicker than before.

The electrical characteristics of a TFT require that the on-current be high and the off-current be low.
In particular, in the case of a TFT liquid crystal display, the charge charged in the pixel capacitor region using the liquid crystal layer or the like as a dielectric or a capacitor formed supplementarily during the on time of the TFT is usually at least 200 times or more the above on time. Since the current needs to be maintained for a certain off-time, the ratio of the on-current to the off-current (on-current / off-current) needs to be about 5 digits or more.

Such electric characteristics of the TFT need to be achieved even when the operating temperature range of the TFT liquid crystal display is extended.

In general, in a semiconductor device such as the above-described TFT, it is necessary to etch a semiconductor film forming a contact layer in a manufacturing process in order to form a contact region for a drain electrode and a source electrode. An increase in the number of defect states due to lattice disorder of the semiconductor layer after etching, etching damage such as desorption of hydrogen, and an etching gas element or a reaction product attached to an object to be etched increase an off-state current of the TFT.

In view of the above, conventionally, as a process after dry etching, various methods have been proposed for removing an etching gas element and a reaction product element attached to an object to be etched.

For example, an etching gas element or a reaction product adhering to a substrate after performing dry etching is converted into an acid,
A method has been proposed in which treatment is performed with a liquid such as an alkali, an organic solution, and water to remove the liquid.

In addition, when dry etching is performed, substances adhering to the chamber walls are removed by evaporating the chamber at a higher temperature and exhausting the same from the chamber, or disclosed in JP-A-59-143073. As described above, a method has been proposed in which a purge gas such as N ₂ or Ar is further flown into a chamber at a high temperature to remove the gas.

Further, a method has been proposed in which a substance attached to the chamber wall is removed by a user wiping the chamber itself with alcohol.

[0022]

However, in general, TF
Both the ON current and the OFF current of T increase with an increase in temperature. The rate of increase of the current due to the temperature rise is particularly large because the off-state current is larger than the on-state current. Can not do it.

As described above, when the off current increases, TF
As a result, the characteristics of T are deteriorated, and the display quality of the TFT liquid crystal display is deteriorated.

In addition, as a conventional post-dry etching process, the following problem occurs in the method of removing an etching gas element and a reaction product attached to an object to be etched.

1) In a treatment method using a solution such as an acid, an alkali, an organic solution, and water, a special device other than the etching device, that is, a device for operating the solution, a waste liquid treatment device for discharging the solution, and the like are required. In addition, problems such as an increase in the number of manufacturing steps occur.

2) In the processing method by raising the temperature of the chamber, the time interval from the end of the processing of the substrate to the processing of the next substrate is shortened in the manufacturing for processing the next substrate. That is, the time required for the elements attached to the substrate to evaporate and be exhausted is shortened, and there is a problem that the elements attached to the substrate cannot be effectively removed.

3) The processing method disclosed in JP-A-59-143073 has a problem that the processing time is as long as 10 minutes to 1 hour, and the processing capacity of the apparatus in the manufacturing process is greatly reduced.

4) The method of wiping the chamber wall with alcohol to remove the etching gas elements and reaction products adhered to the chamber wall is performed by the user himself, so that harmful gases and reaction products adversely affect the human body. May be affected.

The present invention has been made in order to solve the above problems, and an object of the present invention is to reduce the off-state current,
Improving the electrical characteristics of a semiconductor element, that is, in the process of manufacturing a semiconductor element, after etching for forming a contact layer, efficiently remove an etching gas element and a reaction product attached to a substrate, or By reducing the lattice disorder of the layer and suppressing the desorption of hydrogen, by reducing the number of defect levels generated in the semiconductor element, the off current of the semiconductor element can be reduced, and the electrical characteristics can be improved. It is an object of the present invention to provide a semiconductor device capable of reducing the influence of a residual etching gas or a reaction product on a human body, a method of manufacturing the same, and a processing method after dry etching.

[0030]

According to a first aspect of the present invention, there is provided a semiconductor device having at least a gate,
Source and drain electrodes, a gate insulating film, a first semiconductor thin film that forms a channel region, and directly connected to the first semiconductor thin film and formed between the source and drain electrodes and the first semiconductor thin film. And a second semiconductor thin film doped with n + impurity, wherein the gate voltage is a sub-threshold region in the semiconductor device characteristics and the drain current is 1E-10.
[A] In the case of the following region, the leak current Ids flowing between the source electrode and the drain electrode is approximated by the following equation (1), and Ids × L / W = Aexp (−Ea / kT (1) Ea: activation energy (eV) k: Boltzmann constant T: temperature (k) W / L: semiconductor element size The value of T in the above equation (1) at the above gate voltage is 303.
When 〜 [338], the value of A is set to 5E-6 [A] or less.

According to the above configuration, the off-state current and the off-side photocurrent can be reduced in the actual operating temperature range of the device using the semiconductor element.

Thus, when the semiconductor element is a TFT, the electrical characteristics of the TFT can be improved.
That is, the on-state current of the TFT having the above structure can be increased and the off-state current can be decreased.

A device using this TFT is called TF
In the case of a T liquid crystal display, the ratio between the ON current and the OFF current of the TFT can be secured to about 5 digits or more.
The display quality in a TFT liquid crystal display can be improved.

According to a second aspect of the present invention, at least a gate, a source, and a drain electrode, a gate insulating film, and a first semiconductor thin film forming a channel region are provided. In a semiconductor device having a second semiconductor thin film directly connected to a first semiconductor thin film and formed between the source and drain electrodes and the first semiconductor thin film and doped with n +, the gate voltage may be: When the sub-threshold region in the semiconductor device characteristics corresponds to a region where the drain current is 1E-10 [A] or less, the leak current Ids flowing between the source electrode and the drain electrode is expressed by the following equation (1). Ids × L / W = Aexp (−Ea / kT) (1) Ea: activation energy (eV) k: Boltzmann constant T: Temperature (k) W / L: the value of Ea in equation (1) in the semiconductor element size the gate voltage is 0.
In the range of 3 to 0.5 [eV], the value of A is 5E-
6 [A] or less.

As described above, the same effect as in the first aspect can be obtained also in the region of the gate voltage defined by the activation energy instead of the temperature.

As the TFT, for example, in addition to the structure of claim 1 or 2, like the semiconductor element of claim 3,
A TFT in which the entire region of the second semiconductor thin film corresponding to the gap between the source electrode and the drain electrode and a part of the region of the first semiconductor film corresponding to the gap are removed; That is, a back channel etching type TFT can be suitably used.

At this time, the above-mentioned gate voltage is equal to
Is set in the range of -1 to -5 V as in the semiconductor device of FIG. Further, the drain voltage is set to 5 to 15 V as in the semiconductor device of the fifth aspect. The capacitance per unit area of the gate insulating film is set, for example, to 1 to 2E-4 [F / m ² ], as in the semiconductor device of the sixth aspect.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a first step of forming a gate electrode on an insulating substrate; and forming a gate insulating film on the gate electrode. A second step of forming; a third step of laminating a first semiconductor thin film having a channel region to be a semiconductor layer on the gate insulating film;
Second doped with n + impurity to be a contact layer
A fourth step of stacking semiconductor thin films, a fifth step of patterning the first semiconductor thin film and the second semiconductor thin film into a predetermined shape, and forming a source electrode and a drain electrode on the second semiconductor thin film The sixth step and the first step
A seventh step of etching the second semiconductor thin film on the channel region of the semiconductor thin film to form the contact regions for the source electrode and the drain electrode, wherein the semiconductor device is manufactured at least up to the seventh step. A step of performing a surface treatment on the semiconductor element by using a plasma of a gas having low reactivity with the semiconductor element.

According to the above configuration, in the semiconductor device manufacturing process, at least the semiconductor device manufactured up to the seventh process is subjected to the plasma of the gas having low reactivity with the semiconductor device.
By performing the surface treatment of the semiconductor element, by etching performed to form a contact region, an etching gas or a reaction product remaining on the semiconductor element to be etched is removed by plasma of the gas, In addition, the number of defect states which increases due to etching damage such as disorder of the lattice of the semiconductor layer after etching and desorption of hydrogen can be reduced.

As a result, the off-current of the semiconductor element can be reduced, and the electrical characteristics can be improved.

As the gas for plasma surface treatment, for example, as described in claim 8, H ₂ , N ₂ , NH ₃ , H
At least one of e, Ar, and O ₂ is used.

According to a ninth aspect of the present invention, in order to solve the above problem, in addition to the configuration of the seventh aspect, the plasma surface treatment is performed immediately after the seventh step. The process is performed in an etching chamber used for the etching process.

According to the above construction, in addition to the function of claim 7, by performing the etching treatment and the plasma surface treatment in the same etching chamber, there is no need to provide a separate apparatus for plasma surface treatment after etching. May be. This makes it possible to efficiently remove the etching gas elements and reaction products attached to the substrate without increasing the number of manufacturing steps.

According to a tenth aspect of the present invention, in order to solve the above-mentioned problem, the etching gas element and the reaction product remaining after the dry etching are removed.
In a post-dry etching treatment method for removing an object to be etched and a chamber in which etching is performed, a gas having low reactivity with the object to be etched is turned into plasma, and the object to be etched after dry etching and the chamber are etched using the plasma gas. The surface is treated.

According to the above-described structure, the object to be etched after the dry etching is subjected to plasma surface treatment using a gas having a low reactivity with respect to the object to be etched. Gas elements and reaction products can be removed.

Further, if the above-mentioned processing method after dry etching is applied during the manufacture of a semiconductor device, the number of defect levels which increase due to etching damage such as lattice disorder of a semiconductor layer caused by etching and desorption of hydrogen is reduced. be able to.

As a processing method after the dry etching, specifically, as in the processing method after the dry etching according to the eleventh aspect, in addition to the configuration of the tenth aspect, the dry etching and the method after the dry etching are performed. The plasma surface treatment is performed continuously in the same chamber.

As described above, by performing the etching treatment and the plasma surface treatment in the same chamber, it is not necessary to provide a separate apparatus for performing the treatment after the etching.

Further, as another processing method after dry etching, for example, in addition to the structure of claim 10, dry etching and a plasma surface after this dry etching are provided. The processing is performed continuously in separate chambers. This method is a processing method using a so-called multi-chamber type dry etching apparatus, or a processing method using a so-called in-line type dry etching apparatus.

According to the above configuration, the chamber for performing the plasma surface treatment after the dry etching can be filled with the gas for the plasma surface treatment in advance, so that the plasma surface treatment can be performed immediately after the dry etching is completed. it can. As described above, by performing the dry etching and the plasma surface treatment after the dry etching in separate chambers, the evacuation after the dry etching and the gas filling for starting the plasma surface treatment are performed in parallel. Therefore, the time for the entire process can be reduced.

[0051]

BEST MODE FOR CARRYING OUT THE INVENTION

[Embodiment 1] An embodiment of the present invention will be described below with reference to FIGS.
Note that a back channel etching type TFT (hereinafter simply referred to as TFT) is used as the semiconductor element according to the present embodiment.
Will be described.

The TFT is used for an active matrix substrate used in a liquid crystal display device or the like. This active matrix substrate has a structure in which a plurality of signal lines 13 are arranged orthogonally to a plurality of scanning lines 12 arranged in parallel to each other, for example, as shown in FIG.

A pixel electrode 14 is arranged in each rectangular area surrounded by the scanning lines 12 and the signal lines 13. In the vicinity of the intersection between the scanning line 12 and the signal line 13, a TFT 11 functioning as a switching element is formed.

The TFT 11 includes a gate electrode 20 electrically connected to the scanning line 12, a source electrode 60b electrically connected to the signal line 13, and a drain electrode electrically connected to the picture element electrode 14. 60a.

As shown in FIG. 1, the TFT 11 includes a gate electrode 20, a gate insulating film 30, a channel layer 40 as a first semiconductor thin film, and a second semiconductor film on an insulating substrate 10 made of, for example, transparent glass. A contact layer 50 as a thin film, a drain electrode 60a, and a source electrode 60b are sequentially laminated, and the drain electrode 60a and the source electrode 60 are formed.
and a protective layer 70 is formed so as to cover b.

Since the TFT 11 having the above structure is of the back channel etching type as described above, the gap portion 80 between the drain electrode 60a and the source electrode 60b is formed.
Is formed by etching the drain electrode 60a, the source electrode 60b, and the contact layer 50. At this time, since it is difficult to etch only the contact layer 50, the channel layer 40 provided below the contact layer 50 is etched from the surface on the contact layer 50 side to a predetermined thickness. I have.

As described above, when the gap portion 80 is formed by etching, the etched surfaces of the channel layer 40, the contact layer 50, the drain electrode 60a, and the source electrode 60b are damaged by etching, that is, the channel layer 40 which is a semiconductor layer. And the number of defect levels increased due to etching damage such as lattice disorder of the contact layer 50 and desorption of hydrogen. Further, the etching gas element,
Reaction products and the like adhere thereto, and these degrade the electrical characteristics of the TFT 11, particularly the off-current characteristics.

Therefore, in the present embodiment, in the method of manufacturing a semiconductor device described below, the etching gas element, reaction product, and the like remaining when the gap portion 80 is formed are removed, and the characteristics of the TFT 11 are improved. .

Here, a method of manufacturing the TFT 11 will be described below with reference to FIG. Step (I) A gate electrode 20 is formed on an insulating substrate 10 made of a glass substrate.
Is formed (first step). That is, the gate electrode 2
No. 0 is obtained by laminating Al, Mo, Ta, or the like on the insulating substrate 10 by 4500 ° by sputtering and then patterning.

Here, as the insulating substrate 10, in addition to the glass substrate, Ta ₂ O ₅ , SiO ₂
An insulating film such as that formed as a base coat film may be used.

Step (II) A gate insulating film 30 is formed on the gate electrode 20 formed on the insulating substrate 10 so as to cover the gate electrode 20.
Are laminated (second step). In the present embodiment, SiN is formed by a plasma CVD (Chemical Vapor Deposition) method.
The gate insulating film 30 was formed by laminating x films at 3000 °.

In order to enhance the insulating property, the gate electrode 20 is anodized, and this anodic oxide film is used as a first gate insulating film (not shown). May be used as the second gate insulating film.

Step (III) Subsequent to the gate insulating film 30, a first semiconductor film made of amorphous Si serving as the channel layer 40 is laminated by 1500 ° by a CVD method (third step).

Step (IV) Second contact layer 50 is formed on the first semiconductor film.
Are successively laminated (fourth step). That is,
The second semiconductor film is obtained by laminating amorphous Si or microcrystalline Si doped with n + -type impurities (phosphorus or the like) on the first semiconductor film by a plasma CVD method at a thickness of 500 °.

Step (V) Subsequently, the first semiconductor film and the second semiconductor film are
The channel layer 40 and the contact layer 50 are obtained by patterning into an island shape by a dry etching method using a mixed gas of HCl + SF ₆ (fifth step). Here, the gas used in the dry etching method is HCl + SF ₆
The gas mixture is not limited to the mixed gas, and a CF ₄ + O ₂ mixed gas, a BCl ₃ gas, or the like may be used.

The method of etching the first semiconductor film and the second semiconductor film is not limited to the above-described dry etching method.
F + HNO ₃ ) may be used.

Step (VI) On the first semiconductor film and the second semiconductor film patterned in an island shape, a metal thin film of any one of Ta, Ti, Al, ITO and the like is laminated by a sputtering method. Thereafter, patterning is performed to form wirings (not shown) to be the drain electrode 60a and the source electrode 60b (sixth step).

Step (VII) Contact layer 50 on channel region of channel layer 40
Is removed along the gap 80 between the drain electrode 60a and the source electrode 60b by etching to form a contact region (seventh step). At this time, as an etching method, a dry etching method using SF ₆ + HCl mixed gas was used. In this embodiment, a parallel plate type dry etching apparatus shown in FIG. 7 was used as a dry etching apparatus. Details of this device will be described later.

The gas used in the dry etching method is not limited to the above-mentioned HCl + SF ₆ mixed gas, but may be a CF ₄ + O ₂ mixed gas, a BCl ₃ gas or the like.

The above-mentioned etching method is not limited to the above-mentioned dry etching method.
A wet etching method using an etching solution (HF + HNO ₃ or the like) may be used.

Step (VIII) Subsequently, a treatment after the etching (hereinafter referred to as a plasma surface treatment) is performed. Specifically, after the etching in the step (VII) is completed, the etching gas is exhausted with the semiconductor substrate to be etched remaining in the etching chamber. Thereafter, N ₂ gas is introduced into the same chamber as the etching, and the pressure is, for example, 1500 mTorr.
r, N ₂ gas flow rate 1000 sccm, input power 400
W, distance between electrodes 35 mm, temperature 60 ° C., 120
Hold for seconds. At this time, the N ₂ gas is converted into a plasma, and the plasma is used to adsorb and remove an etching gas element and a reaction product attached to the semiconductor substrate.

Here, in the above-mentioned plasma surface treatment, N ₂ gas was used as a plasma gas, but the present invention is not limited to this. H ₂ gas, NH ₃ gas, He gas, O ₂ gas, At least one kind of gas such as Ar may be used.

The details of the plasma surface treatment will be described later.

Step (IX) Finally, a protective layer 70 is formed by stacking and patterning SiNx by the CVD method. The protective layer 7
0 may be a resin insulating film or a two-layer structure including a SiN film and a resin insulating film.

Through the above steps (I) to (IX), the TFT 11 shown in FIG. 1 is completed. The TFT 11 thus completed has the following characteristics.

In order to examine the characteristics of the TFT 11 manufactured as described above, first, the value of the current flowing between the drain electrode 60a and the source electrode 60b is measured.

As shown in FIG. 6, the measuring system is as follows.
A measurement system including a variable voltage generator 2 connected to the gate electrode 20 of the TFT 11 and a voltage generator 4 connected to the drain electrode 60a via the ammeter 3 is used. The source electrode 60b of the TFT 11 is grounded.

In the above measuring system, the variable voltage generator 2 varies the voltage from −20 V to +20 V, and when this voltage (hereinafter, referred to as gate voltage Vg) is applied to the gate electrode 20 of the TFT 11, 60a to the source electrode 60b (hereinafter, the drain current I
d) changes according to the voltage applied to the gate electrode 20 and is sequentially measured by the ammeter 3. At this time, the voltage generated by the voltage generator 4 is applied to the drain electrode 60a.
A fixed voltage of 0 V is applied.

The drain current Id of the TFT 11 of the present invention and that of the conventional TFT were measured at room temperature by the above measurement system. As a result, a Vg-Id curve as shown in FIG. 3 was obtained. In FIG. 3, the processing means, in the present embodiment,
This is a plasma surface treatment for the channel layer 40 and the contact layer 50 after the etching. That is, unprocessed TFT
Indicates a conventional TFT which is not subjected to the plasma surface treatment.
FT.

From the graph of FIG. 3, it can be seen that the processed TFT has a lower off-current value than the unprocessed TFT.

Here, the off current is a current flowing when the gate voltage Vg is lower than the threshold voltage (Vth) of the TFT 11. The above Vth is obtained as follows. For example, in the measurement system shown in FIG. 6, the gate voltage Vg applied by the variable voltage generator 2 is changed from -20V to + 2V.
When the fixed voltage Vsd applied by the voltage generator 4 is 0 V and the fixed voltage Vsd is 10 V, from the Vg-Id curve (graph of FIG. 3) obtained by measuring the drain current Id, Vg> V
In the th region (off-current region), the drain current Id
Is represented by the following equation (2).

Id = １ ／ · μ · C · W / L (Vg−Vth) ² (2) μ: mobility C: gate insulating film capacitance per unit area W / L: TFT Size The above equation (2) can be rewritten as the following equation (3). √Id = √ (１ ／ · C · W / L) · (Vg−Vth) (3) In the above equation (3), a linear region exists in the Vg−√Id curve (not shown). I do. Therefore, the X intercept of the graph represented by the above equation (3) of the approximate curve of this linear region is expressed by Vth
Is determined, the value of Vth is obtained.

In the measuring system shown in FIG.
From the results of measuring the drain current values of the TFT 11 (processed TFT) of the present application at the temperature of 90 ° C. and 90 ° C., and from the results of measuring the drain current values of the conventional TFT (unprocessed TFT) at 30 ° C. and 90 ° C. Vg-I as shown in FIG.
A d-curve was obtained. The definition of processed and unprocessed is the same as the description of the graph of FIG.

FIG. 4 shows that the off-current and the
The on-state current increases, and the rate of increase is slightly higher for the off-state current than for the on-state current.
It can be seen that the rate of increase on the off-current side as compared with T is suppressed.

FIG. 5 is a graph showing the temperature characteristic of the off-state current of the TFT. Here, in FIG.
The treatment is a treatment after etching the channel layer 40 and the contact layer 50 in this embodiment, that is, a plasma surface treatment. That is, the untreated TFT indicates a conventional TFT on which no plasma surface treatment is performed, and
Indicates a TFT of the present invention which has been subjected to plasma surface treatment.

In FIG. 5, each temperature region is a temperature region that can be expressed by activation energy Ea, and Ea is approximately 0.7 to 0.7.
The high temperature region (65 to 90 ° C.) can be expressed by 0.9 eV, the middle temperature region (30 to 65 ° C.) can be expressed by Ea of about 0.3 to 0.5 eV, and Ea is about 0. The low temperature region (30 ° C. or less) can be expressed at 25 eV or less.

FIG. 5 shows that the natural logarithm of the off-current value of the treated TFT is smaller than that of the untreated TFT in any temperature range. That is, processing T
It can be seen that the off current value of the FT is much smaller than that of the untreated TFT.

Therefore, the TF having the characteristics shown in FIG.
It can be seen that the off-state current and the off-side photocurrent can be reduced in the actual operating temperature range of the device using T11.

As a result, the electrical characteristics of the TFT 11 can be improved. That is, the TFT 1 having the above configuration
1 can have a high on-current and a low off-current.

The electric characteristics of the TFT 11 as described above are set as follows. When the gate voltage Vg is T
The subthreshold (subthresh
old) region and corresponds to a region where the drain current is 1E-10 [A] or less (in FIG. 3, the gate voltage Vg is -1 V to -5 V). The leak current (off current) Ids flowing between the first and second electrodes 60a is approximated by the following equation (1). Ids × L / W = Aexp (−Ea / kT) (1) Ea: activation Energy (eV) k: Boltzmann's constant T: temperature (k) W / L: semiconductor element size The value of T in the above equation (1) at the above gate voltage Vg is 3
When the temperature is 03 to 338 [k] (30 to 65 ° C.), the value of A is set to 5E-6 [A] or less. This value of A is
It indicates the amount of defect states (number of defect states) relating to impurities in the semiconductor layer after etching, lattice disorder, and desorption of hydrogen. The smaller this value is, the smaller the leak current (off current) is. .

The value of A is obtained from the graph in the middle temperature range of FIG. 5, and specifically, the value of A is 5E-6 to 5E.
-9 [A]. Therefore, the value of A is 30 when the value of T in the above equation (1) at the gate voltage Vg is 30.
5E-6 at 3 to 338 [k] (30 to 65 ° C)
[A] It can be seen that the following setting is sufficient. The value of A is a value obtained when the above-described plasma surface treatment is performed. If the plasma surface treatment is not performed, 1E-5
[A]. Therefore, it can be seen that the TFT subjected to the plasma surface treatment has a smaller leak current (off current) than the TFT not subjected to the plasma surface treatment.

Therefore, when the TFT 11 of the present embodiment is used for a TFT liquid crystal display, the ratio of the on-current to the off-current of the TFT 11 can be maintained at about 5 digits or more, and the display quality in the TFT liquid crystal display is improved. Can be done.

FIG. 5 shows that when the gate voltage corresponds to the sub-threshold region in the semiconductor device characteristics and the region where the drain current is 1E-10 [A] or less, the gate voltage between the source electrode and the drain electrode is reduced. The leak current Ids flowing therebetween is approximated by the above equation (1), and the value of Ea in the above equation (1) at the above gate voltage is 0.3 to 0.3.
In the region of 0.5 [eV], the value of A is 5E-6.
[A] Even with the following settings, a TFT having characteristics as shown in FIGS. 4 and 5 can be obtained.

A TFT having the characteristics shown in FIG.
In No. 11, the drain voltage is set to 5 to 15V.

Further, the TF having characteristics as shown in FIG.
At T11, the capacitance per unit area of the gate insulating film 30 is set to 1 to 2E-4 [F / m ² ].

The characteristics of the TFT described above are based on (VII
In I), the case where N ₂ gas is used as the gas for plasma surface treatment is described. Hereinafter, the characteristics of the TFT when He gas is used as the gas for plasma surface treatment will be described. This plasma surface treatment is performed by a dry etching apparatus.

In this case, the plasma surface treatment is carried out in such a manner that the pressure in the chamber 105 is 1000 mTorr, the gas flow rate of He gas is 1000 sccm, the input power is 200 W, and the distance between the electrodes is 3
This was performed for 120 seconds under the conditions of 5 mm and a temperature of 60 ° C.

The Vg-Id curve of the TFT subjected to the plasma surface treatment was as shown by a broken line in FIG. In FIG. 11, for comparison, the characteristics of a TFT not subjected to the plasma surface treatment are shown by solid lines.

From the graph of FIG. 11, it can be seen that the sub-threshold region (1 to -6 V) of the TFT and the region (0 V) where the drain current Id is 1E-10 (A) or less.
At a gate voltage Vg corresponding to the following, it was found that the off-state current value of the above-mentioned plasma surface-treated TFT can be reduced as compared with the conventional one.

Here, the plasma surface treatment method in the above-mentioned manufacturing process (VIII) will be described. It is assumed that the plasma surface treatment is continuously performed by the dry etching apparatus used in the manufacturing process (VII).
In the following description, the TFT 11 is replaced with the substrate 101 and the device 102.

First, a dry etching apparatus will be described.

As shown in FIG. 7, the dry etching apparatus is a parallel plate type dry etching apparatus for manufacturing a device 102 such as a TFT on a substrate 101. First electrode 103
And a plate-shaped second electrode 104 which is opposed to and parallel to the first electrode 103.
A chamber 105 for accommodating the second electrode 104;
A high-frequency power supply 107 is connected to the electrode 104 via a matching box 106.

The method of dry etching and the subsequent processing in the above dry etching apparatus will be described below with reference to the flowchart shown in FIG.

First, an etching gas is introduced into the chamber 105 (S1). Generally, as an etching gas,
A mixed gas in which at least two kinds of gases such as SF ₆ , CF ₄ , HCl, Cl ₂ and O ₂ are mixed is used. Here, either a mixed gas of CF ₄ and O ₂ or a mixed gas of HCl and SF ₆ is used.

Next, a discharge (etching) is performed in a state where the etching gas is filled in the chamber 105 (S
2). That is, while the chamber 105 is filled with the etching gas, the high-frequency power from the high-frequency power supply 107 is
The etching gas is led to the second electrode 104 via the matching box 106, the etching gas is turned into a plasma state between the second electrode 104 and the first electrode 103, and the device 102 on the substrate 101 placed on the first electrode 103 is Etching.

The etching conditions in the above S2, that is, the flow rate of the etching gas (gas flow rate), the high frequency power (input power) from the high frequency power supply 107, the internal pressure (pressure) of the chamber 105, and the temperatures of the first electrode 103 and the second electrode 104 (electrode The temperature) and the distance between the first electrode 103 and the second electrode 104 (distance between the electrodes) are as follows. Note that a mixed gas of HCl and SF ₆ is used as an etching gas.

Gas flow rate: HCl 200 to 1000 sccm SF ₆ 200 to 1000 sccm Input power 200 to 1000 W Pressure 150 to 2000 mTorr Electrode temperature Room temperature to 150 ° C. ・ Distance between electrodes ・ ・ ・ ・ 20 to 150 mm Dry etching is performed on the device 102 of the substrate 101 within the range of the above etching conditions. still,
Since the above conditions vary depending on the etching gas, they are appropriately set according to the etching gas.

Next, after completion of the etching, the chamber 10
A vacuum is drawn to exhaust the etching gas and the like in the chamber 5 (S3), and then N ₂ gas is introduced into the chamber 105 until the pressure in the chamber 105 reaches a predetermined value (S4). .

Subsequently, after the pressure in the chamber 105 reaches a predetermined pressure due to the introduction of N ₂ gas, a predetermined high-frequency power is supplied from the high-frequency power supply 107, and plasma surface treatment is performed for 120 seconds (S5). By performing the plasma surface treatment on the substrate 101 and the device 102 immediately after the etching, the substrate 101 and the device 10
2 and the elements of the reaction gas and the etching gas attached to the chamber 105 are removed.

The conditions for the plasma surface treatment here are almost the same as the conditions for the above-described etching treatment, except for the type of gas introduced into the chamber 105.

At S5, the plasma surface treatment time is 1
Although set to 20 seconds, it is not limited to this. That is, the time of the plasma surface treatment is set according to the value of the high-frequency power supplied to the second electrode 104 in the chamber 105. That is, when the value of the applied high frequency power is large, the plasma surface treatment time is set to be short, and when the value of the supplied high frequency power is small, the plasma surface treatment time is set to be long.

Therefore, as described above, the applied power is 2
In the range of 00 to 1000 W, the effect appears from about 15 seconds. However, if the plasma surface treatment time becomes long, the device 102
It is not preferable because it may cause damage.

After the plasma surface treatment, the chamber 105
In order to exhaust the N ₂ gas and the like introduced from the inside, evacuation is performed (S6).

The gas used for the above-mentioned plasma surface treatment is as follows.
A gas having low reactivity with a material or the like forming the substrate 101 or the device 102 is used. For example, in the above-described plasma surface treatment, an N ₂ gas having low reactivity with the substrate 101, the device 102, and the like is used as a treatment gas. However, the present invention is not limited to this, and an inert gas such as Ar or He is used. Alternatively, a gas such as O ₂ may be used.

By the way, the processing after the dry etching, that is, the processing for removing the elements of the etching gas and the reaction products attached to the substrate 101 and the device 102, has conventionally been performed.
It had been removed with acids, alkalis, organic solutions, water and the like. In this case, a special processing apparatus was required in addition to the dry etching apparatus, and a waste liquid processing apparatus for the solution was also required.

On the other hand, in the present embodiment, the processing after dry etching, that is, the substrate 101 and the device 102
The process for removing the etching gas element and the reaction product attached to the is performed in the same dry etching apparatus,
In addition, since the element is removed using a gas having low reactivity with respect to the substrate 101 and the device 102, the substrate 10 and the device 102 are removed.
There is no need to provide a separate processing device for removing elements attached to the device 1 or the device 102, and no special exhaust gas processing device or waste liquid processing device is required.

As a result, the processing time in the dry etching apparatus becomes longer, but the number of steps in the entire processing does not increase.
In addition, the time for the entire process does not increase.

Further, in this embodiment, when the processing after the dry etching is performed, the inside of the chamber 105 does not need to be particularly heated to a high temperature to sufficiently remove the etching gas and the reaction product element adhered to the chamber 105. Since it can be removed, there is no need for a special device such as a high-temperature device as in the conventional case where the chamber is heated to a high temperature to remove the etching gas and reaction product elements attached to the chamber. .

Further, when the chamber is heated to a high temperature to remove the etching gas and reaction product elements attached to the chamber, the processing time takes 10 minutes to 1 hour. In the present embodiment, it takes as long as 10 minutes. Therefore, the processing time can be greatly reduced.

Although the above-mentioned dry etching apparatus is of a parallel plate type, it is not limited to this, and may be an etching apparatus of another structure such as a helicon type.

The above-described plasma surface treatment is performed in the chamber 105 that has been dry-etched. However, the present invention is not limited to this. For example, the etching and plasma surface treatment may be performed in separate chambers. good. As devices for performing the etching process and the plasma surface treatment in separate chambers, there are a multi-chamber type device shown in FIG. 9 and an in-line type device shown in FIG.

First, a multi-chamber type apparatus will be described below with reference to FIG. In FIG. 9, symbols “-” indicate a substrate 101 and a device 1 to be processed.
02 is a symbol indicating the order of the moving route.

The multi-chamber type apparatus includes a first chamber 111 for performing an etching process, a second chamber 112 for performing a plasma surface treatment, and a third chamber 113 for vacuum transfer and vacuum substrate storage. . The first chamber 111 and the second chamber 112 are the same as those shown in FIG.
Has the same structure as the inside of the chamber 105 shown in FIG. therefore,
The member names and member numbers used in FIG. 7 are used as they are.

First, the substrate 101 and the device 102
As shown in FIG. 9, the object (hereinafter referred to as an object to be processed) is transferred to the third chamber 113 in a vacuum state (),
The wafer is conveyed to the first chamber 111 in this vacuum state ().

Next, a mixed gas of CF ₄ and O ₂ or a mixed gas of HCl and SF is placed in the first chamber 111 in which the object is placed.
_The etching process is performed by introducing any one of the mixed gases of No. ₆ . The etching conditions at this time are the same as those described above.
Same conditions as (VII).

Subsequently, after the completion of the etching process, the first chamber 111 is evacuated, and the object to be processed is transferred to the second chamber 112 via the third chamber 113 (,).

In the second chamber 112, after the object to be processed is transported, N ₂ gas is introduced as a gas for plasma surface treatment, and when the inside of the second chamber 112 reaches a predetermined pressure, the high-frequency power Is supplied to perform plasma surface treatment on the object to be processed. By this plasma surface treatment, an etching gas or an element of a reaction product attached to the etched object is removed. For example, when the object to be processed is a semiconductor element, etching damage, that is, an increase in the number of defect states due to disorder of the lattice of the semiconductor layer or desorption of hydrogen can be reduced. This allows
The off-state current of the semiconductor element can be reduced, and the electrical characteristics of the semiconductor element can be improved.

Lastly, the second chamber 112 is evacuated, and the workpiece subjected to the plasma surface treatment in the second chamber 112 is transferred to the third chamber 113 ().

Although the gas used for the plasma surface treatment was N ₂ gas, it is not limited to this.
For example, an inert gas such as Ar or He or O ₂ gas may be used.

Next, an in-line type device will be described.

As shown in FIG. 10, the in-line type apparatus includes a first chamber 121 for performing an etching process,
And a second chamber 122 for performing a plasma surface treatment. The first chamber 121 and the second chamber 122 are arranged in order from the upstream side to the downstream side in the transport direction of the substrate that is the target of each process. The first chamber 121 and the second chamber 122 have the same structure as the inside of the chamber 105 shown in FIG. Therefore, the member names and member numbers used in FIG. 7 are used as they are.

First, either a mixed gas of CF ₄ and O ₂ or a mixed gas of HCl and SF ₆ is introduced into the first chamber 121, and the substrate 101 and the device 102 (here, referred to as an object to be processed) Is subjected to an etching process. The etching conditions at this time are the same as those described above.
Same conditions as (VII).

Subsequently, after the completion of the etching process, the first chamber 121 is evacuated and the object to be processed is transferred to the second chamber 122.

In the second chamber 122, after the object to be processed is transported, N ₂ gas is introduced as a gas for plasma surface treatment, and when the inside of the second chamber 122 reaches a predetermined pressure, the high-frequency power Is supplied to perform plasma surface treatment on the object to be processed. By this plasma surface treatment, an etching gas or an element of a reaction product attached to the etched object is removed.

Lastly, the second chamber 122 is evacuated to vacuum, and the workpiece subjected to the plasma surface treatment in the second chamber 112 is taken out of the second chamber 122.

The gas used for the plasma surface treatment was N ₂ gas, but is not limited to this.
For example, an inert gas such as Ar or He or O ₂ gas may be used.

As described above, in the present embodiment, when performing post-processing after dry etching, a gas having low reactivity with the substrate 101 or the device 102, for example, N ₂ , A
By performing a plasma surface treatment using r, He, or the like, an element of an etching gas or a reaction product attached to the substrate 101 or the device 102 is removed.

With this, the plasma surface treatment can be continuously performed by the apparatus for performing the dry etching.
It is not necessary to provide a special device for removing an etching gas or a reaction product element attached to the substrate 101 or the device 102.

As described above, when the plasma surface treatment is performed after the etching process in the same etching apparatus, particularly in the same chamber, the toxic gas used in the etching process and the toxic substance generated after the etching process are adsorbed on the substrate or the like. Even so, since the plasma surface treatment is continuously performed, the substrate is not transported in a state where toxic gas or toxic substance is adsorbed. Therefore, toxic gases and toxic substances do not affect the human body.

In general, elements remaining after dry etching may adversely affect the characteristics of the device 102 on the substrate 101. In other words, in the manufacture of a transistor, mobile ions such as F and Cl, elements such as C, and metal elements are raised as the above residual elements, and these elements may reduce the reliability of the device 102. .

However, in this embodiment, after the etching process, the elements of the etching gas and the reaction products are removed by plasma surface treatment using a gas having low reactivity to the substrate or the device. Thus, the reliability of the device can be improved.

[Embodiment 2] The following will describe another embodiment of the present invention. As shown in FIG. 12, a semiconductor element according to the present embodiment has a gate electrode 2 on an insulating substrate 10 made of, for example, transparent glass.
0, a gate insulating film 30, a channel layer 40, a channel protective layer 90, a contact layer 50, a drain electrode 60a, and a source electrode 60b are sequentially laminated.
a and a protective layer 70 is formed so as to cover the source electrode 60b.

In the semiconductor device having the above configuration, the contact region is formed by etching the contact layer 50 along the gap 80 between the drain electrode 60a and the source electrode 60b. At this time, unlike the back channel etching type semiconductor element, the channel layer 40 is prevented from being etched by the channel protection layer 90. Therefore, the semiconductor element having the above configuration is a channel protection type semiconductor element.

Here, a method of manufacturing the above-described channel protection type semiconductor device will be described below with reference to FIG. Step (I) A gate electrode 20 is formed on an insulating substrate 10 made of a glass substrate.
To form That is, the gate electrode 20 is obtained by laminating Al, Mo, Ta, or the like on the insulating substrate 10 by 4500 ° by sputtering and then patterning.

Here, as the insulating substrate 10, in addition to the glass substrate, Ta ₂ O ₅ , SiO ₂
An insulating film such as that formed as a base coat film may be used.

Step (II) A gate insulating film 30 is formed on the gate electrode 20 formed on the insulating substrate 10 so as to cover the gate electrode 20.
Are laminated. In this embodiment, plasma CVD (Chemi
cal Vapor Deposition) by SiNx film or S
The gate insulating film 30 was formed by laminating an iO ₂ film at 3500 °.

In order to enhance the insulating property, the gate electrode 20 is anodized, and this anodic oxide film is used as a first gate insulating film (not shown). May be used as the second gate insulating film.

Step (III) Subsequent to the gate insulating film 30, a first semiconductor film made of amorphous Si to be a channel layer 40 is laminated by 400 ° by a CVD method. S serving as channel protection layer 90
An iNx film is laminated by 2000 ° by a CVD method. Subsequently, the SiNx film is patterned so that the channel protection layer 90 remains on the channel region of the channel layer 40.

Step (IV) Second contact layer 50 is formed on the first semiconductor film.
Are successively laminated. That is, the second semiconductor film is formed on the first semiconductor film by using amorphous Si or microcrystalline S doped with an n + type impurity (such as phosphorus).
i obtained by laminating 500 ° by a plasma CVD method.

Step (V) Subsequently, the first semiconductor film and the second semiconductor film are
The channel layer 40 and the contact layer 50 are obtained by patterning into an island shape using a dry etching method using a mixed gas of HCl + SF ₆ . Here, the gas used for the dry etching method is not limited to the above-mentioned HCl + SF ₆ mixed gas, but may be a CF ₄ + O ₂ mixed gas, a BCl ₃ gas, or the like.

The method of etching the first semiconductor film and the second semiconductor film is not limited to the above-mentioned dry etching method.
F + HNO ₃ ) may be used.

Step (VI) Further, the contact layer 50 is removed by etching so that the channel protective layer 90 on the channel layer 40 is exposed. At this time, as an etching method, SF ₆ + HCl
A dry etching method using a mixed gas was used. In the present embodiment, as a dry etching apparatus,
The parallel plate type dry etching apparatus shown in FIG. 7 used in the first embodiment was used.

The gas used in the dry etching method is not limited to the above-mentioned HCl + SF ₆ mixed gas, but may be a CF ₄ + O ₂ mixed gas, a BCl ₃ gas or the like.

The above-mentioned etching method is not limited to the above-mentioned dry etching method.
A wet etching method using an etching solution (HF + HNO ₃ or the like) may be used.

Step (VII) Subsequently, a treatment after the etching (hereinafter referred to as a plasma surface treatment) is performed. Specifically, after the etching in step (VII) is completed, the etching gas is exhausted with the semiconductor substrate left in the etching chamber. Thereafter, an N ₂ gas is introduced into the same chamber as the etching, for example, at a pressure of 1500 mTorr and an N ₂ gas flow rate of 10 mTorr.
00sccm, input power 400W, distance between electrodes 35m
m, at a temperature of 60 ° C. for 120 seconds.

Here, in the plasma surface treatment, N ₂
Although gas was used, it is not limited to this, and H
₂ gas, NH ₃ gas, He gas, O ₂ gas, Ar or the like may be used.

The details of the plasma surface treatment will be described later.

Step (VIII) On the first and second semiconductor films patterned in an island shape, a metal thin film of any one of Ta, Ti, Al, ITO and the like is laminated by a sputtering method. Thereafter, patterning is performed to form a wiring 60 to be the drain electrode 60a and the source electrode 60b.

Step (IX) Finally, a protective layer 70 is formed by stacking and patterning SiNx by the CVD method. The protective layer 7
0 may be a resin insulating film or a two-layer structure including a SiN film and a resin insulating film.

Through the above steps (I) to (IX), the semiconductor device shown in FIG. 12 is completed. The semiconductor element completed in this way reduces the number of defect levels by suppressing etching damage such as lattice disorder of the semiconductor layer and desorption of hydrogen by plasma surface treatment after etching, Since plasma surface treatment is performed after etching to remove elements of the etching gas and reaction products which affect the characteristics of the semiconductor element, the characteristics are the same as those of the first embodiment.

That is, the same effect as the semiconductor element of the first embodiment (back-channel etching type TFT), such as a reduction in off-current, can be achieved in the semiconductor element (channel protection type TFT) having the above configuration. Play.

[0162]

As described above, the semiconductor device according to the first aspect of the present invention comprises at least a gate, a source, and a drain electrode, a gate insulating film, a first semiconductor thin film forming a channel region, and the first semiconductor thin film. In a semiconductor device comprising a second semiconductor thin film directly connected to a semiconductor thin film and formed between the source and drain electrodes and the first semiconductor thin film and doped with n + impurities, the gate voltage may be reduced by the semiconductor device. Sub-threshold region in the characteristics and
When the drain current corresponds to a region of 1E-10 [A] or less, the leak current Ids flowing between the source electrode and the drain electrode is approximated by the following equation (1), and Ids × L / W = Aexp (−Ea / kT) (1) Ea: activation energy (eV) k: Boltzmann constant T: temperature (k) W / L: semiconductor element size T value is 303
In the case of ~ 338 [k], the value of A is set to 5E-6 [A] or less.

According to the above configuration, the off-state current and the off-side photocurrent can be reduced in the actual operating temperature range of the device using the semiconductor element.

Accordingly, when the semiconductor element is a TFT, the electrical characteristics of the TFT can be improved.
That is, the ON current of the TFT having the above structure can be increased and the OFF current can be decreased.

A device using this TFT is called TF
In the case of a T liquid crystal display, the ratio between the ON current and the OFF current of the TFT can be secured to about 5 digits or more.
There is an effect that the display quality in the TFT liquid crystal display can be improved.

In the semiconductor device according to the second aspect of the present invention, at least the gate, source, and drain electrodes, the gate insulating film, and the first region forming the channel region are formed as described above.
A semiconductor element comprising: a semiconductor thin film; and a second semiconductor thin film directly connected to the first semiconductor thin film and formed between the source and drain electrodes and the first semiconductor thin film and doped with n + impurities. When the gate voltage corresponds to a sub-threshold region in a semiconductor device characteristic and a region where a drain current is 1E-10 [A] or less, a leak current Ids flowing between the source electrode and the drain electrode is as follows. Ids × L / W = Aexp (−Ea / kT) (1) Ea: activation energy (eV) k: Boltzmann constant T: temperature (k) W / L: semiconductor element size The value of Ea in the above equation (1) at the above gate voltage is 0.
In the range of 3 to 0.5 [eV], the value of A is 5E-
6 [A] or less.

As the TFT, for example, in addition to the structure of claim 1 or 2, like the semiconductor element of claim 3,
A TFT in which the entire region of the second semiconductor thin film corresponding to the gap between the source electrode and the drain electrode and a part of the region of the first semiconductor film corresponding to the gap are removed; That is, a back channel etching type TFT can be suitably used.

The gate voltage is set in the range of -1 to -5 V as in the semiconductor device of the fourth aspect.
The drain voltage is 5 to 5 as in the semiconductor device of claim 5.
It is set in the range of 15V.

The capacitance per unit area of the gate insulating film is, for example, 1 to 2 as in the semiconductor device of claim 6.
E-4 [F / m ² ].

According to the method of manufacturing a semiconductor device of the present invention, as described above, the first step of forming a gate electrode on an insulating substrate and the step of forming a gate insulating film on the gate electrode are performed. A second step, a third step of stacking a first semiconductor thin film having a channel region serving as a semiconductor layer on the gate insulating film, and an n + impurity serving as a contact layer on the first semiconductor thin film. A fourth step of stacking the doped second semiconductor thin film, a fifth step of patterning the first semiconductor thin film and the second semiconductor thin film into a predetermined shape, and forming a source electrode and a drain on the second semiconductor thin film. A sixth step of forming an electrode, and etching the second semiconductor thin film on the channel region of the first semiconductor thin film;
And a seventh step of forming a contact region of the source electrode and the drain electrode, wherein the plasma of a gas having low reactivity with respect to the semiconductor element manufactured at least up to the seventh step, This is a configuration including a step of performing a surface treatment of the semiconductor element.

According to the above arrangement, in the semiconductor device manufacturing process, the plasma of the gas having low reactivity with the semiconductor device manufactured at least up to the seventh step is used.
By performing the surface treatment of the semiconductor element, by etching performed to form a contact region, an etching gas or a reaction product remaining on the semiconductor element to be etched is removed by plasma of the gas, In addition, the number of defect levels which increase due to etching damage such as disorder of a lattice of a semiconductor layer and desorption of hydrogen generated by etching can be reduced.

As a result, there is an effect that the off-current of the semiconductor element can be reduced and the electrical characteristics can be improved.

As the gas for plasma surface treatment, for example, H ₂ , N ₂ , NH ₃ , H
At least one of e, Ar, and O ₂ is used.

According to a ninth aspect of the present invention, as described above, in addition to the configuration of the seventh aspect, the plasma surface treatment is performed immediately after the seventh step. This is a configuration performed in an etching chamber used for an etching process.

According to the above configuration, in addition to the effect of the configuration of claim 7, by performing the etching treatment and the plasma surface treatment in the same etching chamber, an apparatus for plasma surface treatment after etching is separately provided. It is not necessary to provide.
Thereby, there is an effect that the etching gas element and the reaction product adhered to the substrate can be efficiently removed without increasing the number of manufacturing steps.

According to a tenth aspect of the present invention, there is provided a post-dry etching treatment method for removing an etching gas element and a reaction product remaining after dry etching from an object to be etched and a chamber in which etching is performed. In the processing method of (1), a gas having low reactivity with respect to the object to be etched is turned into plasma, and the surface of the object to be etched and the surface of the chamber after dry etching are processed using the plasma gas.

According to the above-described structure, the object to be etched after the dry etching is subjected to the plasma surface treatment using a gas having low reactivity to the object to be etched, so that the etching adhered to the object to be etched after the dry etching. This has the effect that gas elements and reaction products can be removed.

[0178] As such a processing method after the dry etching, specifically, in addition to the constitution of the tenth aspect, like the processing method after the dry etching of the eleventh aspect, the dry etching and the method after the dry etching are performed. There is a method of performing plasma surface treatment continuously in the same chamber. Therefore, by performing the etching treatment and the plasma surface treatment in the same chamber, it is not necessary to separately provide a device for performing the treatment after the etching.

As another processing method after dry etching, for example, in addition to the structure of claim 10, dry etching and a plasma surface after this dry etching are added to the structure of claim 10. Process is performed continuously in separate chambers. This method is a processing method using a so-called in-line type dry etching apparatus or a processing method using a so-called multi-chamber type dry etching apparatus.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a schematic plan view of an active matrix substrate provided with the semiconductor element shown in FIG.

FIG. 3 is a graph showing a relationship between a gate voltage Vg and a drain current Id of the semiconductor device shown in FIG.

4 is a graph showing a relationship between a gate voltage Vg and a drain current Id of the semiconductor device shown in FIG. 1 and a gate voltage Vg and a drain current Id of a conventional semiconductor device.

FIG. 5 is a graph showing a relationship between off-state current and temperature of the semiconductor device shown in FIG.

FIG. 6 is a schematic diagram of a measuring device for measuring the drain current Id shown by the graphs shown in FIGS. 3 and 4.

7 is a schematic configuration diagram of a dry etching apparatus used when manufacturing the semiconductor device shown in FIG.

8 is a flowchart showing a flow of an etching process and a plasma surface treatment performed in the dry etching apparatus shown in FIG.

FIG. 9 is an explanatory view showing another example of the dry etching apparatus used when manufacturing the semiconductor element shown in FIG.

10 is an explanatory view showing still another example of the dry etching apparatus used when manufacturing the semiconductor device shown in FIG.

11 is a graph showing the relationship between the gate voltage Vg and the drain current Id of the semiconductor device having the configuration shown in FIG. 1 when the plasma surface treatment is changed from N ₂ to He.

FIG. 12 is a schematic sectional view of a semiconductor device according to another embodiment of the present invention.

FIG. 13 is a schematic sectional view of a conventional semiconductor device.

FIG. 14 is a schematic sectional view of a conventional semiconductor device.

DESCRIPTION OF SYMBOLS 10 Insulating substrate 11 TFT (semiconductor element) 20 Gate electrode 30 Gate insulating film 40 Channel layer (first semiconductor thin film) 50 Contact layer (second semiconductor thin film) 60a Drain electrode 60b Source electrode 80 Gap

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Katsuhiro Kawai 22-22, Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (72) Inventor Masaya Okamoto 22-22, Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside the corporation

Claims (12)

[Claims] At least a gate, a source, and a drain electrode, a gate insulating film, and a first region for forming a channel region.
A semiconductor element comprising: a semiconductor thin film; and a second semiconductor thin film directly connected to the first semiconductor thin film and formed between the source and drain electrodes and the first semiconductor thin film and doped with n + impurities. The gate voltage is a sub-threshold region in the semiconductor device characteristics and the drain current is 1E-10 [A].
In the case of the following region, the leak current Ids flowing between the source electrode and the drain electrode is approximated by the following equation (1), and Ids × L / W = Aexp (−Ea / kT) (1) Ea: activation energy (eV) k: Boltzmann constant T: temperature (k) W / L: semiconductor element size The value of T in the above equation (1) at the above gate voltage is 303.
A semiconductor element, wherein the value of A is set to 5E-6 [A] or less when the value is up to 338 [k]. 2. A method according to claim 1, wherein at least each of gate, source and drain electrodes, a gate insulating film, and a first region forming a channel region are formed.
A semiconductor element comprising: a semiconductor thin film; and a second semiconductor thin film directly connected to the first semiconductor thin film and formed between the source and drain electrodes and the first semiconductor thin film and doped with n + impurities. The gate voltage is a sub-threshold region in the semiconductor device characteristics and the drain current is 1E-10 [A].
In the case of the following region, the leak current Ids flowing between the source electrode and the drain electrode is approximated by the following equation (1), and Ids × L / W = Aexp (−Ea / kT) (1) Ea: activation energy (eV) k: Boltzmann constant T: temperature (k) W / L: semiconductor element size The value of Ea in the above equation (1) at the above gate voltage is 0.
In the range of 3 to 0.5 [eV], the value of A is 5E-
A semiconductor element characterized by being set to 6 [A] or less. 3. The entirety of a region of the second semiconductor thin film corresponding to a gap between the source electrode and the drain electrode and a part of a region of the first semiconductor film corresponding to the gap are removed. The semiconductor device according to claim 1, wherein: 4. The semiconductor device according to claim 1, wherein said gate voltage is -1 to -5 V. 5. The semiconductor device according to claim 1, wherein the drain voltage is 5V to 15V. 6. The semiconductor device according to claim 1, wherein the capacitance per unit area of the gate insulating film is 1 to 2E-4 [F / m ² ]. 7. A first step of forming a gate electrode on an insulating substrate, a second step of forming a gate insulating film on the gate electrode, and forming a semiconductor layer on the gate insulating film. A third step of laminating a first semiconductor thin film having a channel region of: a fourth step of laminating a second semiconductor thin film doped with an n + impurity serving as a contact layer on the first semiconductor thin film; A fifth step of patterning the first semiconductor thin film and the second semiconductor thin film into a predetermined shape; a sixth step of forming a source electrode and a drain electrode on the second semiconductor thin film; A seventh step of etching the second semiconductor thin film on the channel region to form a contact region for the source electrode and the drain electrode. 7. A method for manufacturing a semiconductor device, comprising: performing a surface treatment on the semiconductor device by plasma of a gas having low reactivity with respect to the semiconductor device manufactured in the steps up to 7. 8. The gas used for the plasma processing is H
_{2, N 2, NH 3,} He, Ar, a method of manufacturing a semiconductor device according to claim 7, wherein the at least one kind of O _2. 9. The semiconductor device according to claim 7, wherein the plasma surface treatment is performed immediately after the seventh step in an etching chamber used for an etching process in the seventh step. Production method. 10. A post-dry etching treatment method for removing an etching gas element and a reaction product remaining after dry etching from an object to be etched and a chamber in which the etching is performed. A plasma etching method, and processing the object to be etched after dry etching and the surface of the chamber using the plasma gas. 11. The post-dry-etching treatment method according to claim 10, wherein the dry-etching and the plasma surface treatment after the dry-etching are continuously performed in the same chamber. 12. The post-dry etching method according to claim 10, wherein the dry etching and the plasma surface treatment after the dry etching are continuously performed in separate chambers.