JPH11354785A - Field effect transistor, semiconductor integrated circuit device comprising the same, and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve large-current driving capacity for a desired substrate effect, by providing a first semiconductor region of a conductive type reversal to that of a semiconductor region so as to surround a channel region side, and also providing a second semiconductor region of a conductive type reversal to the semiconductor region at such position of a semiconductor device as specified depth, for suppressed short-channel effect. SOLUTION: A pocket region (first semiconductor region) 5n is provided below the peak region of impurity concentration of a source region 4s and a drain region 4d so as to surround them. The pocket region 5n is provided near a high-impurity concentration region 4s2 of the source region 4s and a high-impurity region 4d2 of the drain region 4d. An embedded layer (second semiconductor region) 6n is extended so as to overlap the pocket region 5n on the source region 4s side and that on the drain region 4d side as well at a position of specified depth of a semiconductor substrate 1, between the source region 4a and the drain region 4d. Thus, a desired off current is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor, a semiconductor integrated circuit device, and a manufacturing technique thereof.
In particular, MIS • FET (Metal Insulator Semiconducto
r Field Effect Transistor) and a technology effective when applied to a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art Miniaturization of MISFETs is effective not only for improving the degree of element integration but also for improving the element driving capability. . However, on the other hand, the power supply voltage cannot be easily reduced due to compatibility with existing systems, and the rate of decrease is slow, so that the electric field strength inside the device increases, resulting in adverse effects on device characteristics such as short channel effect. Various problems have arisen.

In the short channel effect, the influence of the drain voltage extends directly below the gate electrode as the channel length is reduced, so that the potential on the surface of the semiconductor substrate is reduced, and the fluctuation (decrease) of the threshold voltage and the execution channel This is a phenomenon that causes various adverse effects such as a reduction in length. If the short channel effect becomes more remarkable, the drain current cannot be controlled by the gate voltage, that is, so-called punch-through occurs, and a problem arises in that the leak current between the source and the drain increases.

[0004] As a structure for suppressing such a short channel effect, for example, the following two structures are well known.
First, a semiconductor region having a conductivity type opposite to that of the source region and the drain region is provided at least at and near the bottom corner of each of the source region and the drain region of the MIS transistor on the channel region side (hereinafter, pocket region). Shape). Second, in the channel region between the source region and the drain region of the MIS transistor, the source region and the drain region extend at a predetermined depth from the main surface of the semiconductor substrate in contact with both the source region and the drain region. This is a structure in which a buried layer of a conductivity type opposite to that of the region is provided (hereinafter referred to as a buried layer type).

[0005] The above-mentioned pocket type structure is described in, for example, Japanese Patent Application Laid-Open No. 5-136404.

[0006]

However, the present invention provides:
In a semiconductor integrated circuit device having a MIS transistor, high current driving capability and low power consumption were studied. The following is not a known technique, but is a technique studied by the present inventor, and its outline is as follows. That is, in recent years, in a semiconductor integrated circuit device, a high current driving capability has been realized by depletion of a threshold voltage in a normal operation of a MIS transistor. When the test is performed, the device may be destroyed due to thermal runaway due to a large off-state current.
It has been studied to apply a substrate bias voltage to an IS transistor to enhance its threshold voltage to reduce the off-state current. And
Including such a viewpoint, even in a semiconductor integrated circuit device for ultra-low voltage operation, in order to achieve both high current driving capability and low power consumption, in one semiconductor chip,
Depletion of the threshold voltage of the operating MIS transistor achieves high current driving capability, and application of a substrate bias voltage to the non-operating MIS transistor enhances its threshold voltage. To reduce the off-current by increasing the current.

However, the present inventor has found that when the method is applied to a semiconductor integrated circuit device having a structure for suppressing the above-mentioned short channel effect, there are the following problems. That is, when the first pocket type structure is adopted as the short channel effect suppressing structure, the impurity concentration in the channel region below the center of the gate electrode can be suppressed low, so that high current driving capability and low threshold voltage can be achieved. Although voltage conversion can be realized, there is a problem that the threshold voltage cannot be increased to a desired enhancement side even when a substrate bias voltage is applied because the substrate effect is too small. Further, when the second buried layer structure is employed, a desired substrate effect can be obtained, but there is a problem that the current driving capability is greatly reduced as compared with the case of the pocket structure. .

SUMMARY OF THE INVENTION It is an object of the present invention to provide a technique that can suppress a short channel effect in a field effect transistor, improve a high current driving capability, and obtain a desired substrate effect.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the present invention, in a field-effect transistor, each of a pair of source / drain semiconductor regions provided on a semiconductor substrate with a channel region therebetween surrounds at least a bottom corner on the channel region side and its vicinity. And a first semiconductor region having a conductivity type opposite to that of the pair of semiconductor regions, and a predetermined depth position of the semiconductor substrate at least on a source semiconductor region side between the pair of semiconductor regions. And a second semiconductor region having a conductivity type opposite to that of the pair of semiconductor regions.

Further, according to the present invention, the impurity concentration of the second semiconductor region is lower than the impurity concentration of the first semiconductor region.

Further, in the present invention, when a plurality of field effect transistors having different set threshold voltages are provided on the semiconductor substrate, an electric field whose set threshold voltage is relatively low is provided. The impurity concentration of the first semiconductor region of the effect transistor is lower than the impurity concentration of the first semiconductor region of the field effect transistor having a relatively high set threshold voltage.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. (Note that components having the same functions in all drawings for describing the embodiments are denoted by the same reference numerals.) , And the repeated explanation is omitted).

(Embodiment 1) FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 shows the present invention having a buried layer and the technology without a buried layer. FIGS. 3 to 6 are cross-sectional views of main parts of the semiconductor integrated circuit device shown in FIG.

In the first embodiment, a case will be described in which the present invention is applied to, for example, a surface channel p-channel MIS-FET (hereinafter simply referred to as pMIS). In the first embodiment, the case where the present invention is applied to pMIS will be described. However, the present invention is not limited to this, and may be applied to an n-channel MIS • FET (hereinafter simply referred to as nMIS). .

As shown in FIG. 1, the semiconductor substrate 1 is, for example p ^- consists shape of the silicon single crystal. This semiconductor substrate 1
Is formed with an n-well 2NW having a retrograde well structure, for example. In this n-well 2NW,
For example, phosphorus or arsenic is introduced to set the n-type. On the main surface of the semiconductor substrate 1, for example, a shallow trench buried isolation portion 3 is selectively formed. This separation unit 3
Are, for example, separation grooves 3 dug in the thickness direction of the semiconductor substrate 1.
For example, it is formed by embedding a separation film 3b such as a silicon oxide film in a. The structure of the isolation part 3 is not limited to the shallow groove buried type, but may be variously changed. For example, the isolation part 3 may be formed of a field insulating film by a selective oxidation method.

The above-described pMISQp is formed in the element formation region surrounded by the isolation portion 3. This pM
The power supply voltage of ISQp is, for example, about 1 to 1.8 V, and the gate length is, for example, about 0.15 μm to 0.2 μm. This p
The MISQp has, for example, a salicide structure, and includes a pair of source region 4s and drain region 4d, pocket region (first semiconductor region) 5n, buried layer (second semiconductor region) 6n, source region 4s and drain Area 4d
A gate insulating film 7 formed on the main surface of the semiconductor substrate 1 and a gate electrode 8 formed thereon.

Source region 4s and drain region 4d
Has low impurity concentration regions 4s1, 4d1, high impurity concentration regions 4s2, 4d2, and silicide layers 4s3, 4d3. The low impurity concentration regions 4s1 and 4d1 are regions for mainly suppressing the hot carrier effect, and are provided at planar positions adjacent to the channel region. The high impurity concentration regions 4s2 and 4d2 are provided at plane positions separated from the channel region by the plane width of the low impurity concentration regions 4s1 and 4d1. This high impurity concentration region 4s2,4
The junction depth of d2 is, for example, about 0.15 to 0.17 μm. The low impurity concentration regions 4s1 and 4d1 and the high impurity concentration regions 4s2 and 4d2 are both set to be p-type by introducing boron, for example.
The impurity concentration of 4d1 is higher than that of the high impurity concentration regions 4s2, 4d.
2 lower than that. The silicide layers 4s3 and 4d3 are made of, for example, titanium silicide, and by providing this, the parasitic resistance of the source region 4s and the drain region 4d can be reduced. The symbol 9a represents pMISQ
5 shows a threshold voltage adjustment layer formed in a p channel region. For example, boron difluoride is introduced into the threshold voltage adjusting layer 9a.

The pocket region 5n is a region mainly for suppressing the channel effect, and includes the bottom surface and side surfaces of the source region 4s and the drain region 4d (the low impurity concentration regions 4s1, 4d1 and the high impurity concentration regions 4s2, 4d2). An impurity concentration peak region is provided below the impurity concentration peak regions of the source region 4s and the drain region 4d so as to surround the whole. Thereby, the short channel effect can be suppressed. The pocket region 5n is set to an n-type by introducing phosphorus, for example. The peak concentration of the impurity in the pocket region 5n is, for example, about 1 to 3 × 10 ¹⁸ cm ⁻³ .
The pocket region 5n has at least the high impurity concentration region 4s2 of the source region 4s and the drain region 4d.
May be provided at the bottom corner of the high impurity concentration region 4d2 on the channel region side and in the vicinity thereof.

The buried layer 6n is a region mainly for obtaining a substrate effect, and is provided between the source region 4s and the drain region 4d at a predetermined depth position of the semiconductor substrate 1 at a pocket on the source region 4s side. It is formed to extend so as to overlap both the region 5n and the pocket region 5n on the drain region 4d side. The buried layer 6n is set to the same conductivity type as that of the pocket region 5n by introducing arsenic, for example. However, the impurity concentration of the buried layer 6n is lower than the impurity concentration of the pocket region 5n. The peak concentration of the impurity in the buried layer 6n is, for example, 1 to 4
It is about × 10 ¹⁷ cm ⁻³ . Thereby, pMISQp
Is not significantly reduced by providing the buried layer 6n. The impurity concentration peak position in the buried layer 6n is at a deep position away from the main surface of the semiconductor substrate 1, but is shallower than the junction depth of the source region 4s and the drain region 4d. The projection range is, for example, deeper than about 0.05 μm, and is about 0.08 to about 0.08 μm.
The depth of the lower portion is, for example, about 0.14 μm. Thus, the provision of the buried layer 6n does not significantly increase the junction capacitance.

The gate insulating film 7 has a thickness of 4 to
It is made of a silicon oxide film of about 5 nm. Note that the gate insulating film 7 may be formed of an oxynitride film (SiON). Thus, the generation of interface states in the gate insulating film 7 can be suppressed, so that the hot carrier resistance of the gate insulating film 7 can be improved. Therefore, the reliability of the gate insulating film 7 can be improved. As a method of oxynitriding the gate insulating film 7, for example, NH _{3 is used} when the gate insulating film 7 is formed by oxidation treatment.
A method of performing a high-temperature heat treatment in a gas atmosphere or a NO gas atmosphere, a method of forming a gate insulating film 7 made of a silicon oxide film or the like, and then forming a nitride film on an upper surface thereof, and an ion implantation of nitrogen into the main surface of the semiconductor substrate 1 After the gate insulating film 7
Or a method in which nitrogen is ion-implanted into a polysilicon film for forming a gate electrode, and then a heat treatment is performed to deposit nitrogen on the gate insulating film 7.

The gate electrode 8 is formed by providing a silicide layer 8b such as titanium silicide on a conductor film 8a made of, for example, low-resistance polysilicon. For example, boron is introduced into the conductor film 8a. Also, the silicide layer 8b
Are formed in the same process as the silicide layers 4s3 and 4d3 in the source region 4s and the drain region 4d. However, the structure of the gate electrode 8 is not limited to this, and can be variously changed. For example, a single-layer structure of low-resistance polysilicon or a conductor film made of low-resistance polysilicon such as titanium nitride or tungsten nitride may be used. A polymetal structure in which a metal film such as tungsten is provided via a barrier metal film may be used. When a polymetal structure is employed, the electric resistance of the gate electrode 8 can be greatly reduced. Note that a side wall 10 made of, for example, a silicon oxide film or a silicon nitride film is formed on a side surface of the gate electrode 8.

In such a pMISQp, the threshold voltage during normal operation without application of the substrate bias voltage is set to +0.1 V and depletion. As a result, the threshold voltage when applying the substrate bias voltage (for example, about +1.8 V) could be shifted to -0.13 V, for example, to the enhancement side. FIG. 2 is a graph comparing the substrate effect with and without the buried layer 6n. The substrate effect (threshold voltage change amount ΔVth) when there is no buried layer 6n is only about 0.1 V, whereas in the structure of the first embodiment having the buried layer 6n, Vth is greatly improved to 0.2 or more. In this case, there was almost no difference in drain current depending on the presence or absence of the buried layer 6n. As a result, a desired off-state current can be reduced by applying the substrate bias voltage. That is, in the first embodiment, pMIS
The short channel effect of Qp can be suppressed, the current driving capability can be improved by the depletion operation during normal operation of pMISQp, and the power consumption can be reduced and the element breakdown occurrence rate can be reduced by reducing the off current when pMISQp is not operating. Can be reduced. In addition, Lg in FIG.
(= Lgmin) is, for example, about 0.2 μm.

Next, a method of manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.

First, as shown in FIG. 3, a shallow trench buried type isolation portion 3 is formed in an isolation region of the semiconductor substrate 1, and then the isolation portion 3 is formed on the semiconductor substrate 1 in an element formation region surrounded by the isolation portion. For example, an insulating film 11 made of a silicon oxide film or the like having a thickness of about 20 nm to 30 nm is formed by a thermal oxidation method. The isolation part 3 forms an isolation groove 3a at a predetermined plane position of the semiconductor substrate 1 by an etching method, and then deposits an insulating film made of a silicon oxide film or the like on the upper surface including the isolation groove 3a of the semiconductor substrate 1 by a CVD method or the like. Further, the CMP (Chem) is performed so that the insulating film is left only in the isolation trench 3a.
ical Mechanical Polishing) method.

Subsequently, for example, phosphorus is added to the semiconductor substrate 1.
About 300 to 400 keV, about 1 to 2 × 10 ¹³ cm ⁻² , for example, arsenic is about 150 to 180 keV (projection range is deeper than about 0.05 μm, and about 0.08 to 0.1 μm); × 10 ¹² cm ^-2 order, and, for example, a 2 boron fluoride, about 20~25keV, 1~2 × 10 ¹²
After each ion implantation under the condition of about cm ⁻² , the semiconductor substrate 1 is subjected to a heat treatment, for example, at 950 ° C. for 10 to 20 seconds. As a result, as shown in FIG. 4, an n-well 2NW having a retrograde structure, a buried layer 6n, and a threshold voltage adjusting layer 9a (corresponding to the order of the impurity ion implantation described above) are formed on the semiconductor substrate 1.

Thereafter, after removing the insulating film 11 (see FIG. 3), the semiconductor substrate 1 is subjected to another thermal oxidation treatment, so that the semiconductor substrate 1 has a thickness of, for example, 4 to 5 mm.
A gate insulating film 7 made of a silicon oxide film or the like having a thickness of about nm is formed. Thereafter, a conductor film made of, for example, low-resistance polysilicon is deposited on the main surface of the semiconductor substrate 1 by a CVD method or the like, and is patterned by a photolithography technique and a dry etching technique, as shown in FIG. Then, a conductor film 8a for a gate electrode is formed. The conductor film 8a contains, for example, 2 × 10 ¹⁵ c of boron.
The dose is set at about m ^-2 and introduced.

Next, for example, boron difluoride is added to the semiconductor substrate 1 by using the conductive film 8a for a gate electrode as a mask.
About 10 to 10 keV, about 1 to 3 × 10 ¹⁴ cm ⁻² , for example, phosphorus is added to about 50 to 60 keV, 2 to 4 × 10 ¹³ cm ^−2.
After each ion implantation under the conditions of the order, the semiconductor substrate 1
Is subjected to a heat treatment at 950 ° C. for 10 to 20 seconds. Thus, the low impurity concentration regions 4s1, 4d1 for the source / drain and the pocket region 5n in which the impurity concentration peak position exists deeper than and surrounding the low impurity concentration regions 4s1, 4d1 (corresponding to the order of the impurity ion implantation described above)
To form The impurities for forming the pocket region 5n may be ion-implanted obliquely with respect to the main surface of the semiconductor substrate 1.

Subsequently, an insulating film made of, for example, a silicon oxide film is deposited on the main surface of the semiconductor substrate 1 by a CVD method, and this is etched back by an anisotropic dry etching method or the like. As shown in FIG. 6, a sidewall 10 is formed on the side surface of the gate electrode conductive film 8a. The width of the sidewall 10 is, for example, 0.1 to
It is about 0.15 μm. Thereafter, using the conductor film 8a for the gate electrode and the sidewalls 10 as a mask, for example, boron difluoride is
After ion implantation under the conditions of about × 10 ¹⁵ cm ⁻² , the semiconductor substrate 1 is subjected to a heat treatment at 950 ° C. for 10 to 20 seconds, for example. Thus, source / drain high impurity concentration regions 4s2 and 4d2 are formed.

Thereafter, a metal film such as, for example, titanium is deposited on the main surface of the semiconductor substrate 1 by a sputtering method or the like, and then subjected to a two-stage annealing treatment or the like.
As shown in FIG. 1, silicide layers 4s3, 4d3, 8b made of, for example, titanium silicide are formed on the high impurity concentration regions 4s2, 4d2 and the conductor film 8a. Thereafter, an interlayer insulating film, a connection hole, and a wiring are formed by a normal wiring forming step, and a semiconductor integrated circuit device having pMISQp is manufactured.

According to the first embodiment, the following effects can be obtained.

(1). In addition to suppressing the short channel effect of pMISQp, during normal operation of pMISQp, the current driving capability can be improved by the depletion operation.
When the MIS Qp is not operating, it is possible to reduce the power consumption and the element destruction rate by reducing the off current.

(2) Since the impurity concentration of the buried layer 6n is lower than that of the pocket region 5n, the provision of the buried layer 6n significantly reduces the current drive capability of the pMISQp. Therefore, the effect of the above (1) can be obtained.

(3) By setting the peak position of the impurity concentration of the buried layer 6n at a position shallower than the junction depth of the source region 4s and the drain region 4d, the provision of the buried layer 6n reduces the junction capacitance. The effect of the above (1) can be obtained without a significant increase.

(4) According to the above (1), (2) and (3), pMI
It is possible to promote the improvement of the operation speed of the semiconductor integrated circuit device having SQp.

(5) According to the above (1), the yield and reliability of the semiconductor integrated circuit device having pMISQnp, can be improved.

(6) According to the above (1), it is possible to promote low power consumption of the semiconductor integrated circuit device having the pMISQp.

(Embodiment 2) FIG. 7 is a sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the second embodiment, for example, complementary MIS transistors (so-called CMIS; Compliment
ary MIS) will be described.
In the second embodiment, the case where the structure of the present invention is applied to both nMIS and pMIS constituting CMIS will be described. However, the structure of the present invention may be applied to either nMIS or pMIS. good.

FIG. 7 is a cross-sectional view of a main part of the CMIS structure in the semiconductor integrated circuit device according to the second embodiment. In FIG. 7, nMISQn is on the left and pMISQp is on the right.
Is shown. Since pMISQp is the same as that of the first embodiment, the description of the overlapping portions will be omitted except for the portions that need to be particularly described.

The nMISQn is formed, for example, in a p-well 2PW region having a retrograde well structure.
The p-well 2PW is set to a p-type by introducing boron, for example. The power supply voltage and the gate length of nMISQn are the same as pMISQp. Like nMISQp, the structure of nMISQn is, for example, a salicide structure, and includes a pair of source region 12s and drain region 12d, pocket region (first semiconductor region) 5p, buried layer (second semiconductor region) 6p, , A gate insulating film 7 formed on the main surface of the semiconductor substrate 1 between the source region 12s and the drain region 12d, and a gate electrode 8 formed thereon.

Source region 12s and drain region 12
d denotes the low impurity concentration regions 12s1, 12d1, the high impurity concentration regions 12s2, 12d2, and the silicide layers 12s3, 1
2d3. The function, position (plane and depth) of these regions, the relationship between the impurity concentration and the silicide layer 1
For 2s3,12d3, the constituent materials and effects are p
MISQp low impurity concentration regions 4s1, 4d1, high impurity concentration regions 4s2, 4d2 and silicide layers 4s3, 4d3
Therefore, the description is omitted. This low impurity concentration region 1
2s1,12d1 and high impurity concentration regions 12s2,12d
2 are both set to the n-type by introducing, for example, phosphorus or arsenic. Reference numeral 9b denotes a threshold voltage adjustment layer formed in the channel region of nMISQn. For example, phosphorus or arsenic, and in some cases, boron fluoride is introduced into the threshold voltage adjusting layer 9b.

The pocket region (first semiconductor region) 5p of nMISQn is provided with the same function and the same relative impurity concentration relationship as the pocket region 5n of pMISQp, but the introduced impurity and conductivity type are different from those of the pocket region 5n. For example, boron is introduced and the p-type is set. Further, the pocket region 5p is formed in the low impurity concentration region 12
It is provided so as to surround the bottom of s1 and the side surface on the channel side, and a part thereof overlaps the buried layer (second semiconductor region) 6p. The peak concentration of the impurity in the pocket region 5p is, for example, about 1 to 3 × 10 ¹⁸ cm ⁻³ . The ion implantation energy of the impurity in the step of forming the pocket region 5p is, for example, about 25 to 30 keV, and the dose is
For example, it is about 1-3 × 10 ¹³ cm ⁻² . In this case, the ion implantation energy in the step of forming the pocket region 5n is, for example, about 50 to 60 keV, and the dose is, for example, about 1 to 3 × 10 ¹³ cm ⁻² . The pocket region 5p may be provided at least at the bottom corner of the high impurity concentration region 12s2 of the source region 12s and the high impurity concentration region 12d2 of the drain region 12d on the channel region side and in the vicinity thereof.

The buried layer 6p of nMISQn has pM
Although it is provided with the same mechanism, the same relative positional relationship, and the same relative impurity concentration relationship as the buried layer 6n of the ISQp, the introduced impurities and the conductivity type are different from the buried layer 6n, and for example, indium is introduced and the pocket region 5p is formed. Is set to the same p-type. In this case, the ion implantation energy in the step of forming the buried layer 6p is, for example, 200 to 250 k.
The dose is about eV and the dose is, for example, about 1 to 4 × 10 ¹² cm ⁻² .

However, the impurity concentration of the buried layer 6p is lower than the impurity concentration of the pocket region 5p, like the buried layer 6n. The peak concentration of the impurity in the buried layer 6p is, for example, about 1 to 4 × 10 ¹⁷ cm ⁻³ . Thus, the provision of the buried layer 6p does not significantly reduce the current driving capability of the nMISQn. The impurity concentration peak position in the buried layer 6p is at a deep position away from the main surface of the semiconductor substrate 1, but the source region 12s
At a position shallower than the junction depth of the drain region 12d, and the projection range is, for example, deeper than about 0.05 μm, about 0.08 to 0.1 μm, and the lower depth is, for example, 0.1 μm. It is about 14 μm. Thus, the provision of the buried layer 6p does not significantly increase the junction capacitance. In the second embodiment, as both the nMISQn and the pMISQp, a large value of the substrate effect amount, for example, 0.2 to 0.25 V was obtained.

According to the second embodiment, the following effects can be obtained.

(1) In addition to suppressing the short channel effect of pMISQp and nMISQn, pMISQp and nM
In the normal operation of ISQn, the current driving capability can be improved by the depletion operation. In the case of non-operation of pMISQp and nMISQn, the first embodiment is used.
In this case, the off-state current can be further reduced as compared with the case described above, and the power consumption and the rate of occurrence of element destruction can be further reduced.

(2) Since the impurity concentration of the buried layers 6n and 6p is lower than the impurity concentration of the pocket regions 5n and 5p, the current drive capability of pMISQp and nMISQn is provided by providing the buried layers 6n and 6p. The effect of the above (1) can be obtained without a significant decrease in

(3) Since the peak position of the impurity concentration of the buried layers 6n and 6p is set to a position shallower than the junction depth of the source regions 4s and 12s and the drain regions 4d and 12d, the buried layers 6n and 6p The effect of (1) can be obtained without providing a large increase in the junction capacitance due to the provision of.

(4) According to the above (1), (2) and (3), pMI
It is possible to promote the improvement of the operation speed of the semiconductor integrated circuit device having SQp and nMISQn.

(5) According to the above (1), the yield and reliability of the semiconductor integrated circuit device having pMISQp and nMISQn can be improved.

(6) According to the above (1), it is possible to promote a reduction in power consumption of a semiconductor integrated circuit device having pMISQp and nMISQn.

(Embodiment 3) FIG. 8 is a sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 9 is a semiconductor integrated circuit having a plurality of MIS-FETs having different threshold voltages. FIG. 4 is a graph showing threshold voltage-gate length characteristics of the circuit device.

In the third embodiment, for example, a plurality of Ms with various threshold voltage specifications are provided in one semiconductor chip.
A case in which the present invention is applied to a MIS • FET having a relatively low threshold voltage in a semiconductor integrated circuit device provided with an IS • FET will be described. FIG. 8 shows two types of MISFETs, nMISQnL having a relatively low threshold voltage (right in FIG. 8) and nMISQnH having a relatively high threshold voltage (left in FIG. 8), on the same semiconductor substrate 1. Is shown in FIG.

Since nMISQnL in this case is the same as nMISQn of the second embodiment, the description of the overlapping parts will be omitted except for the parts that need special explanation. On the other hand, nMISQnH is almost the same as nMISQn of the second embodiment except that the buried layer 6p is not formed. However, the threshold voltage adjustment layer 9b and the pocket region
The implantation amount of impurity ions for forming p is different, and nMIS
The impurity concentration of the pocket region 5p of QnH is higher than that of nMI.
It is higher than that of SQnL. As a result, not only a desired substrate effect amount can be ensured at nMISQnL having a relatively low threshold voltage, but also nMISQnL having a relatively low threshold voltage and nMISQnH having a relatively high threshold voltage. Thus, a good threshold voltage-gate length characteristic can be obtained.

This will be described with reference to FIG. In FIG.
NMIS with a high / low threshold voltage specification formed by changing the amount of channel ions (impurity ions for adjusting the threshold voltage) with respect to the amount of impurities to be implanted into the different pocket regions.
Threshold voltage-gate length characteristics of QnH and QnL are shown. In FIG. 9, curves A1 and B2 correspond to nMISQ of FIG.
nH and QnL. Here, curve A1 and curve A
2 has the same amount of ion implantation for the pocket region, and the curves B1 and B2 have the same amount of ion implantation for the pocket region. Further, curves A1 and A2 are better than curve B
The injection amount is higher than 1, B2. From these results (curves A1, A2, B1, B2), if the threshold voltage is lowered in the case where the impurity ion implantation amount in the pocket region is the same, the reverse short channel effect increases or the short channel effect is further suppressed. It is understood that it is done. Therefore, in order to obtain a good threshold voltage-gate length characteristic having the same shape between the high / low threshold voltage specifications, it is necessary to use the MIS / low threshold voltage specification.
It is necessary to relatively reduce the amount of impurity ions implanted in the pocket region in the FET as compared with the MIS • FET of the high threshold voltage specification.

According to the third embodiment, the following effects can be obtained.

(1). NMIS having a relatively low threshold voltage
In QnL, a desired substrate effect can be ensured, the same effect as in the first and second embodiments can be obtained, and nMISQnH having a relatively high threshold voltage and nMISQnL having a relatively low threshold voltage. In both cases, good threshold voltage-gate length characteristics can be obtained.

(2) By setting the impurity concentration of the buried layer 6p lower than the impurity concentration of the pocket region 5p, the current driving capability of the nMISQnL is significantly reduced by providing the buried layer 6p. Therefore, the effect of the above (1) can be obtained.

(3) By setting the peak position of the impurity concentration of the buried layer 6p at a position shallower than the junction depth of the source region 12s and the drain region 12d, the junction capacitance is reduced by providing the buried layer 6p. The effect of the above (1) can be obtained without a significant increase.

(4) According to the above (1), (2) and (3), nMI
It is possible to promote the improvement of the operation speed of the semiconductor integrated circuit device having SQnL.

(5) According to the above (1), the yield and reliability of a semiconductor integrated circuit device having two types of MIS • FETs of nMISQnL and QnH having different threshold voltages can be improved.

(6) According to the above (1), it is possible to promote low power consumption of the semiconductor integrated circuit device having nMISQnL.

(Embodiment 4) FIG. 10 is a sectional view showing a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the fourth embodiment, a case where the structure of the present invention is applied to a CMIS transistor having a finer gate length will be described. In Embodiment 4, nMIS and pM constituting CMIS are used.
The case where the structure of the present invention is applied to both IS will be described, but the structure of the present invention may be applied to either nMIS or pMIS.

FIG. 10 shows that the gate length is, for example, 0.10-0.
The figure shows a case where a buried layer 6p for ensuring a substrate effect is formed in nMISQna of about 15 μm. In addition,
The structure of the nMISQna is the same as that of the nMISQna of the second embodiment.
Since it is the same as Qn, the description of the overlapping part will be omitted except for the part that requires special explanation. Further, the structure of pMIS is the same as that of nMISQna, and the conductivity type of the region formed on the semiconductor substrate 1 is only reversed, so that the description is omitted here.

In this case, in order to suppress the short channel effect, a shallower junction is required in the source region 12s and the drain region 12d. In this case, in order to prevent an increase in the junction capacitance, the buried layer 6p is replaced with the high impurity concentration regions 12s2,1
If an attempt is made to make the junction depth shallower than 2d2, it will be too close to the main surface of the semiconductor substrate 1 and the drain current will be reduced. Therefore, in the fourth embodiment, the buried layer 6p is formed at an appropriate depth that does not adversely affect the drain current, and the buried layer 6p is formed to reduce the junction capacitance.
The other buried layer 13n of the conductivity type opposite to the conductivity type of the high impurity concentration region 12 of the source region 4s and the drain region 4d is formed.
Formed under s2,12d2.

The buried layer 13n is set to an n-type by introducing, for example, phosphorus or arsenic, and has an impurity concentration of, for example, about 1 to 4 × 10 ¹⁷ cm ⁻³ . And
The buried layer 13n is formed in a self-aligned manner by ion implantation simultaneously with the formation of the high impurity concentration regions 12s2 and 12d2 in the source region 12s and the drain region 12d. As a result, a high current drivability and an appropriate substrate effect amount could be secured without increasing the junction capacitance even in the ultra-fine nMISQna. In the fourth embodiment, the gate insulating film 7 is composed of a gate insulating film 7a made of an oxynitride film obtained by lightly nitriding a silicon oxide film and a gate insulating film 7b made of a silicon oxide film or the like thereon. I have. Thereby, the reliability against the hot carrier effect is also improved.

In the fourth embodiment, the same effect as in the second embodiment can be obtained.

(Embodiment 5) FIG. 11 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to still another embodiment of the present invention.

In the fifth embodiment, a case where the structure of the present invention is applied to a CMIS transistor having a finer gate length will be described. FIG. 11 shows a case where a buried layer 6p for ensuring the substrate effect is formed in nMISQnb having a gate length shorter than 0.13 μm, for example. In the structure of the nMISQnb, those having the same functions as those of the nMISQn of the second embodiment are denoted by the same reference numerals, and the description of the overlapping parts will be omitted except for the parts that need to be particularly described. The structure of pMIS is the same as that of nMISQnb, and only the conductivity type of the region formed on the semiconductor substrate 1 is reversed.

In this case, in order to further suppress the short channel effect, the source region 12s and the drain region 12s
d high impurity concentration regions 12s2 and 12d2
On the main surface of the (low impurity concentration regions 12s1, 12d1), silicide layers 12s3, 12d3 made of, for example, cobalt silicide are formed. In order to reduce the junction capacitance, similarly to the fourth embodiment, the low impurity concentration regions 12s1, 12d1 are formed.
The buried layer 13n is formed under the following. Thereby, the ultrafine n
Also in MISQnb, a low junction capacitance, a high current driving capability, and an appropriate substrate effect amount could be secured. In the fifth embodiment, as the gate electrode 8, for example, a metal film 8d made of tungsten or the like is stacked on a conductor film 8a made of low-resistance polysilicon via a barrier metal film 8c made of tungsten nitride or the like. Adopted polymetal structure.
Thereby, the resistance of the gate electrode 8 can be reduced.

Further, for example, a silicon nitride film was used for the sidewall 10, and a cap insulating film 14 made of, for example, a silicon nitride film was formed on the gate electrode. Accordingly, when a connection hole exposing a source region, a drain region, and a well power supply region is formed by etching in an interlayer insulating film made of a silicon oxide film or the like deposited on the main surface of the semiconductor substrate 1, By performing the etching process under such a condition that the etching selectivity between the oxide film and the silicon nitride film is increased, the connection holes can be formed in a self-aligned manner with good alignment. For this reason, miniaturization of the element can be promoted while ensuring reliability.

According to the fifth embodiment, the same effects as those of the second embodiment can be obtained.

(Embodiment 6) FIG. 12 is a sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the sixth embodiment, a so-called SOI device in which a semiconductor layer for forming an element is provided on a buried insulating layer.
(Silicon On Insulator) A case where the present invention is applied to a substrate structure will be described. As shown in FIG. 12, the SOI substrate (semiconductor substrate) 15 is configured by providing a semiconductor layer 15c on a support substrate 15a via a buried insulating layer 15b. The supporting substrate 15a is, for example n ^- comprised the form of a silicon single crystal, on its, for example, a silicon oxide film thin semiconductor layer 15c of element formation through a buried insulating layer 15b made of such as are formed . The semiconductor layer 15c is made of, for example, a silicon single crystal having a thickness of about 0.3 to 0.5 μm,
It has a so-called partially depleted SOI structure. Further, the substrate bias voltage is applied to the supporting substrate 15 under the buried insulating layer 15b.
This is a so-called back bias structure applied from a.

In the thin semiconductor layer 15c for element formation, an isolation groove 16a exposing the buried insulating layer 15b is dug. In the isolation groove 16a, an isolation groove made of, for example, a silicon oxide film or the like is formed. The isolation portion 16 is formed by burying the insulating film 16b. For example, an nMISQnc is formed in the element formation region surrounded by the isolation portion 16. The structure of the nMISQnc is the same as that of the second embodiment.
The description is omitted because it is the same as MISQn. The element applied in the sixth embodiment is not limited to nMIS, but may be pMIS. Further, similarly to the second embodiment, the present invention can be applied to a CMIS transistor. In this case, nM
The present invention may be applied to both IS and pMIS, or the present invention may be applied to only one of them.

According to the sixth embodiment, the same effect as that obtained in the first embodiment can be obtained, and also, a low parasitic capacitance, which is a special effect in the SOI substrate structure, can be realized. Was.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described first to sixth embodiments, and the present invention is not limited thereto. It goes without saying that various changes can be made.

For example, in the first to sixth embodiments,
The case where the low impurity concentration regions of the source region and the drain region are formed by ion implantation and heat treatment has been described. However, the present invention is not limited to this. For example, heat treatment may be performed while impurities are contained in the sidewall. Accordingly, the impurity in the sidewall may be extended and diffused into the semiconductor substrate to form the low impurity concentration region.

In the first to fifth embodiments,
The case where a normal semiconductor substrate formed by slicing a semiconductor ingot formed by a normal crystal growth method has been described.However, the present invention is not limited to this. For example, on a surface of the normal semiconductor substrate, A so-called epitaxial substrate (semiconductor substrate) provided with an epitaxial layer made of silicon single crystal may be used. The thickness of the epitaxial layer is not particularly limited, but is preferably 5 μm or less.

In the above description, the invention made mainly by the present inventor is described in the field of application MIS,
The case where the present invention is applied to a semiconductor integrated circuit device technology having an FET has been described. However, the present invention is not limited to this case. For example, a DRAM (Dynamic Random Access Memor
y), SRAM (Static Random Access Memory) or flash memory (EEPROM; Electrically Era)
Semiconductor integrated circuit device provided with a memory circuit such as a sable programmable ROM), a semiconductor integrated circuit device provided with a logic circuit such as a microprocessor, or a semiconductor integrated circuit provided with the memory circuit and the logic circuit on the same semiconductor substrate Applicable to circuit device technology.

[0084]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the short channel effect of the field effect transistor can be suppressed, and the current driving capability can be improved by the depletion operation during the normal operation of the field effect transistor, and the desired substrate effect can be obtained. Accordingly, when the field-effect transistor is not operating, it is possible to realize a reduction in power consumption and a reduction in the rate of element destruction due to a reduction in off-state current.

(2) According to the present invention, since the impurity concentration of the second semiconductor region is lower than the impurity concentration of the first semiconductor region, the current driving of the field effect transistor is provided by providing the second semiconductor region. The effect of the above (1) can be obtained without a significant decrease in performance.

(3) According to the present invention, the peak position of the impurity concentration in the second semiconductor region is set at a predetermined depth position which is smaller than the junction depth of the source region 4s and the drain region 4d. By providing the semiconductor region, the effect (1) can be obtained without a large increase in the junction capacitance.

(4) According to the present invention, the semiconductor substrate has
When a plurality of field effect transistors having different set threshold voltages are provided, the impurity concentration of the first semiconductor region of the field effect transistor whose set threshold voltage is relatively low is set. Since the upper threshold voltage is lower than the impurity concentration of the first semiconductor region of the field effect transistor, the threshold voltage is relatively high. Good threshold voltage-gate length characteristics can be obtained for both low field effect transistors.

(5) According to the above (1), (2) and (3), it is possible to promote the improvement of the operation speed of the semiconductor integrated circuit device having the field effect transistor.

(6) According to the above (1) and (7), the yield and reliability of the semiconductor integrated circuit device having the field effect transistor can be improved.

(7) According to the above (1), it is possible to promote low power consumption of a semiconductor integrated circuit device having a field effect transistor.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention;

FIG. 2 is a graph comparing the substrate effect between the present invention having a buried layer and the technology having no buried layer.

3 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step thereof;

4 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 3;

5 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 4;

6 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 5;

FIG. 7 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 8 is a sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 9 is a graph showing threshold voltage-gate length characteristics of a semiconductor integrated circuit device having a plurality of MIS • FETs having different threshold voltages.

FIG. 10 is a sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 11 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to still another embodiment of the present invention.

FIG. 12 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to still another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 NW n well 2 PW p well 3 Separation part 3a Separation groove 3b Separation film 4s Source region (semiconductor region) 4s1 Low impurity concentration region 4s2 High impurity concentration region 4s3 Silicide layer 4d Drain region (semiconductor region) 4d1 Low impurity concentration region 4d2 High impurity concentration region 4d3 Silicide layer 5n, 5p Pocket region (first semiconductor region) 6n, 6p Buried layer (second semiconductor region) 7 Gate insulating film 8 Gate electrode 8a Conductive film 8b Silicide layer 9a, 9b Threshold voltage Adjustment layer 10 Sidewall 11 Insulating film 12s Source region (semiconductor region) 12s1 Low impurity concentration region 12s2 High impurity concentration region 12s3 Silicide layer 12d Drain region (semiconductor region) 12d1 Low impurity concentration region 12d2 High impurity concentration region 12d3 Silicide layer 13n Buried Buried layer 1 Reference Signs List 4 cap insulating film 15 SOI substrate (semiconductor substrate) 15a supporting substrate 15b embedded insulating layer 16 separating section 16a separating groove 16b separating insulating film

Claims (9)

[Claims] 1. A pair of source / drain semiconductor regions provided on a semiconductor substrate with a channel region interposed therebetween, and a gate electrode provided on the semiconductor substrate between the pair of semiconductor regions via a gate insulating film. And (a) being provided so as to surround at least a bottom corner of each of the pair of semiconductor regions on the channel region side and the vicinity thereof, and having a conductivity opposite to that of the pair of semiconductor regions. A shaped first semiconductor region;
(B) a second semiconductor region provided at a predetermined depth position of the semiconductor substrate at least on the side of the source semiconductor region between the pair of semiconductor regions and having a conductivity type opposite to that of the pair of semiconductor regions; And a field-effect transistor. 2. The field effect transistor according to claim 1, wherein said second semiconductor region has an impurity concentration of said first semiconductor region.
A field effect transistor having a lower impurity concentration than a semiconductor region. 3. The field effect transistor according to claim 1, wherein an impurity concentration peak position of said second semiconductor region is smaller than a junction depth of said pair of semiconductor regions. 4. A pair of source / drain semiconductor regions provided on a semiconductor substrate with a channel region interposed therebetween, and a gate electrode provided on the semiconductor substrate between the pair of semiconductor regions via a gate insulating film. A semiconductor integrated circuit device provided with a field effect transistor having: (a) at least a bottom corner of each of the pair of semiconductor regions on the channel region side and the vicinity thereof; A first semiconductor region having a conductivity type opposite to that of the pair of semiconductor regions, and (b) a first semiconductor region provided at a predetermined depth position of the semiconductor substrate on at least a side of the source semiconductor region between the pair of semiconductor regions; A semiconductor integrated circuit device, comprising: a pair of semiconductor regions; and a second semiconductor region having an opposite conductivity type. 5. The semiconductor integrated circuit device according to claim 4, wherein an impurity concentration of said second semiconductor region is lower than an impurity concentration of said first semiconductor region. 6. The semiconductor integrated circuit device according to claim 4, wherein an impurity concentration peak position of said second semiconductor region is smaller than a junction depth of said pair of semiconductor regions. . 7. The semiconductor integrated circuit device according to claim 4, wherein the field-effect transistor is an n-channel field-effect transistor or a p-channel field-effect transistor constituting a complementary field-effect transistor. A semiconductor integrated circuit device characterized by at least one of the following. 8. The semiconductor integrated circuit device according to claim 4, wherein when the semiconductor substrate is provided with a plurality of field effect transistors having different set threshold voltages, The impurity concentration of the first semiconductor region of the field-effect transistor having a relatively low threshold voltage is set to the impurity concentration of the first semiconductor region of the field-effect transistor having a relatively high threshold voltage. A semiconductor integrated circuit device characterized by being lower than the above. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein (a) forming the second semiconductor region at a predetermined depth position in a semiconductor substrate. (B) forming a gate insulating film on the main surface of the semiconductor substrate and then forming a gate electrode thereon;
(C) using the gate electrode as a mask, introducing, into the semiconductor substrate, impurities for forming the low impurity concentration regions of the pair of semiconductor regions and the first semiconductor region, and then performing a heat treatment on the semiconductor substrate. Forming a concentration region and a first semiconductor region; and (d) forming a sidewall insulating film on a side surface of the gate electrode, and then using the gate electrode and the sidewall insulating film as a mask, forming the pair of semiconductors on the semiconductor substrate. Forming a high impurity concentration region by introducing heat for forming a high impurity concentration region in the region and then performing heat treatment.