JPH11344949A - Video display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily compensate dispersion of luminance of light emission of a display element. SOLUTION: When a video display section is constituted by plural display elements, compensation data compensating dispersion of luminance of light emission of individual display element are stored in a storing means 60. When a display element is to be driven, this compensation data are supplied to corresponding drivers 34a-34w. Thereby, display can be driven in a state in which dispersion of luminance of light emission is compensated. Even when a display element is exchanged or a luminance level is readjusted, data is updated to a new compensation data, and updated compensation data will do by only being stored in the storing means 60. Therefore, even when a display element is exchanged or a luminance level is readjusted, dispersion of luminance of light emission can be simply compensated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video display device suitable for application to a large video display device and the like. More specifically, a current correction value for correcting a variation in light emission luminance of a plurality of display elements constituting an image display unit is stored in memory, and when these display elements are driven, the image is driven by using the current correction value. This is to make it possible to correct variations in light emission luminance in the display section.

[0002]

2. Description of the Related Art Large-scale image display devices are installed at various outdoor events, outdoor ball games, sports facilities, and the like, and event contents and competition results are displayed on a large-size image display unit (panel or screen). I am trying to do it.

An image display device used for such a purpose is, as shown in FIG.
The video source (event content, competition content, drama program, etc.) transmitted from the video source is supplied to the signal processing device 30 and converted into a signal form suitable for the video display unit 14. 14 to display a desired image. The image display unit 14 has a large screen (for example, 4 m
× 3 m).

[0004] The image display section 14 is an aggregate of a plurality of dots, an example of which is shown in FIG. In the example of FIG. 1, as shown in FIG. 3A, a unit dot (hereinafter referred to as a dot) 16 is constituted by a trio of display elements that emit red R, green G, and blue B, and the dot 16 is composed of p rows and q columns ( (p = q = 4 is exemplified) to form a unit cell 18 (FIG. 2B). Further, this unit cell has m rows and n columns (m = n = 4
Are arranged vertically and horizontally to form a unit unit 20 (C in the same figure). Then, a large-sized video display unit 14 is constructed by assembling the unit units 20.

[0005] In such an image display section 14, for the purpose of obtaining a sufficient luminous luminance, RGB for forming dots is used.
The display elements 16 themselves, which are trios, are driven by independent drivers. Normally, 4 × 4 dots = 4 ×
4 × 3 = 48 display elements are driven by individual drivers.

However, as shown in FIG. 15, even if the unit cell is 4 × 4 = 16 dots, 16 × 3 = 48 dots.
The number of drivers had to be prepared, and the size of the drive circuit had to be increased. As means for solving this problem, by providing switching means for driving two display elements by one driver, the number of drivers can be reduced to one.
A method employing a means for reducing to / 2 has been proposed.

FIG. 16 is a system diagram of a main part showing one example. When one cell is composed of 48 display elements as shown in FIG. 15, one-half, that is, 24 display elements are driven. The driver circuit 32 is configured to perform the operation. Therefore, as shown in the figure, 24 pieces of video data S0 to S23
The latch circuits 33a to 33w for latching the data and the drivers 34a to 34w connected to the subsequent stage
C driver) 32, and each of the drivers 34a-34
The output of w is connected to the corresponding display elements RU0 to RU7 via the switching means 35.

For example, as shown in FIG. 15, n lines and n + 2
Display elements RU0 to RU7, GU0 of the same color in the line
To GU7, BU0 to BU7 (upper element group U) are simultaneously driven, and at the next timing, the remaining n + 1 lines and n + 3
Display elements RL0 to RL7, GL0 of the same color in the line
GL7 and BL0 to BL7 (lower element group L) are simultaneously driven. That is, these display element groups U and L are alternately driven at a predetermined cycle.

One example is shown in FIG. The figure shows a case where the time (1/30 second) of one frame is alternately switched a plurality of times (about 16 times). During this one frame period, the same video data is supplied to the corresponding display element.

[0010]

In the case where the image display section 14 is composed of a plurality of display elements as described above, for example, a light emitting diode element (LED) is used as the display element, although it differs depending on the display element used. In this case, since the light emission luminance varies among the elements, it is necessary to correct the current value for driving the elements in advance so that the light emission luminance of all the display elements used is constant.

As a current correction method, it is conceivable to adjust a constant of a driver for driving a display element. In this case, when a unit cell is replaced, the display element provided in the unit cell is changed. The corresponding driver must be readjusted to obtain a new current correction value. This is very cumbersome.

In view of the above, the present invention has been made to solve such a conventional problem, and is intended to easily set a current correction value for adjusting light emission luminance even when a display element is replaced. A display device is proposed.

[0013]

According to a first aspect of the present invention, there is provided an image display apparatus having a unit cell in which a plurality of display elements are arranged vertically and horizontally. A first memory means for arranging a plurality of the unit cells to form a video display section and storing video data to be supplied to the plurality of display elements, and for correcting variations in light emission luminance of the display elements. And a second memory means for storing the correction data of the above (1), wherein the display element is driven based on the correction data read from the second memory means.

According to the present invention, the correction data (current correction value) for correcting the variation in the light emission luminance of the display element is stored in the second data.
Is stored in the memory means. When the display element is driven, it is driven based on a current correction value related to the display element. Thereby, the plurality of display elements emit light at the same luminance level. When a unit cell or the like is replaced or the brightness of a specific unit cell is readjusted, a new current correction value for the unit cell is updated. By doing so, the brightness of the entire image display unit can be made uniform even when the unit cell is replaced.

The display elements are alternately driven by using the same video data within one frame. In this case, the video data merely reads data stored in the first storage means. It can be processed at high speed.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a case where an embodiment of a video display device according to the present invention is applied to the above-described large-size video display device will be described in detail with reference to the drawings. Therefore, the video display unit constituting the video display device is also the same as that shown in FIG.
As in the conventional example shown in FIG. 4, the RGB trio is configured as one dot 16, and a plurality of these dots are grouped into a unit cell 18.
The large image display unit 14 is configured by arranging the units 20 in which the unit cells are assembled vertically and horizontally.

As the display element, any one of an organic light emitting display element (organic EL), a light emitting diode element (LED), a discharge tube, and a cathode ray tube (CRT tube) is used. The following example is a case where a light emitting diode element is used.

The unit cell 18 is composed of 4 × 4 dots as shown in FIG. When the n lines and the n + 2 lines are the first display element group U and the n + 1 lines and the n + 3 lines are the second display element group L, the first and second display element groups U and L Are alternately driven with a cycle of Thus, the number of drivers for driving the display elements is reduced by half. In the example shown in the figure, the driver circuit 32 is composed of 24 drivers (RGB trios × 8 dots = 24) per cell.

When displaying an image, in this example, 1 is displayed.
The video signal is handled as a 10-bit digital signal so that 024 gradations (0 to 1023 steps) can be expressed.

FIG. 1 shows one signal processing device provided for the unit cell 18. A plurality of the signal processing devices 30 are provided on the back side of the unit unit 20 and used.

In FIG. 1, video data output from a video source such as a VTR 12 is supplied to a pair of memories 41 and 42 constituting a first memory means.
Video data for a frame is stored. That is, in each of the memories 41 and 42, video data (= 8 dots × 2) for the unit cell 18 constituting the two display element groups U and L
Is stored. If one is an odd-numbered frame memory (for example, a RAM configuration) 41, the other is an even-numbered frame memory (RAM configuration) 42.

Therefore, as shown in FIG. 2, a read / write pulse (enable pulse) R / W is generated with reference to the pulse DLD of the frame period (A and B in FIG. 2). Write processing is performed alternately. Therefore, one memory (RAM / A)
41 is in the write mode, the other memory (RA
MB) is controlled to the read mode.

To control these memories 41 and 42, a data read counter 43 is provided. In addition to the basic clock CK, a data read pulse LDa (FIG. 6A) having a frame period is supplied. R
/ W is generated, a carry pulse Pa described later,
Read / write address A for memories 41 and 42
DR and the like are output. The read and write periods of the video data are periods in which the ready pulse RDY synchronized with the synchronization pulse LDb shown in FIG. 6 is at a low level.

In the read mode, the 10-bit width video data read from the memories 41 and 42 is supplied to a shift register 44 including a subsequent latch circuit, and one display element group is controlled using 24 clocks CK. The video data for the 24 display elements that constitute it is latched.

The video data expressed in 10 bits is then subjected to pulse width modulation (Pulse Width modulation) in the next comparator 45.
Modulated) video data (10-bit value) is converted into a comparison output PWMi. Therefore, carry pulse Pa and clock CK are applied to control signal generation circuit 5.
It is supplied to 0 to generate a count output CO.

The control signal generation circuit 50 comprises a plurality of counters 51 to 54 as shown in FIG. The carry pulse Pa and the clock CK are supplied to the first counter 51, and a counter output CO synchronized with the clock CK as shown in FIG. 4 is generated. In the control signal generation circuit 50, a second counter 52 is further provided, and a switching pulse XUL for alternately driving the display element groups U and L by counting the carry pulse CP (FIG. 6E).
Is generated. Further, third and fourth counters 5
Pulses XR and X for driving an RGB trio to be described later in a dot-sequential manner by a third counter 53.
G and XB are respectively generated, and a switching pulse XUL 'for the display element groups U and L used in the dot sequential driving is generated.

The first counter 51 is supplied with a 4-bit luminance level control signal BRT for controlling the luminance level. This brightness level is for manually controlling the brightness level of the entire video display unit 20 according to external light. In this example, the brightness level can be controlled in 16 steps.

The brightness level is controlled by the length of the pulse width cycle. For example, when the brightness level is controlled as shown in FIG. 5A, the unit cycle Th is set longer and the brightness level is controlled. In this case, the unit cycle Tl is set to be short. Since a 4-bit control signal BRT is provided as a factor for controlling the length of the cycle, the maximum value in one cycle is 1024 × 24 clock width. Control signal BRT is externally applied to first memory 41.

The comparator 45 outputs a high level signal until the latched 10-bit data of the video data matches the value of the count output CO. Therefore 10
A comparison output PWMi having a different pulse width as shown in FIG. 6D is obtained according to the value of the bit. The comparison output PWMi obtained by converting the 10-bit data into the length of the pulse width is obtained for the display elements (for 24 display elements). The display element is driven for a time corresponding to the pulse width.

Here, the display elements have different light emission luminance levels even when the same current flows. That is, there are individual variations. In order to absorb (correct) the variation of each display element including the emission color, correction data of each display element, that is, a current correction value is externally given. Therefore, a current correcting memory means (RAM or the like) 60 is provided as a second memory means, and the memory means 6 is externally provided together with the video data.
Current correction data (10-bit configuration) for 48 display elements prepared in advance at 0 is stored. The current correction data is also stored as data corresponding to the display element group. The current correction data is supplied to a shift register 61 including a latch circuit, and the current correction data for 24 elements constituting one display element group is stored. Is latched.

The current correction data is updated when the display element is replaced or readjusted. Also, the memory means 60 is provided because, even when the unit cell 18 is replaced or readjusted as described above, the current correction data for the replaced and readjusted display element is newly set from outside. This is to make it possible.

The current correction data is supplied to the D / A converter 62
Are supplied to the analog correction current values I0, I1,
Are converted to I2,... I23. These correction current values are supplied to the corresponding drivers 34a to 34w. The drivers 34a to 34w are provided with the above-described comparison output PWMi, and are configured so that the drivers operate only while this is at a high level.

Switching means (switching means) 35 is provided between the drivers 34a to 34w and the display element. As described in the conventional example, the switching means 35 connects the upper and lower display elements (for example, a set of display elements RU0 and RL0, hereinafter the same) to a single driver (34a, 34b) in order to reduce the number of drivers to half. ,... 34w).

FIG. 7 shows a specific example of the switching means 35.
In this example, a driver output is switched using a MOS transistor as a semiconductor switching element. That is, as is apparent from FIG. 8, the first display element group U includes eight display elements RU0 to RU3 and RU4 that emit red light.
To RU7 and eight display elements GU0 to GU3 that emit green light.
And GU4 to GU7 and eight display elements B emitting blue light
U0 to BU3 and BU4 to BU7.

Similarly, the second display element group L includes eight display elements RL0 to RL3 and RL4 to RL7 for emitting red light and eight display elements GL0 to GL3 and GL4 to GL4 for emitting green light.
GL7 and eight display elements BL0 to BL3 and BL4 to BL7 that emit blue light.

The display element groups U and L are alternately driven using the corresponding video data (the same data for the same color) during one frame to display a video.

To realize this, the first display element group U
The display element RU0 constituting the second display element group L is connected to the display element RU0 constituting the second display element group L via the transistor SRU0.
0 is connected to the driver 3 via the transistor SRL0.
4a are commonly connected.

The transistors SRU0 and SRL0 are switched by the switching signal XUL. Therefore, when the transistor SRU0 is turned on, the first signal based on the video data S0 corresponding to the display element RU0 as shown in FIGS.
The display element RU0 is time-divisionally driven by the drive current I0 (current corrected). Next, when the other transistor SLU0 is turned on, the first drive current I0 'based on the video data S0' corresponding to the display element RL0.
The display element RL0 (current corrected)
Are driven in a time-division manner. The same configuration is applied to other display elements, and the corresponding display elements GU1, GL1,... BU7, BL7 are switched using the switching signal XUL.

Here, the shift processing and the data latch processing of the video data in the same frame are performed by the memories 41 and 4.
Since only the process of reading data from 2 and shifting or latching it is performed, any of these processes can be performed within a very short period Wa shown in FIG. As a result, even when the cycle of the switching signal XUL is short, there is no problem in capturing the video data, and the display element can be driven in a time-division manner while performing high-speed switching by the switching signal XUL. by this,
Video flicker can be prevented.

Further, in order to correct the variation of the luminance level of each display element, current correction data for obtaining the same luminance level is stored for each display element.
When the display element is driven based on the current correction data, it is possible to not only vary the luminance level within the unit cell, but also to reduce the luminance level of the entire image display unit 14 using a plurality of unit units 20. Variation can be corrected.

FIG. 9 et seq. Show another embodiment according to the present invention.

In the configuration of FIG. 1, a drive current value different for each display element is D / A converted and supplied to a corresponding driver. FIG. 9 shows a modification of this embodiment.

In the example of FIG. 9, the current correction value is stored in the memory 6
It is the same until it is read from 0, shifted by 24, and latched. The latched current correction value is supplied to the multiplier 65 together with the latched video data, and the video data itself is weighted by the current correction value. Thus, the content of the 10-bit video data is changed according to the current correction value. The weighted video data is converted into a pulse width by the comparator 45.

On the other hand, all the drivers 34a to 34w are connected to the constant current source 66, and the weighted comparison output P
The operation period of the drivers 34a to 34w is controlled by WMi. Even in the case of such a configuration, it is possible to perform light emission display by absorbing the variation of each display element.

The example of FIGS. 1 and 9 switches the display element of the same color in the first and second display element groups by the switching signal XUL.
In the above description, the sequential driving method in which the display elements of the same color are driven at the same time while the display elements of the same color are driven alternately. In contrast to this sequential driving method, an image can also be displayed by a dot sequential driving method in which RGB trios are sequentially emitted.

In this case, for example, of the dots located in the same row, the upper dot and the lower dot are driven as a pair. Referring to FIG. 10, for example, in the dot configuration shown in FIG. 8, among the RGB trios forming a pair of dots located above and below, the upper RGB trio (RU)
0, GU0, BU0) are driven in a dot-sequential manner, and in the next cycle, the lower RGB trio (RL0, GL0, BL0) is driven in a dot-sequential manner (FIG. 10D). The remaining pairs are driven in a similar dot-sequential manner. For example, the upper RGB trio (RU3, GU3, B
U3) and the lower RGB trio (RL3, GL3, BL3) are paired and driven sequentially. This is repeated within one frame. The capture of the video data is performed within the low level period Wa of the ready pulse RDY as in the case of FIG.

In order to perform this processing, as shown in FIG.
And second switching means 35 and 70, respectively. The first switching means 35 has three switching elements (SUR0, SGU0, SBU) for each dot.
0), (SUR1, SGU1, SBU1) (SUR
7, SGU7, SBU7), each of which is shown in FIG.
The switching signals XR, XG, and XB shown in FIG.

In order to select each dot 16, a pair of switching elements (SU0, SL0), (SU1,
SL1)... (SU7, SL7) are provided, and are alternately switched by a switching signal XUL '(see FIGS. 3 and 10).

The drive currents IRU0 to IBU0 based on the video data for the upper RGB trio and the lower R
Drive current IRL based on video data for GB trio
0 to IBL0 are supplied to these switching means 35 and 70 as a common driver output. With this configuration, the upper and lower RGB trios can be driven by the same driver as a pair.

That is, with this configuration, since six display elements can be driven by one driver, the number of drivers can be further reduced as compared with the configuration of FIG.

The embodiment shown in FIG. 12 is a further modified example of FIG. 9, and in this example, a configuration capable of realizing a stereoscopic image is shown. In this case, video data for the left eye and video data for the right eye are required. Therefore, these left and right video data are stored in the same memories 41 and 42 as video data for one frame. Therefore, the memory capacity is twice as large as that of FIG.

When the RGB trio is driven in a dot-sequential manner, as shown in FIG. 12, the image data for the left eye is first read out and the display element is driven by using the drive cycle of the upper and lower dots as a unit. In the next cycle, the video data for the right eye is read to drive the display element. This is repeated several times within one frame. People who watch the video use stereoscopic glasses. The stereoscopic eyeglasses alternately open and close the shutters of the left and right eyes in synchronization with the left and right video data of FIG. For example, the shutter of the left eye may be opened when the image for the left eye is displayed.

By doing so, a stereoscopic image can be enjoyed without image flicker. Its configuration is also simple.

[0054]

As described above, according to the present invention, when the video data is stored in the storage means and the video display section is constituted by a plurality of display elements, the correction data for correcting the variation in the light emission luminance of each display element is provided. Is stored in the storage means, and when the display element is driven, the display element is driven using this correction data.

According to this, it is possible to reliably correct the variation in the light emission luminance of the entire image display unit with respect to the image data read at high speed, and to replace the display element or readjust the luminance level. Sometimes it is only necessary to store new correction data for them in the same memory means. Therefore, it is possible to very easily perform the variation correction of the light emission luminance.

Therefore, the present invention is extremely suitable for application to a large-sized image display device composed of a large number of display elements as described above.

[Brief description of the drawings]

FIG. 1 is a system diagram of a main part showing a first embodiment of a signal processing device for one cell constituting a video display device according to the present invention.

FIG. 2 is a diagram showing write and read timings for a memory.

FIG. 3 is a system diagram of a control signal generation circuit.

FIG. 4 is an explanatory diagram of a counter output.

FIG. 5 is an explanatory diagram of luminance adjustment.

FIG. 6 is a timing chart of video display.

FIG. 7 is a configuration diagram of a switching circuit.

FIG. 8 is a diagram showing an RGB trio and a cell configuration.

FIG. 9 is a system diagram of a main part showing a second embodiment of the signal processing device.

FIG. 10 is a timing chart of the image display in FIG.

FIG. 11 is a connection diagram of the switching circuit in FIG. 8;

FIG. 12 is a timing chart when displaying a stereoscopic video.

FIG. 13 is a system diagram of a large-sized image display device.

FIG. 14 is a diagram showing the relationship between RGB trios and cells.

FIG. 15 is an explanatory diagram of a cell and an RGB trio.

FIG. 16 is a connection diagram showing a relationship between a driver and a display element.

FIG. 17 is a diagram illustrating a relationship between switching timing and reading.

[Explanation of symbols]

12 ... video source, 14 ... large display panel, 1
6 ... RGB trio, 18 ... cell, 20 ... unit, 30 ... signal processing device, 34a-34w ...
.Drivers, 35, 70... Switching means, 41, 4
2 ... Memory means, 43 ... Data read counter, 45 ... Comparator, 50 ... Control signal generation circuit, 62 ... D / A converter, RU0-BL7 ... Display element

Claims (14)

[Claims] 1. A video display device in which a plurality of display elements are arrayed vertically and horizontally, a first storage means for storing video data to be supplied to the display elements, and a correction for correcting a variation in emission luminance of the display elements. A video display device, wherein: a second storage unit for storing data; and the display element is driven based on the correction data read from the second storage unit. 2. The image display device according to claim 1, wherein the display element is configured to emit red, green, and blue light. 3. The image display device according to claim 1, wherein the display element is formed of one of an organic light emitting element, a light emitting diode element, a discharge tube, and a cathode ray tube. 4. The video display device according to claim 1, wherein said display element is driven based on a current value corresponding to an analog value of the correction data read from said second storage means. . 5. The video data to be corrected is a digital value, wherein the video data is corrected by correction data read from the second storage means, and the display element is based on the corrected video data. The image display device according to claim 1, wherein the image display device is driven. 6. The video display device according to claim 5, wherein the corrected video data is pulse width modulated, and the driving time of the display element is controlled based on the pulse width. 7. The first storage means comprises a plurality of storage means, wherein video data to be supplied to the plurality of display elements are sequentially stored in units of one frame or one field. The video display device according to claim 1. 8. The first storage means comprises two memories, one of which stores odd one frame or one field of video data, and the other of which stores even one frame or one field of video data. The video display device according to claim 7, wherein video data is stored. 9. The storage means for storing video data supplied to the plurality of display elements in units of one frame or one field, wherein the plurality of display elements are stored in a plurality of display elements. When divided into groups,
2. The video display device according to claim 1, wherein the display element groups are sequentially switched and driven based on video data corresponding to the display element groups read from the first storage unit. 10. The display element group is composed of two display element groups, and the two display element groups are based on video data corresponding to the two display element groups read from the first storage unit. The image display device according to claim 1, wherein the image display devices are alternately driven. 11. The display element is composed of elements that emit red, green, and blue light, and the display element group is composed of display elements for the same emission color, and is sequentially and simultaneously driven for each of the display element groups. 10. The image display device according to claim 9, wherein the image display device is configured to: 12. The display device is constituted by three display devices emitting red, green and blue light as a unit, and driven by sequentially switching the three display devices in accordance with switching of the display device group. The image display device according to claim 9, wherein: 13. The video display device according to claim 1, wherein the video data is video data for stereoscopic display. 14. The video display device according to claim 13, wherein the video data for the left eye and the video data for the right eye are alternately read from the same storage means within the same frame period.