JPH11340206A - Flattening method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flattening method for flattening a surface of a workpiece, at low cost. SOLUTION: A resist 36 is exposed by using a pattern focused only at a lower part 35 with a focus face at the lower part 35 and an out-of-focus face at a higher part 34. An interlayer insulating film 32 is etched with a mask, and after the resist 36 is removed, a surface 38 of the interlayer insulating film 32 is flattened. Even if the whole the resist 36 is exposed without positioning the pattern to a wide-area step part 36, the resist 36 in this pattern can be selectively left at the lower part 35, so that there remains substantially only a local step at the interlayer insulating film 32 after the etching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flattening method for flattening a surface of an object to be processed when manufacturing a semiconductor device or the like.

[0002]

2. Description of the Related Art In the manufacture of semiconductor devices, the resolution of an exposure apparatus used in lithography has been increased in accordance with the miniaturization of design rules. One of the means for increasing the resolution is to increase the numerical aperture of the exposure apparatus. As the value increases, the depth of focus of the exposure apparatus decreases in inverse proportion to the square of the numerical aperture. In order to increase the resolution without reducing the depth of focus, it is necessary to shorten the wavelength of light used in the exposure apparatus and to improve the resist process.

However, at present, the demand for miniaturization precedes the shortening of the wavelength of light used in an exposure apparatus and the progress of improvement of a resist process. Therefore, the surface of the interlayer insulating film is flattened in order to reduce the difference in height of the structure of the semiconductor device to compensate for the shortage of the depth of focus, suppress the defocus, and reliably resolve a fine pattern.

As a method for performing such flattening,
A so-called resist etch-back method of forming a planarizing film such as a resist on the interlayer insulating film and simultaneously etching back the resist and the interlayer insulating film has been adopted. Further, a chemical mechanical polishing method using mirror surface processing of a silicon wafer is also employed, and FIG. 3 shows the apparatus. In this chemical mechanical polishing apparatus, a polishing pad 12 is adhered to a surface of a polishing plate 11, and a polishing plate rotating shaft 13 rotates the polishing plate 11.

A dresser 15 for forming a dressing layer 14 on the surface of the polishing pad 12 faces a part of the polishing pad 12. Diamond 1 on the metal plate of dresser 15
6 and the like are electrodeposited, and the dresser rotating shaft 17 rotates the dresser 15. The polishing slurry supply device 21 has a nozzle 22 extending to the center of the polishing pad 12, and a polishing slurry 23 is supplied from the nozzle 22 onto the polishing pad 12.

A carrier 25 for supporting an object to be processed 24, which is a silicon wafer having an interlayer insulating film formed thereon, also faces the polishing pad 12, and a backing film 26 for bringing the object to be processed 24 into close contact with the carrier 25. It is provided in. The carrier rotation shaft 27 rotates the carrier 25, and the polishing pressure adjusting mechanism 28 applies pressure to the carrier 25.

In order to flatten the surface of the interlayer insulating film in the object to be processed 24 by this chemical mechanical polishing apparatus, the dressing layer 14 is formed on the polishing pad 12 by dressing (grinding) with a dresser 15, and then the polishing plate is formed. Rotating shaft 13
And the carrier rotation shaft 27 is rotated. Then, while the polishing slurry 23 is supplied from the nozzle 22 to the center of the polishing pad 12, the object 24 is pressed against the polishing pad 12 by the polishing pressure adjusting mechanism 28 to polish the surface of the interlayer insulating film.

By the way, when an interlayer insulating film is formed on a silicon wafer on which wirings and the like are formed, the surface of the interlayer insulating film has a wide area due to a local step due to the wiring itself and a difference in wiring density in the plane of the silicon wafer. A step is formed. However, not only the above-described resist etch-back method but also the chemical mechanical polishing method using the apparatus shown in FIG. 3 makes it difficult to sufficiently eliminate a wide area step when flattening the surface of the interlayer insulating film. Therefore, the shortage of the depth of focus of the exposure apparatus cannot be sufficiently compensated.

That is, in order to eliminate a wide area step by the chemical mechanical polishing method, the elasticity of the polishing pad 12 is increased,
It is necessary to increase the relative speed between the polishing pad 12 and the object 24 or to perform both of them. But,
Any of these causes the polishing pad 12 to follow the surface of the object 24 to be warped, thereby reducing the uniformity of polishing within the surface of the object 24. Therefore, it is difficult to sufficiently eliminate a wide area step under the condition of ensuring uniformity of polishing.

In view of the above, a flattening method has been considered in which a wide area step is eliminated by using a chemical mechanical polishing method or the like in combination with another method. FIG. 4 shows a conventional example. In this conventional example, as shown in FIG. 4A, after the wiring 31 is covered with an interlayer insulating film 32, as shown in FIG.
Then, a resist 36 exposing the high part 34 of the third part and covering only the low part 35 is formed.

Next, as shown in FIG.
Only the high portion 34 is etched using the mask 6 as a mask, and then the resist 36 is removed. Then, as shown in FIG. 4D, the interlayer insulating film 32 in which the uneven portions 37 remain is chemically and mechanically polished, and the surface 38 of the interlayer insulating film 32 is flattened.

[0012]

However, in the conventional example shown in FIG. 4, a wide step 3 is formed as shown in FIG.
It is necessary to form a resist 36 that covers only the lower portion 35 of the resist 3 and exposes the higher portion 34.
It is necessary to align the pattern No. 6 with the wide area step 33. However, due to such alignment, the productivity of the lithography process is reduced, and it has been difficult to flatten the surface 38 of the interlayer insulating film 32 at low cost.
Therefore, an object of the invention of the present application is to provide a planarization method capable of planarizing the surface of an object to be processed at low cost.

[0013]

According to a first aspect of the present invention, there is provided a flattening method, wherein a low-level portion of a step of an object to be processed is a focal plane, and a high-level portion of the step is out of the depth of focus. Since the resist on the object to be processed is exposed, the pattern is not resolved at the high part of the step and the contrast is low. Therefore, even if the entire resist is exposed without aligning the pattern with respect to the step of the object to be processed, after the pattern is transferred, almost no resist remains on the high part of the step, and the transferred pattern has The resist can be selectively left at the lower part of the step.

Since the object to be processed is etched using the resist to which the pattern has been transferred as a mask, the upper surface of the high step portion and the low step portion are covered with the resist. The step with the upper surface of the portion can be reduced to a level that can be eliminated by flattening later. For this reason,
Even if the initial step of the object is a wide-area step, if the density of the pattern is set to a certain level or higher, the object does not substantially have a local step after etching.

As a result, after removing the resist, even if the surface of the object to be processed is flattened by a method in which local stepping cannot be eliminated and a wide area step cannot be eliminated, The step can be eliminated from the surface. That is, even if the object to be processed has a wide step and the entire resist is exposed without aligning the pattern with the wide step, the step is eliminated from the surface of the object. Can be.

In the flattening method according to the second aspect, since the width of the pattern for exposing the resist is set to the width of the resolution limit in the exposure, the contrast at the time of exposure is further lowered at a high step portion of the object. For this reason, the possibility that the resist remains at the high part of the step is further reduced, and the process of removing the resist from the high part of the step of the object to be processed before or during etching using the resist as a mask may be small.

In the flattening method according to the third aspect, the amount of etching at the high part of the step of the object to be processed is adjusted by adjusting the density of the pattern for exposing the resist. In addition, the density of the resist remaining at the high part of the step of the object to be processed also increases and decreases, and the amount of etching of the high part of the step decreases during subsequent etching using this resist as a mask. For this reason, it is easy to make the upper surface of the portion where the step is high in the object to be processed and the upper surface of the portion where the step is low the same height by etching.

In the flattening method according to the fourth aspect, a stripe pattern, a dot pattern, or a combination thereof is used as a pattern for exposing the resist, so that a wide area can be efficiently filled with the stripe pattern, and even a narrow area can be filled. The dot pattern can be evenly filled, and the density of the pattern can be easily increased. For this reason, it is possible to make the flattening speed of the portion where the step is high and the portion where the step is low the same level.

In the flattening method according to the fifth aspect, since the object to be processed is etched under the condition that the resist is eroded, even if the resist remains to a certain degree at a high portion of the step of the object after the pattern is transferred, the etching is performed. As a result, the resist at the high part of the step can be completely removed, and the step can be easily eliminated from the surface of the object to be processed.

In the flattening method according to the sixth aspect, at least a portion of the resist to which the pattern has been transferred on the high part of the step of the object to be processed is eroded before etching, so that the object to be processed is transferred after the pattern is transferred. Even if the resist remains on the high part of the step to a certain extent, the resist on the high part of the step can be completely removed by erosion or subsequent etching, and the step can be easily eliminated from the surface of the object to be processed. .

In the flattening method according to the seventh aspect, since the pattern for exposing the resist is made to correspond to at least the lower part of the step of the object to be processed, the resist having the transferred pattern always remains on the lower part of the step. Moreover, even if the pattern corresponds to the high part of the step, almost no resist remains on the high part of the step after the pattern is transferred. For this reason, even if the accuracy of pattern alignment with respect to the step of the object to be processed is low, the upper surface of the portion where the step is high and the upper surface of the portion where the step is low are equal by etching. Easy to adjust to height.

In the flattening method according to the eighth aspect, since the object to be processed is flattened by chemical mechanical polishing, a step can be more accurately eliminated from the surface of the object to be processed.

In the flattening method according to the ninth aspect, the object to be processed is planarized by simultaneously etching back the planarized film formed on the object to be processed after etching and the object to be processed. The step can be eliminated from the surface of the object without being used.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, first and second embodiments of the present invention applied to a planarization method for planarizing the surface of an interlayer insulating film in manufacturing a semiconductor device will be described with reference to FIGS. I will explain while. FIG. 1 shows a first embodiment. In the first embodiment, as shown in FIG. 1A, after a wiring 31 having a height of about 0.6 μm is covered with an interlayer insulating film 32, a resist 36 is applied on the entire surface of the interlayer insulating film 32.

Thereafter, the resolution R is expressed as k ₁ λ / NA, the depth of focus DOF is expressed as k ₂ λ / NA ^2, and the constants k ₁ = 0.4 and k ₂ = 1 determined by the process. 0.0, an exposure wavelength λ = 0.248 μm, a numerical aperture NA = 0.7, and a stripe pattern having a line and space of 0.14 μm with the lower part 35 of the wide area step 33 as a focal plane. The entire resist 36 is exposed with a dot pattern or a combination of these patterns. Then, after this exposure, the resist 36 is developed.

According to the above equation, the depth of focus DOF is 0.50 μm and the low portion 35 of the wide area step 33 is used as the focal plane as described above, so that the height from the low portion 35 is 0.25 μm or more. Is outside the depth of focus. Therefore,
The high part 34 whose height from the low part 35 is about 0.6 μm is outside the depth of focus. Also, from the above equation, the resolution R is set to 0.
Since it is 14 μm, the line and space of 0.14 μm is the resolution limit.

For this reason, the pattern is not resolved in the high part 34 and the contrast is very low. Even if the entire resist 36 is exposed, as shown in FIG.
After the development of Step 6, the resist 36 hardly remains in the high portion 34, and the resist 36 having the transferred pattern is in the low portion 3
5 remains selectively.

Next, as shown in FIG.
Using the mask 6 as a mask, the interlayer insulating film 32 is etched by the height of the wide step 33, that is, by the height of the wiring 31, and then the resist 36 is removed. As a result, the upper surface 41 of the etched portion, which is the high portion 34, and the upper surface 42 of the portion, which was the low portion 35, which was covered with the resist 36 and was not etched, have substantially the same height. Therefore, there is no local step on the surface of the interlayer insulating film 32.

As shown in FIG. 1B, even if the resist 36 slightly remains in the high part 34 after the development, the resist 36 in the high part 34 is initially formed in the etching of the interlayer insulating film 32.
Is also etched at the same time, as shown in FIG.
The shape of the upper surface 41 is hardly affected by the resist 36.

Next, as shown in FIG. 1D, the surface 38 of the interlayer insulating film 32 is subjected to chemical mechanical polishing. At this time, the upper portion 4 of the portion that was the high portion 34
Since the upper surface 42 having a height equal to 1 exists at a high density, the polishing speed of the portion that was the lower portion 35 is close to the polishing speed of the portion that was the higher portion 34. For this reason, the surface 38 of the interlayer insulating film 32 is planarized by chemical mechanical polishing.

If the constant k ₂ and the exposure wavelength λ are made smaller than the above values and the numerical aperture NA is made larger than the above values, the depth of focus DOF becomes further smaller. The contrast is further reduced. Therefore, the possibility that the resist 36 remains on the high portion 34 is further reduced, and the planarization of the surface 38 of the interlayer insulating film 32 is further facilitated. However, DOF is 0.8μ
If it is about m or less, no problem occurs in the actual manufacture of the semiconductor device.

FIG. 2 shows a second embodiment. Also in the second embodiment, as shown in FIGS. 2A and 2B, the same steps as those in the first embodiment are executed until the entire exposure and development of the resist 36. However, in the second embodiment, after that, the resist 36 has a thickness of about 100 nm.
The resist 36 is ashed under the condition of removing. This ashing may be either isotropic or anisotropic.

As a result, as shown in FIG.
4 is less likely to remain the resist 36 than in the first embodiment. Therefore, thereafter, as shown in FIGS. 2D and 2E, the same steps as those in the first embodiment are performed again, but the surface 38 of the interlayer insulating film 32 is flattened more than in the first embodiment. Easy.

In the first and second embodiments described above,
The resist 36 is exposed by a stripe pattern or a dot pattern whose line and space has a resolution limit of 0.14 μm or a combination pattern thereof.
If the pattern is not resolved by the above, a line-and-space pattern wider than the resolution limit or a line wider than the space may be used.

In particular, if the pattern of the line is wider than the space, the upper surface 41 of the high portion 34
Is formed in the lower portion 35 at a density of 50% or more, so that when the surface 38 of the interlayer insulating film 32 is chemically and mechanically polished, the polishing rate of the portion which was the lower portion 35 is increased to the higher portion. Since the polishing rate of the portion which was 34 is closer, the flatness of the surface 38 of the interlayer insulating film 32 is further improved.

If the density of the pattern, that is, the ratio of the line to the entire pattern is increased or decreased, the density of the resist 36 remaining in the high portion 34 after the development is also increased or decreased. The etching amount of the portion 34 decreases and increases. For this reason, it is easy to make upper surface 41 and upper surface 42 uniform by etching.

In the first and second embodiments,
The entire resist 36 is exposed with a stripe pattern or the like.
In other words, the stripe pattern or the like is moved from the lower portion 35 to the higher portion 34 with a width wider than the alignment margin.
The resist 36 may be exposed in a state where the resist 36 is spread out.

In this manner, the resist 36 having the transferred stripe pattern or the like always remains in the lower portion 35.
Moreover, even if the stripe pattern or the like spreads to the high part 34, the resist 36 hardly remains on the high part 34 after development. For this reason, even if the accuracy of alignment of the stripe pattern or the like with respect to the wide area step 33 is low, the upper surface 41 and the upper surface 42 can be easily adjusted to the same height by etching.

In the first and second embodiments described above,
Although chemical mechanical polishing is performed to planarize the surface 38 of the interlayer insulating film 32, the surface 3 is formed by a so-called etch-back method or the like.
8 may be flattened. In the first and second embodiments described above, the invention of the present application is applied to a planarization method for planarizing the surface 38 of the interlayer insulating film 32 in manufacturing a semiconductor device. The present invention can be applied to flattening of a surface other than the insulating film and flattening other than manufacturing of a semiconductor device.

[0040]

According to the first aspect of the present invention, the object to be processed has a wide step, and the entire resist is exposed without aligning the pattern with the wide step. In addition, since the step can be eliminated from the surface of the object to be processed, the surface of the object to be processed can be flattened at low cost.

In the flattening method according to the second aspect, the process of removing the resist from the high part of the step of the object before or during the etching using the resist as a mask may be small, so that the surface of the object to be processed may be reduced. Can be flattened at a lower cost.

In the flattening method according to the third aspect, the upper surface of the portion where the step is high and the upper surface of the portion where the step is low of the object to be processed are easily made to have the same height by etching. The flattening process after the etching is easy, and the surface of the object to be processed can be flattened at a lower cost.

In the flattening method according to the fourth aspect, the flattening speed can be made substantially equal between the portion having the high step and the portion having the low step on the object to be processed. And the surface of the object can be flattened at a lower cost.

In the flattening method according to the fifth aspect, even if a resist remains to a certain degree at a high portion of a step of the object after pattern transfer, the resist at a high portion of the step is completely removed by etching. As a result, a step can be easily eliminated from the surface of the object to be processed, so that a flattening process after etching is easy, and the surface of the object to be processed can be flattened at a lower cost.

In the flattening method according to the sixth aspect, even if the resist remains to a certain degree at the high portion of the step of the object after the pattern is transferred, the resist at the high portion of the step is completely removed by erosion or subsequent etching. Since the step can be easily eliminated from the surface of the object to be processed, the flattening treatment after the etching is easy, and the surface of the object to be processed can be flattened at a lower cost. .

In the flattening method according to the seventh aspect, even if the accuracy of pattern alignment with respect to the step of the object is low, the upper surface of the portion where the step is high and the low portion of the step are low. Since the upper surface of the portion to be processed is easily adjusted to the same height by etching, the surface of the object to be processed can be flattened at a lower cost.

In the flattening method according to the eighth aspect, since the step can be more accurately eliminated from the surface of the object to be processed, the surface of the object to be processed can be flattened more accurately.

According to the flattening method of the ninth aspect, since the step can be eliminated from the surface of the object without using a new apparatus, the surface of the object can be flattened at a lower cost. it can.

[Brief description of the drawings]

FIG. 1 is a side sectional view showing a first embodiment of the present invention in the order of steps.

FIG. 2 is a side sectional view showing a second embodiment of the present invention in the order of steps.

FIG. 3 is a side view of a chemical mechanical polishing apparatus used for flattening.

FIG. 4 is a side sectional view showing a conventional example of the invention of the present application in the order of steps.

[Explanation of symbols]

24: object to be processed, 33: wide area step (step), 34: high part, 35: low part, 36: resist, 38: surface

Claims (9)

[Claims] A step of applying a resist on an object to be processed having a step, and a pattern which is resolved only in the lower part with the lower part of the step as a focal plane and the higher part of the step outside the depth of focus. A step of exposing the resist, a step of etching the object using the resist to which the pattern is transferred as a mask, a step of removing the resist after the etching, and a surface of the object after the removal And a step of flattening. 2. The flattening method according to claim 1, wherein the width of the pattern is set to a width of a resolution limit in the exposure. 3. The flattening method according to claim 1, wherein an amount of the etching in the high portion is adjusted by adjusting a density of the pattern. 4. The method according to claim 1, wherein a stripe pattern, a dot pattern, or a combination pattern thereof is used as the pattern. 5. The flattening method according to claim 1, wherein the etching is performed under a condition that the resist is eroded. 6. The flattening method according to claim 1, further comprising a step of eroding at least a portion on the high portion of the resist to which the pattern has been transferred before the etching. 7. The method according to claim 1, wherein the exposure is performed in a state where the pattern corresponds to at least the lower part. 8. The method according to claim 1, wherein the planarization is performed by chemical mechanical polishing. 9. The flattening film is formed on the object to be processed after the etching, and the flattening is performed by simultaneously etching back the flattening film and the object to be processed. 2. The flattening method according to 1.