JPH11338776A - External storage subsystem - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an external storage subsystem with which durability against a fault can be made satisfactory and a high-reliability cache function can be provided. SOLUTION: A disk controller 2 interposed between a central processing unit(CPU) 1 and a magnetic disk device 3 is provided with mutually independent plural cache units 80 and 81 and non-volatile memory units 90 and 91. Plural channel units 60 and 61 for controlling the exchange of data with the side of the CPU 1 and plural control units 70 and 71 for controlling the exchange of data with the side of the magnetic disk device 3 are independently connected through respective data buses 60A, 60B, 61A, 61B, 70A and 70B and access lines 80a-80d, 81a-81d, 90a-90d and 91a-91d to plural cache units 80 and 81 and non-volatile memory units 90 and 91.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external storage subsystem, and more particularly, to a technique effective when applied to an improvement in the reliability of an external storage subsystem having a cache function.

[0002]

2. Description of the Related Art For example, in a magnetic disk subsystem used as an external storage device in a general-purpose computer system or the like, a well-known cache memory such as a semiconductor memory is interposed in a part of a disk control device. 2. Description of the Related Art There is known a technology for avoiding a reduction in data transfer speed due to a mechanical factor such as rotation waiting in a magnetic disk device as much as possible.

[0003] With regard to such a cache structure in the disk control device, A Multiport P
age-memory Architecture a
ndA Multiport Disk-Cache
System (New Generation Com
putting 2 (1984) 241-260 OHM
SHA. LTD. and Springer-Vell
As discussed in ag), a method of improving access performance to a cache by dividing the memory into a plurality of memory banks is being studied. Further, as a method of connecting a plurality of memory banks and a channel or a disk controller, an interconnection N is used.
A switch network called an Ework has been proposed.

[0004]

SUMMARY OF THE INVENTION The above prior art aims to improve the cache function by providing a plurality of memory banks and a switch network. In
A switch network system called terconnection network is being studied. However, when implementing a data bus configuration for exchanging data by connecting a plurality of memory banks and a plurality of channel units or a plurality of control units, the switch network system is subject to hardware design restrictions. There was a problem.

No reference is made to multiplexing of cache units constituted by memory banks.

SUMMARY OF THE INVENTION It is an object of the present invention to consider constraints such as a data transfer rate on hardware and a data bus width.
It is an object of the present invention to realize a data bus structure for connecting a plurality of cache units and a plurality of channel units on the host device side or a plurality of control units on the rotary storage device side.

Another object of the present invention is to provide an external storage subsystem which has good reliability against a failure and has a highly reliable cache function.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the present invention relates to an external storage subsystem including a rotary storage device for storing data accessed from a host device and an external storage control device connected to the host device and the rotary storage device. The storage control device includes: a plurality of cache memories that temporarily hold data transmitted and received between the rotary storage device and the host device; and a plurality of channel units that control transmission and reception of data between the host device and the host device. A plurality of control units for controlling the transfer of data to and from the rotary storage device;
A plurality of channel units, a plurality of control units, and a plurality of cache memories are provided with an access path including a plurality of common buses respectively connected thereto.

The present invention also relates to an external storage subsystem including a rotary storage device for storing data accessed from a host device and an external storage control device connected to the host device and the rotary storage device. The storage control device includes a plurality of cache memories for temporarily storing data transmitted and received between the rotary storage device and the higher-level device, and a plurality of channels and a plurality of channels for controlling transmission and reception of data between the higher-level device.
A plurality of control units for controlling data transfer between the unit and the rotary storage device; and a plurality of common buses to which a plurality of channel units, a plurality of control units, and a plurality of cache memories are connected, respectively. And an access path including

In each of the above-described external storage subsystems, the external storage control device includes a plurality of first control processors for controlling a plurality of channel units and a plurality of first control processors for controlling a plurality of control units, respectively. This is a configuration having two control processors.

(Operation) According to the above-described external storage subsystem of the present invention, the cache units (cache memories) are multiplexed, and the access path for the individual cache units by the host device and the rotary storage device. Are independent configurations, so that a combination of multiple cache units and multiple channel units or multiple control units can optimize the data transfer rate and data bus width. it can.

Further, since the cache unit and the access path to the cache unit are multiplexed, the probability that the cache function can be maintained in the event of a failure increases, and the tolerance and reliability of the external storage subsystem against the failure are improved. The quality is definitely improved.

[0015]

(Embodiment 1) An example of an external storage subsystem according to an embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the computer system of this embodiment comprises a central processing unit (CPU) 1 and a disk subsystem. disk·
The subsystem includes a disk control device 2 and a magnetic disk device 3.

The CPU 1 and the disk controller 2 are connected via a plurality of channel interfaces 4, and the disk controller 2 and the magnetic disk device 3 are connected via a plurality of control interfaces 5.

The CPU 1 issues an access command to the disk controller 2 via the channel interface 4, and the disk controller 2 controls the magnetic disk device 3 via the control interface 5 in accordance with a command from the CPU 1. Thus, data reading or writing is controlled.

In the disk controller 2, the channel
A plurality of channel units 60 and 61 operating under the control of the channel control processor 110 and the channel control processor 111 are provided on the connection side of the interface 4. A control operating under the control of the unit control processor 120 and the control unit control processor 121
A unit 70 and a control unit 71 are provided.

An instruction issued from the CPU 1 to the disk control device 2 is received by the channel units 60 and 61, decoded by the channel control processors 110 and 111, and controlled by the control necessary for controlling the magnetic disk device 3. The control unit control processors 120, 1 are passed to the unit control processors 120, 121,
21 controls the magnetic disk drive 3 via the control units 70 and 71.

In the disk controller 2, two independent cache units 80 and 81, which temporarily store data using a semiconductor memory (not shown) as a storage medium, and two independent nonvolatile memories, which are also independent from each other. Memory unit 90 and nonvolatile memory unit 9
1 is equipped. Non-volatile memory units 90, 9
Reference numeral 1 denotes a rewritable memory having the ability to hold data for a certain period of time regardless of the presence or absence of external power supply.

The capacity of each of the cache units 80 and 81 is set, for example, independently to a value that enables a sufficient cache operation in accordance with the storage capacity of the magnetic disk device 3. Similarly, the capacity of each of the non-volatile memory units 90 and 91 is set, for example, independently to a value that enables a sufficient cache operation in accordance with the storage capacity of the magnetic disk device 3.

In this case, the channel unit 60 includes:
A plurality of independent data buses 60A and 60B are provided. On the side of the data bus 60A, the cache unit 8 is connected via an access line 80a.
0 is connected, and the nonvolatile memory unit 91 is independently connected via the access line 91a. The cache unit 81 is connected to the data bus 60B via an access line 81a, and the nonvolatile memory unit 90 is connected to the data bus 60B via an access line 90a.

Similarly, the channel unit 61 includes a plurality of independent data buses 61A and data buses 6A.
1B is provided. The cache unit 80 is connected to the data bus 61A via an access line 80c, and the nonvolatile memory unit 91 is connected via an access line 91c. The cache unit 8 is connected to the data bus 61B via the access line 81c.
1 is connected, and the nonvolatile memory unit 90 is connected via the access line 90c.

The control unit 70 includes:
A plurality of independent data buses 70A and 70B are provided. The cache unit 80 is connected to the data bus 70A via an access line 80b, and the nonvolatile memory unit 91 is connected via an access line 91b. The cache unit 8 is connected to the data bus 70B via the access line 81b.
1 is connected, and the nonvolatile memory unit 90 is connected via the access line 90b.

Similarly, the control unit 71 has a plurality of independent data buses 71A and data buses 71A.
A bus 71B is provided. The cache unit 8 is connected to the data bus 71A via an access line 80d.
0 is connected, and the nonvolatile memory unit 91 is connected via the access line 91d. Data bus 71B
Is connected to a cache unit 81 via an access line 81d, and is connected to a nonvolatile memory unit 90 via an access line 90d.

That is, in the configuration of this embodiment, the channel units 60 and 61 and the control unit 7
Each of 0 and 71 can access the cache units 80 and 81 and the non-volatile memory units 90 and 91 by independent paths.

Hereinafter, an example of the operation of the external storage subsystem of this embodiment will be described.

The write data sent from the CPU 1 to the disk control device 2 is temporarily stored in the channel control processor 110 or 111 in accordance with an instruction from the channel control processor 110 or 111.
Unit 60 or 61 and data buses 60A, 60
B, 61A, and 61B, and are stored in two sets of the cache unit 80 or 81 and the non-volatile memory unit 90 or 91. Thereafter, the cache units 80, 81 are instructed by the control unit control processor 120 or 121.
, Or data from one of the non-volatile memory units 90 and 91 and the data buses 70A to 70A.
The write data is stored in the magnetic disk device 3 via the control unit 1B and the control unit 70 or 71.

On the other hand, the channel control processor 110 or 111, which has received the data read request from the CPU 1 via the channel unit 60 or 61, makes the two cache units 80 or 81 and the non-volatile memory unit 90 or 91 The contents are checked, and if there is data requested by the CPU 1, the cache unit 80
Or 81 or non-volatile memory unit 90 or 91
From one of the data buses 60A to 61B and the channel unit 60 or 61
Send to PU1.

If the data requested by the CPU 1 does not exist in the two cache units 80 or 81 and the non-volatile memory units 90 or 91, the channel control processor 110 or 111 reads the data from the magnetic disk device 3. Notify control unit control processor 120 or 121. The control unit control processor 120 or 121 receiving the data read request from the channel control processor 110 or 111 transmits the request data read from the magnetic disk device 3 to the control unit 70 or 71 and the data buses 70A to 71B. Via either the cache unit 80 or 81.

Control unit control processor 1
The channel control processor 110 or 111, which has received the report of the completion of the storage of the read data to the cache unit 80 or 81 from the storage unit 20 or 121, reports the completion of the data preparation to the CPU 1 and stores the read data in accordance with the instruction of the CPU 1 From the data
The read data is sent to the CPU 1 via the buses 60A to 61B and the channel unit 60 or 61.

FIG. 2 shows channel units 60 and 61 or control units 70 and 71 and a plurality of cache units 80 and 8 in the disk controller 2.
1 shows a signal configuration of a data bus 60A to 71B connecting between the first or non-volatile memory units 90 and 91. In this embodiment, the channel units 60 and 61 or the control units 70 and 71 are the cache units 80 and 81 and the non-volatile memory units 90 and 91.
Perform the master operation. Cache unit 8
0, 81 or the non-volatile memory units 90, 91
The slave operation is performed on the channel units 60 and 61 or the control units 70 and 71.

The channel units 60 and 61 or the control units 70 and 71 are driven by driving the SEL <0-1> signal line to control the cache units 80 and 8 having two sides.
1 or the non-volatile memory units 90 and 91 are selected. The channel units 60 and 61 or the control units 70 and 71 include a cache unit 80,
81 or the state of the data buses 60A to 71B specified by the combination of the signals illustrated in FIG. 4 of the DTOUT / * DTIN signal line and the CMD / * DTIN signal line when the non-volatile memory units 90 and 91 are selected. I do. The data shown in FIG.
Channel units 60 and 6 according to the bus protocol
1, or exchange of read data, write data, commands, and status between the control units 70 and 71 and the cache units 80 and 81 or the nonvolatile memory units 90 and 91.

As described above, in the external storage subsystem of this embodiment, a plurality of cache units 80 and 8 are provided.
1 and the non-volatile memory units 90 and 91 are provided independently of each other, and furthermore, the channel units 60 and 61 on the central processing unit 1 side and the magnetic disk unit 3
Access to the plurality of cache units 80, 81 and the non-volatile memory units 90, 91 from the side of the control units 70, 71 is performed by the plurality of data buses 60A to 71B and the access lines 80a to 80B.
80d, access lines 81a to 81d, access line 90a
To 90d and the access lines 91a to 91d, so that the data transfer speed and the width of the data bus in each data bus and access line can be set optimally. is there.

The plurality of cache units 80,
81 or one of the nonvolatile memory units 90 and 91 or a plurality of data buses 60A to 71B,
Further, access lines 80a to 80d, access line 81a
To 81d, access lines 90a to 90d, access line 91
Even if a failure occurs in any of a to 91d, the cache function can be maintained, and the tolerance to the failure and the reliability of the operation are reliably improved.

(Embodiment 2) FIG. 5 is a block diagram showing an example of the configuration of an external storage subsystem according to another embodiment of the present invention.

In the case of the second embodiment, each of the plurality of cache units 80 and 81 and the non-volatile memory units 90 and 91 is connected to the plurality of data buses 8 respectively.
0A, data bus 80B and data bus 81A,
Data bus 81B and data bus 90A, data bus 90B, data bus 91A, data bus 91
B, and the channel units 60 and 61 and the control unit 7 for each of these data buses.
0, 71 are access lines 60a-60d, access line 6
1a to access line 61d, access lines 70a to 70d, and access lines 71a to 71d.

In this case, the same effect as in the first embodiment can be obtained.

(Embodiment 3) FIG. 6 is a block diagram showing an example of the configuration of an external storage subsystem according to still another embodiment of the present invention.

In the third embodiment, two common data buses 200A and 200B are provided.
And for each of them, the channel unit 60
Are connected via an access line 60e and an access line 60f, and the channel unit 61 is connected to the access line 61e,
The control unit 70 is connected via an access line 70e and an access line 70f, the control unit 71 is connected via an access line 71e and an access line 71f, and the cache unit 80 Are connected via an access line 80e and an access line 80f, and the cache unit 81
Are connected via an access line 81e and an access line 81f, and the nonvolatile memory unit 90
e, are connected via an access line 90f, and the nonvolatile memory unit 91 is connected to the access line 91e, the access line 91f.
These are connected independently via f.

In this case, the same effects as in the above embodiments can be obtained.

(Embodiment 4) FIG. 7 is a block diagram showing an example of the configuration of an external storage subsystem which is still another embodiment of the present invention.

In the case of the fourth embodiment, each of a cache unit group 800 and a cache unit group 801 each comprising a plurality of cache units and a non-volatile memory including a plurality of non-volatile memory units. Unit group 900, nonvolatile memory unit group 9
01, and the cache unit groups 800 and 801 and the non-volatile memory unit groups 900 and 901 are divided into data buses 60 g to 60 j and a data bus 61.
g to 61j, the data buses 70g to 70j, and the channel units 60,
It is configured to be connected to the channel unit 61, the control unit 70, and the control unit 71.

In this case, the same effects as in the above embodiments can be obtained.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

[0047]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

According to the external storage subsystem of the present invention,
In the external storage subsystem including the rotary storage device, a plurality of cache units are simply structured with respect to a plurality of channel units on the host device side and a plurality of control units on the rotary storage device side. Can be combined. Therefore, there is an effect of improving the cache function and performance in the disk control device.

Further, according to the external storage subsystem of the present invention, since both the cache unit and the access path to the cache unit are multiplexed, the cache function with good fault tolerance and high reliability is provided. Can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a configuration of an external storage subsystem according to an embodiment of the present invention.

FIG. 2 shows a channel unit or a control unit and a plurality of cache units in a disk controller.
Data between units or non-volatile memory units
FIG. 3 is an explanatory diagram illustrating an example of a bus signal configuration.

FIG. 3 shows read data, write data, commands, and the like between a channel unit or a control unit and a cache unit or a nonvolatile memory unit.
It is a conceptual diagram which shows an example of the data bus protocol at the time of exchanging status.

FIG. 4 is an explanatory diagram showing an example of a data bus mode for specifying a state of a data bus.

FIG. 5 is a block diagram showing an example of a configuration of an external storage subsystem according to another embodiment of the present invention.

FIG. 6 is a block diagram showing an example of a configuration of an external storage subsystem according to still another embodiment of the present invention.

FIG. 7 is a block diagram showing an example of a configuration of an external storage subsystem according to still another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Central processing unit (CPU) (upper device) 2 Disk controller (external storage controller) 3 Magnetic disk device (rotary storage device) 4 Channel interface 5 Control interface 60 Channel unit 60a-60d Access line 60e 60f Access line 60g-60j Data bus (access path) 60A, 60B Data bus (access path) 61 Channel unit 61a-61d Access line 61e, 61f Access line 61g-61h Data bus (access path) 61A, 61B Data bus (access path) 70 Control unit 70a to 70d Access line 70e, 70f Access line 70g to 70j Data bus (access path) 70A, 70B Data bus (access path) 71 Control unit 71a-71d Access line 71e, 71f Access line 71g-71j Data bus (access path) 71A, 71B Data bus (access path) 80 Cache unit (cache memory) 80a-80d Access line 80e, 80f Access Lines 80A, 80B Data bus (access path) 81 Cache unit (cache memory) 81a-81d Access line 81e, 81f Access line 81A, 81B Data bus (access path) 90 Non-volatile memory unit (cache memory) 90a- 90d access line 90e, 90f access line 90A, 90B data bus (access path) 91 non-volatile memory unit (cache memory) 91a to 91d access line 91e, 91 Access lines 91A, 91B Data bus (access path) 110, 111 Channel control processor (first control processor) 120, 121 Control unit control processor (second control processor) 200A, 200B Common data bus (access path) ) 800,801 cache unit group 900,901 nonvolatile memory unit group

Claims (4)

[Claims] 1. An external storage subsystem including: a rotary storage device that stores data accessed from a host device; and an external storage control device that is connected to the host device and the rotary storage device. An external storage control device, a plurality of cache memories that temporarily hold the data transmitted and received between the rotary storage device and the host device, and control of transmission and reception of the data between the host device and the cache memory; A plurality of channel units; a plurality of control units for controlling transfer of the data between the rotary storage device; a plurality of channel units; a plurality of control units; and a plurality of caches Memory is
An external storage subsystem, comprising: an access path including a plurality of common buses connected to each other. 2. The external storage control device includes: a plurality of first control processors that respectively control the plurality of channel units; and a plurality of second control processors that respectively control the plurality of control units. The external storage subsystem according to claim 1, wherein: 3. An external storage subsystem including: a rotary storage device that stores data accessed from a host device; and an external storage control device connected to the host device and the rotary storage device. An external storage control device, a plurality of cache memories that temporarily hold the data transmitted and received between the rotary storage device and the host device, and control of transmission and reception of the data between the host device and the cache memory; A plurality of channel units; a plurality of control units for controlling transmission and reception of the data between the rotary storage device; a plurality of channel units, the plurality of control units, and the plurality of cache memories; And an access path including a plurality of common buses respectively connected to the external storage subsystem. 4. The external storage control device includes: a plurality of first control processors that respectively control the plurality of channel units; and a plurality of second control processors that respectively control the plurality of control units. The external storage subsystem according to claim 3, wherein: