JPH11338772A - Cache memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease communication between a cache memory related to a temporary variable and an external memory and to contribute to improvement in the performance of a processor. SOLUTION: A data memory 2 is composed of plural cache lines, a tag memory 3 registers the tag address of data, a valid memory 4 stores the valid bit of data and an attribute memory 5 stores an attribute bit showing data are secured as a temporary area not to be reflected with updating in the external memory or not. A hit discriminating means 6 discriminates cache hit by comparing the address index part of data with the tag address in the tag memory 3 and when a temporary area securing instruction and a temporary area releasing instruction are executed, an attribute operating means 7 operates the attribute bit in the attribute memory 5. Based on the attribute bit in the attribute memory 5, a replacing means 8 performs the replacing processing of data when data on the cache line can be replaced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory, and more particularly, to writing back (replacement) data to a real memory (main memory) or a lower cache memory (for example, a secondary cache memory for a primary cache memory). The present invention relates to a cache memory that can be selectively performed.

[0002]

2. Description of the Related Art Conventional microprocessors use a relatively small high-speed cache memory to reduce the average access time to data based on the temporal and spatial locality of access data in a program to be executed. To improve the performance of However, since the cache memory is used as a projection of the memory space of the real memory or the lower cache memory (hereinafter, the real memory or the lower cache memory is collectively referred to as an external memory), data in the cache memory is generally updated. Then, it was always reflected in the external memory in the future. That is, communication from the cache memory to the external memory has been performed.

On the other hand, in a program, there is a variable (hereinafter referred to as a temporary variable) which is generated temporarily, is referred to or updated for a very short time, and thereafter does not need to exist. Generally, a general-purpose register in a microprocessor is used for an area for storing a temporary variable. However, the number of such general-purpose registers is as small as about 256 in a conventional microprocessor, and in some cases, all temporary variables cannot be stored. Had occurred. All temporary variables that cannot be stored in general-purpose registers are temporarily allocated in the cache memory, but the temporary variables stored in these cache memories disappear immediately,
Since the area is allocated in the external memory space, unnecessary communication between the cache memory and the external memory will occur in the future to replace data. This unnecessary communication increases the bus occupancy in a shared bus type multiprocessor system, particularly in a shared bus type multiprocessor system, and causes bus contention, leading to a reduction in the performance of the entire system.

To solve this problem, Japanese Patent Application Laid-Open No. 3-18693 has been proposed.
Japanese Patent Application Laid-Open No. 5 (1999) -2005 provides a configuration in which one data buffer can be used both as a data cache and as a memory at a specific address. As a result, there is a possibility that an area that can be used as a local memory can be controlled without having to communicate with an external memory. However, in this configuration, since the data buffer is used as a memory of a specific address, in a multi-process environment, the region becomes a critical region. There is a risk that proper management is required and performance improvement is hindered. In addition, depending on the characteristics of the program, there is no flexibility in using a large area for storing a temporary variable in some cases and in others not using a large area. Furthermore, when an area that can be used as a memory at a specific address is set, the capacity of the cache memory is reduced or eliminated, and there is a risk that performance improvement will be hindered.

[0005]

A first problem is that, in the conventional cache memory, when an area for a temporary variable is taken in an external memory space at the time of executing a program, the cache memory relating to the temporary variable Unnecessary communication between external memories occurs, which leads to a decrease in processor performance. The reason is that the cache memory is configured as a projection of the external memory space,
This is because, when the value of the temporary variable is changed on the cache memory, all updates of the value are reflected on the external memory.

A second problem is that an area for storing temporary variables is provided in a specific area in the external memory space by a program in order to alleviate the performance degradation caused by the first problem. Even if the time for which the area is stored is increased, other data is replaced by using the cache memory, and it is not necessary to update the area for storing the temporary variable. Is that communication occurs again. The reason is that there is no means for designating whether or not the variable is a temporary variable and whether or not to perform replacement, in the conventional cache memory.

An object of the present invention is to provide a cache memory capable of reducing communication between a cache memory and an external memory relating to temporary variables and contributing to an improvement in processor performance.

[0008]

According to the present invention, there is provided a cache memory having a two-way or more set associative configuration, wherein a temporary area in which data update is not reflected in an external memory is provided for each cache line of the data memory. It can be specified selectively.

A cache memory according to the present invention is a cache memory having a two-way or more set associative configuration, a multiple-way data memory comprising a plurality of cache lines for storing cached data, A multi-way tag memory for registering a tag address of data of the cache line corresponding to each cache line, and a valid bit indicating validity of data of the cache line corresponding to each cache line of the data memory are stored. And a plurality of attribute bits indicating whether or not the cache line is secured as a temporary area that does not reflect the update of data in the external memory in correspondence with each cache line of the data memory. Way attribute memory and access Hit judging means for judging a cache hit by comparing an address index part of data with a tag address of the tag memory; and an attribute of the attribute memory when a temporary area securing instruction and a temporary area releasing instruction are executed. An attribute operating means for operating a bit; and a replacement for determining whether data of a cache line of the data memory can be replaced based on attribute bits of the attribute memory and performing a data replacement process if the replacement is possible. Means.

Further, the cache memory of the present invention has a
In a cache memory having a set associative way configuration, a pair of data memories each including a plurality of cache lines for storing cached data, and a tag address of data of the cache line corresponding to each cache line of the data memories A pair of tag memories, a pair of valid memories storing valid bits indicating validity of data of the cache line corresponding to each cache line of the data memory, and a pair of valid memory corresponding to each cache line of the data memory. A pair of attribute memories for storing attribute bits indicating whether or not the cache line is secured as a temporary area that does not reflect data updates in an external memory; an index portion of an address of data to be accessed; and the tag memory Comparison with the tag address of Hit determining means for determining a cache hit; attribute operating means for operating attribute bits of the attribute memory when a temporary area securing instruction and a temporary area releasing instruction are executed; And a replacement means for determining whether or not the data in the cache line of the data memory can be replaced and performing a data replacement process if the replacement is possible.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit block diagram showing a configuration of a cache memory 1 according to one embodiment of the present invention. A cache memory 1 according to the present embodiment includes a multi-way data memory 2 including a plurality of cache lines for storing cached data, and a multi-way tag for registering tag addresses of data on corresponding cache lines. A memory 3, a plurality of ways of valid memory 4 for storing valid bits indicating the validity of data on the corresponding cache line, and an area for storing temporary variables for each cache line (hereinafter abbreviated as a temporary area) A plurality of ways of attribute memory 5 for storing attribute bits indicating whether or not the data is secured as data, and a hit determination means 6 for determining a cache hit for data to be accessed.
Attribute operation means 7 for registering attribute bits in the attribute memory 5; and determining whether or not data on the cache line can be replaced based on the attribute bits registered in the attribute memory 5, and replacing the data if possible. And a replacement means 8 for performing processing.

In the cache memory 1 according to the present embodiment, a temporary area is explicitly secured and released by a code in a program, a part of the external memory space being explicitly selected in units of cache lines. Hereinafter, the instruction for securing the temporary area is referred to as a temporary area securing instruction (VRSV instruction), and the instruction for releasing the temporary area is referred to as a temporary area release instruction (VREL instruction). The temporary area allocation instruction and temporary area release instruction must be inserted into the object program by the compiler by statically extracting by the compiler that the variables used in the source program are temporary variables. Is desirable.

FIG. 2 is a diagram for explaining a temporary area reservation instruction (VRSV instruction) and a temporary area release instruction (VREL instruction). The temporary area securing instruction and the temporary area releasing instruction are instructions for securing and releasing the cache line as a temporary area using the head address of the cache line in the data memory 2 as an argument. In FIG.
By using the start address 10000 of the cache line A as an argument, the cache line A is secured and released as a temporary area by the VRSV instruction and the VREL instruction. When the cache line A is reserved as a temporary area, the attribute bit 1 is set in the corresponding entry of the attribute memory 5, and the cache line A is not reserved as a temporary area (released state). In, the attribute bit of the corresponding entry in the attribute memory 5 is reset to 0.

Next, the operation of the cache memory 1 thus configured according to the present embodiment will be described.

First, when a temporary area securing instruction (VRSV instruction) for securing the cache line A as a temporary area is executed, an argument (address) and a temporary area securing request are given to the cache memory 1.

Then, in the cache memory 1, the entries of the data memory 2, tag memory 3, valid memory 4 and attribute memory 5 (applicable entries) are indicated by the index part of the address, and the hit determination means 6 Is compared with the tag address of the corresponding entry in the tag memory 3 of each way to determine a cache hit. If there is a cache hit, the data memory 2 of the way that hit the cache (the corresponding way)
The data on the cache line of the corresponding entry is output, and the corresponding way number is notified to the attribute operating means 7 and the replacing means 8.

The attribute operating means 7 sets the attribute bit of the corresponding entry in the attribute memory 5 of the corresponding way to 1, and
The cache line of the corresponding entry in the data memory 2 of the corresponding way is secured as a temporary area.

The cache line A once secured as a temporary area continues to exist in the data memory 2 as a temporary area until a temporary area release instruction (VREL instruction) is executed. When the cache line A is released from the temporary area, the temporary variables existing in the cache line A are not written back from the cache memory 1 to the external memory. That is, data is not transferred from the cache memory 1 to the external memory.

The attribute memory 5 indicates that the corresponding cache line has been secured as a temporary area. If the attribute bit of the attribute memory 5 indicates that it is a temporary area, the data on the cache line is excluded from the replacement target. Note that the attribute bits of the attribute memory 5 are
The value 1 is not changed until the temporary area release instruction (VREL instruction) is executed.

The replacement means 8 replaces the cache line data from the attribute bits of the attribute memory 5 and other information.

If the cache line of the data memory 2 is temporarily secured as a temporary area by the temporary area securing instruction, the cache line is not replaced until the temporary area release instruction is executed. If it is used, data in the external memory space corresponding to the cache line cannot be stored in the cache memory.
It is desirable that it is above.

The provision of a temporary area is performed for a certain external memory space. For example, in a cache memory 1 having a two-way set associative configuration, when two cache lines are reserved as temporary areas, if the tag addresses of the two cache lines match, the same entry in the data memory 2 of a different way is stored. If two cache lines occupy the entry of the data memory 2 as a temporary area, and all the cache lines of the same entry are excluded from replacement, another memory access in the program and the cache line Can not be loaded on the cache memory 1 for the memory address corresponding to.
For this reason, securing a temporary area guarantees a vacancy of a cache line for at least one way. That is, all temporary area reservation instructions that are equal to or larger than the number of ways that request the reservation of a cache line with the same tag address as a temporary area do not always succeed, but at most (in the cache memory 1). Number of ways-
1) Only the number is secured. Note that the failed temporary area reservation instruction is treated as data to be replaced, and the temporary area release instruction for the corresponding memory address is ignored.

When a temporary area release instruction is executed to release the cache line A secured as a temporary area, the temporary area is released in cache line units.

The cache memory 1 according to the present embodiment
Although the extra operation of two clock cycles is required for the temporary area reservation instruction and the temporary area release instruction, the data in the cache memory 1 is not written out to the external memory at the time of replacement. Time is reduced. Generally, if replacement by a write-back policy is performed, writing data on one cache line to an external memory requires several tens of cycles. Therefore, in the cache memory 1 according to the present embodiment, the penalty can be reduced, and
This can contribute to improving the performance of the processor.

[0026]

Next, an example of the cache memory according to the present embodiment will be described in detail with reference to FIGS.

FIG. 3 is a circuit block diagram showing the configuration of the cache memory 1 of the present embodiment. The cache memory 1 of the present embodiment is a secondary cache memory connected to a processor core (not shown) including a processor and a primary cache memory, and has a two-way set associative configuration. The way number is
It is assumed that way 0 and way 1. Hereinafter, in the present embodiment, it is assumed that the entire memory space can be represented by 32 bits.

The data memory 2 is composed of cache lines for storing cached data, and is prepared by the number of ways (2). The size of each cache line is 256 bytes (B) × 256 entries. Data is written to the data memory 2 in cache line units.

The tag memory 3 stores a tag address of data on each cache line of the data memory 2 and has a size of 17 bits × 256 entries and is prepared for the number of ways (2). The tag address is the upper 17 bits of the 32-bit address of the external memory to be accessed.

The valid memory 4 stores valid bits indicating the validity of each cache line of the data memory 2. The valid memory 4 has a size of 1 bit × 256 entries and is prepared for the number of ways (2).

The attribute memory 5 is for writing attribute bits indicating that data on each cache line of the data memory 2 is not to be replaced (the cache line is a temporary area), and has a size of 1 bit × 256.
In the entry, the number of ways (2) is prepared. For example,
The attribute bit of the entry 3F of the attribute memory 5 of the way 0 is 1, the valid bit of the entry 3F of the valid memory 4 of the way 0 is 1, and the tag address of the entry 3F of the tag memory 3 of the way 0 is FF. This means that 256 bytes from address FF3F00 in the external memory space have been reserved for the temporary area.

The hit judging means 6 judges a cache hit for the data stored in the data memory 2 and includes comparators 61 and 62 and an AND gate 63.
And 64, and a selector 65.

The attribute operating means 7 is for operating attribute bits of the attribute memory 5, and is a RAM (Random Access Memory) constituting the attribute memory 5.
ry), which is a control circuit for controlling
, An OR gate 72, and an AND gate 73. The NAND gate 72 and the AND gate 73 are designed to prevent a temporary area reservation request from the processor core from being input to the attribute memory control unit 71 when the attribute bit of the corresponding entry in the attribute memory 5 of both ways becomes 1. It serves to prevent it.

The replacement means 8 is for replacing data on a cache line, and is used for replacing LRU (L
east recently used) information, an LRU memory 81, a data memory 2, and a tag memory 3.
And a memory control unit 82 for controlling the effective memory 4. The LRU memory 81 has a size of 1
A “bit × 256 entry” stores “the most recently accessed way number” as the content of each entry.

Referring to FIG. 4, a temporary area reservation instruction (VRSV instruction) in the cache memory 1 according to the present embodiment.
The processing of the attribute operating means 7 and the replacing means 8 at the time of execution of the process includes an attribute bit readout step S101, a two-way temporary area securing determination step S102, a valid bit readout step S103, an empty way existence determination step S104, Ejection step S105, attribute bit 1 setting step S106, way 0 empty determination step S107, way 0 valid bit 1 setting step S108, and way 0 attribute bit 1 setting step S1
09 and way 1 valid bit 1 setting step S110
And a way 1 attribute bit 1 setting step S111, and a temporary area securing failure step S112.

Referring to FIG. 5, when the temporary area release instruction (VREL instruction) in the cache memory 1 according to the present embodiment is executed, the processing of the attribute operating unit 7 and the replacing unit 8 includes an attribute bit reading step S201, Attribute bit 1 determination step S202, attribute bit 0 restoration step S203, and valid bit 0 restoration step S204
, Data presence / absence determination step S205, and valid bit 0
It comprises a restoration step S206 and a no-processing step S207.

Next, the operation of the thus configured cache memory 1 of this embodiment will be described.

First, when a temporary area securing instruction (VRSV instruction) is executed by the processor core, an argument (address) and a temporary area securing request are given to the cache memory 1 from the processor core.

Then, in the cache memory 1, the data memory 2, the tag memory 3, the valid memory 4, the attribute memory 5, and the LRU
An entry in the memory 81 (hereinafter, this entry is referred to as a corresponding entry) is designated, and the hit determination means 6
Compares the tag portion of the upper 17 bits of the address with the tag address of the corresponding entry in the tag memory 3 of both ways.
Then, the outputs of the comparators 61 and 62 are ANDed with the valid bits of the corresponding entry in the valid memory 4 of both ways by AND gates 63 and 64 to determine a cache hit. If there is a cache hit, the output of the AND gate 63 or 64 becomes 1 (the case where both outputs become 1 is a failure). Is selected by the selector 65 and output to the processor core, and the effective way number is stored in the attribute memory control unit 71 of the attribute operating unit 7.
And the memory control unit 82 of the replacement unit 8 is notified.

On the other hand, the attribute operating means 7 comprises an AND gate 7
When a temporary area reservation request is given via the attribute memory 3, the attribute bit is read from the corresponding entry of the attribute memory 5 of both ways by the attribute memory control unit 71 (step S 10).
1) It is determined whether both cache lines of the corresponding entry in the data memory 2 of both ways have already been secured as temporary areas (step S102). If the cache line of at least one of the ways has already been secured as a temporary area, the attribute memory control unit 71 determines that the securing of the temporary area has failed and ends the process without doing anything (step S112). .

In step S102, if the cache line of the corresponding entry in the data memory 2 of both ways is not secured as a temporary area, the attribute memory control unit 71 determines from the corresponding entry of the valid memory 4 of both ways the valid bit. Is read (step S103), and it is determined whether or not there is an invalid (vacant) way (step S104).

If there is no invalid way, the attribute memory control unit 71 notifies the memory control unit 82 of the replacement unit 8 of the fact.

The memory control unit 82 refers to the LRU memory 81 and drives out the data on the cache line of the corresponding entry in the data memory 2 of the way which is not used most recently (old) to the external memory (step S105). .
It should be noted that a path for flushing data to the external memory is not shown.

After the data has been flushed to the external memory, the attribute memory control unit 71 of the attribute operating means 7 sets the attribute bit of the entry in the attribute memory 5 of the way to 1 (step S106). As a result, the cache line of the corresponding entry in the data memory 2 of the corresponding way is secured as a temporary area.

On the other hand, if there is an invalid way in step S104, the attribute operating means 7
It is determined whether way 0 is free (step S107).

If way 0 is free, replacement means 8
Is the effective memory 4 of the way 0 by the memory control unit 82.
Is set to 1 (step S1).
08).

Next, the attribute memory control unit 71
The attribute bit of the corresponding entry in the attribute memory 5 is set to 1 (step S109). As a result, the cache line of the corresponding entry in the data memory 2 of way 0 is secured as a temporary area.

If the way 0 is not empty at the step S107, the memory control unit 82 sets the valid bit of the corresponding entry of the valid memory 4 of the way 1 to 1 (step S110).

Next, the attribute memory control unit 71
The attribute bit of the corresponding entry in the attribute memory 5 is set to 1 (step S111). As a result, the cache line of the corresponding entry in the data memory 2 of the way 1 is secured as a temporary area.

At the time of fetching, the same operation as that of the conventional cache memory is performed, and the detailed description of the operation is omitted.

When a temporary area release instruction is executed by the processor core after the temporary area is secured, an argument (address) is stored in the cache memory 1 from the processor core.
And a temporary area release request.

Then, in the cache memory 1, the data memory 2, the tag memory 3, the valid memory 4, the attribute memory 5, and the LRU
The entry of the memory 81 (corresponding entry) is specified, and the hit determination means 6 compares the tag portion of the upper 17 bits of the address with the tag address of the corresponding entry in the tag memory 3 of both ways by the comparators 61 and 62. , AND gates 63 and 64 AND the outputs of comparators 61 and 62 and the valid bits of the corresponding entry in valid memory 4 of both ways to determine a cache hit. If there is a cache hit, AND gate 63 or 6
4 becomes 1 (the case where both outputs become 1 is a failure), the data on the cache line of the corresponding entry of the data memory 2 of the way (the corresponding way) which hit the cache is selected by the selector 65 and the processor core Is output to the attribute operation means 7
To the attribute memory control unit 71 and the memory control unit 82 of the replacement unit 8.

Attribute memory control unit 71 of attribute operation means 7
When the temporary area release request is given, the attribute bit is read from the corresponding entry in the attribute memory 5 of the corresponding way (step S201), and it is determined whether the attribute bit is 1 (step S202).

If the attribute bit is 1, the attribute memory control unit 71 returns the attribute bit of the entry in the attribute memory 5 of the way to 0 (step S203). As a result, the cache line of the corresponding entry in the data memory 2 of the corresponding way is released from the temporary area.

Next, the memory controller 82 of the replacing means 8
Returns the valid bit of the corresponding entry of the valid memory 4 of the corresponding way to 0 (step S204).

If the attribute bit is not 1 in step S202, the replacing means 8 determines whether the corresponding temporary variable is on the cache line by the memory control unit 82 (step S205). The valid bit of the corresponding entry in the attribute memory 5 is reset to 0 (step S206). In step 205, if the corresponding temporary variable is not on the cache line, the replacing means 8
Does nothing (step S207) and ends the process.

[0057]

An advantage of the present invention is that the communication between the cache memory and the external memory can be reduced and the performance of the processor can be improved. The reason is that an area (temporary area) for a temporary variable generated during the execution of the program can be prepared in the cache memory, and the update performed on the data in the temporary area is not reflected in the external memory. Because it was.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of a cache memory according to an embodiment of the present invention.

FIG. 2 is a diagram showing a data memory and an attribute memory in FIG. 1 and a program example for explanation.

FIG. 3 is a circuit block diagram showing a configuration of an example of a cache memory according to the present embodiment.

FIG. 4 is a flowchart illustrating processing of an attribute operation unit and a replacement unit when a temporary area securing instruction (VRSV instruction) in a cache memory according to the present embodiment is executed.

FIG. 5 is a flowchart illustrating processing of an attribute operation unit and a replacement unit when a temporary area release instruction (VREL instruction) is executed in the cache memory according to the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Cache memory 2 Data memory 3 Tag memory 4 Valid memory 5 Attribute memory 6 Hit determination means 7 Attribute operation means 8 Replacement means 61, 62 Comparator 63, 64 AND gate 65 Selector 71 Attribute memory control unit 72 NAND gate 73 AND gate 81 LRU Memory 82 Memory control unit

Claims (9)

[Claims] 1. A cache memory having a two-way or more set associative configuration, wherein a temporary area in which data update is not reflected in an external memory can be selectively designated for each cache line of the data memory. . 2. An attribute memory for storing an attribute bit indicating a temporary area in which data update is not reflected in an external memory for each cache line of the data memory, and means for referring to the attribute bit of the attribute memory. 2. The cache memory according to claim 1, comprising: 3. The cache memory according to claim 2, further comprising replacement means for selecting whether or not data can be replaced for each cache line by referring to attribute bits of said attribute memory. 4. A temporary area securing request and a temporary area releasing request are received from the processor when the processor executes a program or a dedicated instruction for securing and releasing the temporary area, and securing the temporary area. 4. The cache memory according to claim 3, further comprising attribute operation means for operating attribute bits of said attribute memory to perform release. 5. A cache memory having a two-way or more set associative configuration, a plurality of ways of data memory comprising a plurality of cache lines for storing cached data, and a plurality of way data memories corresponding to each of the cache lines. A multi-way tag memory for registering the tag address of the data of the cache line, and a multi-way effective memory for storing a valid bit indicating the validity of the data of the cache line corresponding to each cache line of the data memory; A multi-way attribute memory for storing an attribute bit indicating whether or not the cache line is reserved as a temporary area that does not reflect data update to an external memory, corresponding to each cache line of the data memory; Address index part of the data Hit determining means for comparing a tag address of the tag memory with a tag address to determine a cache hit; and attribute operation for operating attribute bits of the attribute memory when a temporary area securing instruction and a temporary area releasing instruction are executed. Means for determining whether data in the cache line of the data memory is replaceable based on attribute bits of the attribute memory and performing replacement processing of the data if replacement is possible. Characteristic cache memory. 6. In a cache memory having a two-way set associative configuration, a pair of data memories including a plurality of cache lines for storing cached data, and a cache corresponding to each cache line of the data memories A pair of tag memories for registering tag addresses of line data, a pair of valid memories for storing valid bits indicating validity of data of the cache line corresponding to each cache line of the data memory, and the data memory A pair of attribute memories for storing attribute bits indicating whether or not the cache line is secured as a temporary area that does not reflect the update of data in the external memory, corresponding to each of the cache lines; Index part and tag address of the tag memory Hit determining means for determining a cache hit by comparing the attribute memory with an attribute memory for operating an attribute bit of the attribute memory when a temporary area securing instruction and a temporary area releasing instruction are executed; A cache memory comprising: a replacement unit that determines whether data in a cache line of the data memory is replaceable based on an attribute bit of the memory and performs a data replacement process if the replacement is possible. . 7. A pair of comparators for comparing an index part of an address of data to be accessed with a tag address of the tag memory, and an output of the comparator and a valid bit of the valid memory. 7. The cache memory according to claim 6, further comprising: a pair of AND gates for performing an AND operation, and a selector for selecting data from one of the cache lines of the pair of data memories in accordance with an output of the AND gate. 8. A NAND gate for inverting a logical product of attribute bits of the pair of attribute memories;
An AND gate for ANDing the output of the NAND gate and the temporary area reservation request; and an attribute memory control unit for operating the attribute bits of the pair of attribute memories in response to the output of the AND gate and the temporary area release request. Claim 6 including
The cache memory as described. 9. An LRU memory for storing a way number most recently accessed corresponding to each cache line of said pair of data memories, and said pair of data memories in response to an output of said hit judging means. 7. The cache memory according to claim 6, further comprising: a memory control unit that controls the pair of data memories, the pair of tag memories, and the pair of valid memories by referring to attribute bits of the attribute memory.