JPH11330487A - Thin film transistor, solid state device, display and fabrication of thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor in which electric characteristics, e.g. off current characteristics, can be enhanced and a fabrication method thereof. SOLUTION: The thin film transistor 110 has an n<-> source region 112 of about 400 Å n<-> silicon film (lightly doped region) a source region 112 and an n<-> drain region 113 wherein the lightly doped region and a gate electrode are overlapped. The gate electrode 116 is a metal electrode being formed after formation of the n<-> source region 112 and the n<-> drain region 113 wherein the gate electrode 116, the n<-> source region 112 and the n<-> drain region 113 are self-aligned.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a thin film transistor,
Regarding solid-state devices such as semiconductor devices, display devices such as liquid crystal display panels and methods of manufacturing thin film transistors,
The present invention relates to a technique for improving electric characteristics of a thin film transistor.

[0002]

2. Description of the Related Art In an active matrix substrate of a liquid crystal display panel or the like, a thin film transistor mounted as a switching element is, for example, a gate oxide film on a surface of a silicon layer 2202 on a surface of a substrate 2201 as shown in FIG. 2203 is formed, ion implantation is performed using the gate electrode 2204 on the surface thereof as a mask, and a part of the silicon layer is made conductive so that the source region 2205 and the drain region 2206 are formed to be self-aligned. I have. However, FIG.
In the thin film transistor of the structure shown in 0, as indicated by a solid line L ₃ in FIG. 21, when applying a negative gate voltage to the gate electrode 2204 even (OFF state), there is a question deer that a large drain current flows . The reason is,
It is understood as a phenomenon that the pn junction is broken and holes are injected at the end of the drain region 2206 which is reverse biased, and the magnitude is applied between the gate electrode 2204 and the drain region 2206. There is a tendency defined by the voltage and the trap level in the silicon film corresponding to the drain region 2206 and the end of the gate electrode 2204 near the drain region 2206. Therefore, a low-concentration region is provided at the end of the drain region corresponding to the end of the gate electrode, and a drain structure (LDD structure) in which the electric field strength is reduced is adopted, and a structure in which the on / off current ratio is increased is adopted. May be. This LDD
In order to manufacture a thin film transistor having a structure, the following manufacturing method has conventionally been adopted. That is, as shown in FIG. 22A, after a pattern 2402 made of a silicon film is formed on the surface side of a substrate 2401, the surface side is covered with a gate insulating film 2403, and a gate electrode should be formed on the surface side. A conductive film 2404 is formed.

Next, as shown in FIG. 22B, a resist pattern 2405 is formed on the surface side of the conductive film 2404 by using a light exposure technique, and the resist pattern 2405 is selectively etched using the resist pattern as a mask. A gate electrode 2406 smaller than the pattern is formed.

Next, an impurity to be a donor or an acceptor is ion-implanted, for example, into 1 × 10 ¹⁵
cm ⁻² , and as shown in FIG.
The source region 2407 and the drain region 2 are self-aligned.
408 are formed. Here, a region which is blocked by the gate electrode 2406 and the resist pattern 2405 and in which ions are not implanted becomes a channel formation region 2409.

Next, the resist pattern 2405 is removed. Here, in order to configure the LDD structure, FIG.
As shown in FIG. 3D, low concentration regions 2410 and 2411 are formed in regions corresponding to ends of the gate electrode 2406 by ion-implanting impurities of about 1 × 10 ¹⁴ cm ⁻² using the gate electrode 2406 as a mask.

[0006]

However, in a conventional method of manufacturing a thin film transistor having an LDD structure,
After forming the gate electrode 2406, the source region 240
7, drain region 2408 and low concentration region 2410,
Since the gate electrode 2406 is heated when the impurity is activated by performing a heat treatment at about 1000 ° C. on the silicon film into which the impurity is introduced to form 2411, a material that can be used for the gate electrode 2406 Is
It is limited to those having high heat resistance such as silicon compounds, and there is a problem that the electric resistance or the like must be sacrificed. Here, when a signal is transmitted using a wiring formed at the same time as the gate electrode 2406 as in an active matrix substrate of a liquid crystal display panel, signal delay is caused due to high electric resistance. Becomes large. Therefore, there is a method of activating the impurity without partially applying a laser beam to the gate electrode 2406 without applying thermal stress. In this method, the crystal state disturbed by the introduction of the impurity is sufficiently reduced. However, since the trap level increases, the off-state current increases, and the significance of adopting the LDD structure is lost.

[0007] In view of the above problems, an object of the present invention is to provide:
A thin film transistor, a solid state device such as a semiconductor device, a display device such as a liquid crystal display panel, and a method for manufacturing the thin film transistor, which can improve electrical characteristics such as off-current characteristics by improving a configuration of a source / drain region and a gate electrode. Is to do.

[0008]

In order to solve the above-mentioned problems, means taken in a thin film transistor according to the present invention is to form a channel on a front surface side of a substrate so that a channel can be formed between a source region and a drain region. A region and a gate electrode facing the surface of the channel formation region with a gate insulating film interposed therebetween. In the source region and the drain region, the end of the gate electrode is interposed between the gate electrode and the gate electrode. The overlapping region is a low-concentration region formed in a step before the gate electrode, for example, a low-concentration region having an impurity concentration of 1 × 10 ²⁰ cm ⁻³ or less. That is, a structure in which the source region and the drain region are formed in a step before the gate electrode and have a low concentration region overlapping with the gate electrode, or the entire source region and the drain region are formed in a step before the gate electrode. A low-concentration region having a structure in which the end overlaps the gate electrode.

In the thin film transistor according to the present invention, the source region and the drain region are not formed by introducing impurities using the gate electrode as a mask, but are formed before forming the gate electrode and activate the introduced impurities. When the gate electrode is formed, the gate electrode is not yet formed. Therefore, the impurity can be activated without being restricted by the heat resistance of the constituent material of the gate electrode. In particular, when a thin film transistor is formed by a low-temperature process, crystallization of a channel portion can be performed after introduction of an impurity, so that a trap level in a drain region corresponding to an end portion of a gate electrode and its vicinity can be reduced. . Further, since the low concentration regions of the source region and the drain region face the gate electrode, the electric field intensity at the end of the gate electrode is low. Therefore, the off-current characteristics of the thin film transistor can be improved.

Here, when the thin film transistor according to the present invention is formed by a low temperature process in which the maximum process temperature is suppressed to about 600 ° C. or less, an activation process for forming a low concentration region is performed by crystallization of a channel portion. It is preferable to also serve as processing.

That is, a silicon film for forming a low-concentration region and a channel formation region is formed, and after selectively introducing impurities, a crystallization process which also activates the impurities is performed. Here, as the crystallization treatment, a laser annealing method of irradiating a silicon film with a laser beam to crystallize the silicon film and deactivate impurities,
Alternatively, a silicon film is annealed for a long time at a low temperature to crystallize it and activate impurities, or a solid phase growth method (SPC method), or a lamp annealing is performed on the silicon film, Rapid thermal annealing face (RTA method) that crystallizes and activates impurities
Can be adopted.

In the present invention, the source region and the drain region are provided with a low resistance region connected to a low concentration region with a high impurity concentration or a low resistance region connected with a thick film, respectively. Is preferably reduced. In some cases, the channel formation region and the whole or part of the source region and the drain region are formed in different steps.

In the present invention, it is preferable that the thickness of the low concentration region is equal to the thickness of the channel formation region. Alternatively, the thickness of the low-concentration region is set to be smaller than the thickness of a depletion layer formed in a state where the thickness is defined by the impurity concentration of the low-concentration region when a potential is applied to the gate electrode. Is preferred. For example, the thickness of the low concentration region is set to about 500 Å or less.

Such a thin film transistor can be used for various solid-state devices such as a three-dimensional integrated circuit (semiconductor device) and an image sensor. In addition, a display device such as a liquid crystal display panel can be formed by using the thin film transistor according to the present invention as a pixel transistor (component) in a pixel region of an active matrix array. In this case, for example, while the thin film transistor according to the present invention is formed of an n-channel type thin film transistor, the C of the driving circuit unit formed on the same substrate together with the active matrix array is formed.
As the MOS circuit, a structure using an n-channel thin film transistor having the same structure as the thin film transistor and a p-channel thin film transistor formed in a self-alignment manner with the gate electrode can be considered. As another combination, the structures of the n-channel thin film transistor and the p-channel thin film transistor may be reversed, the p-channel thin film transistor may have the structure of the present invention, and the n-channel thin film transistor may be a self-aligned type. In this case, the pixel portion is formed of a p-channel thin film transistor.

In the pixel portion, the thin film transistor of the present invention is used, and in a driving circuit formed on the same substrate together with the active matrix array, a CMOS circuit is used.
As each of the thin film transistors included in the circuit, an n-channel thin film transistor and a p-channel thin film transistor formed in self-alignment with the gate electrode can be used.

In any case where the thin film transistor of the pixel portion and the driving circuit is formed by any combination, the impurity concentration of each region may be, for example, approximately 1 × the impurity concentration of the source region and the drain region of the self-aligned thin film transistor. A region of 10 ²⁰ cm ⁻³ or more, and a low concentration region of a non-self-aligned thin film transistor has an impurity concentration of about 1
× 10 ²⁰ cm ⁻³ or less. Further, among the thin film transistors formed over the substrate, the thickness of the source region and the drain region of the self-aligned thin film transistor may be equal to the thickness of the low concentration region of the non-self aligned thin film transistor.

Here, in the active matrix array, it is common that a storage capacitor is connected in series to a drain portion of a thin film transistor constituting a pixel region. For example, the storage capacitor can be configured such that the preceding scanning line is used as the upper electrode, the gate insulating film of the thin film transistor is used as the capacitor insulating film, and the extended region extending from the drain region of the thin film transistor is used as the lower electrode.

However, when a thin film transistor is formed by a conventional technique, that is, when a source / drain region is formed after a gate electrode is formed, ion implantation is performed below the gate electrode after formation of the gate electrode. Therefore, it is necessary to add a step of forming a lower electrode in advance below the gate line. However, in the thin film transistor of the present invention, at least the low concentration region is formed before the formation of the gate electrode. With this step, an extended region is provided in the drain region and can be used as a lower electrode.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a thin film transistor according to the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view showing the structure of a thin film transistor according to this embodiment.

In this figure, the thin film transistor 110 of this embodiment is formed on an insulating substrate 111 such as glass, quartz or sapphire. On the surface side of the insulating substrate 111, about 1 × 10 ¹⁹ cm ^{−3 of} phosphorus is added. Thickness less than about 500 angstroms, for example, about 40
0 angstrom n ^- type silicon film (low concentration region)
A drain region 113, these n ^{- -} source region 112 and the n ^- n consisting of the source region 112 and the n ^- be between the drain region 113, and a channel forming region 114 connecting these regions. Here, n ^- source region 112, n ^- drain region 113 Oyopi channel forming region 114 is a silicon film crystallization process is performed to the amorphous silicon, the presence or absence of impurities, n ^- source region 112 , N ^- drain region 11
3 and the channel formation region 114 are defined, so that the thicknesses of the n ⁻ source region 112, the n ⁻ drain region 113, and the channel formation region 114 are all equal to about 400 Å. On the surface side of the n ⁻ source region 112, the n ⁻ drain region 113 and the channel forming region 114, a gate insulating film 115 made of an insulating film such as a silicon oxide film covering the whole thereof, And a gate electrode 116 formed on the front surface side. The gate electrode 116 is made of a material such as a metal or a transparent conductive film according to the function of the device on which the thin film transistor 110 is to be mounted. Here, gate electrode 116 and n ⁻ source region 112 and n ⁻ drain region 113 are not configured in a self-aligning manner, and one rigid end 117 of gate electrode 116 and n ⁻
The overlapping area of the source region 112 with the end 118 and the other end 119 of the gate electrode 116 and the n ⁻ drain region 1
The superimposed area of the thirteenth and the 120 is relatively large.

Reference numeral 121 denotes an insulating film between layers, and a source electrode 124 and a drain electrode 125 through contact holes 122 and 123 of the insulating film 121.
Are the n ⁻ source region 112 and the n ⁻ drain region 11
3 is conductively connected.

The thin film transistor 110 having such a configuration
In this case, since the n ⁻ source region 112 and the n ⁻ drain region 113 are formed before the gate electrode 116 is formed, the impurities introduced in forming the n ⁻ source region 112 and the n ⁻ drain region 113 are formed. Is activated, the gate electrode 116 has not been formed yet. Therefore, a large-area LCD is used for the gate electrode 116 by using, for example, a metal electrode having a small sheet resistance.
Even if a high-definition LCD is formed, its heat resistance does not limit the activation condition of the impurities introduced into n ⁻ source region 112 and n ⁻ drain region 113. That is, the impurities introduced to form n ⁻ source region 112 and n ⁻ drain region 113 can be sufficiently activated, and the crystal state collapsed by the introduction of the impurities can be sufficiently repaired. The other end of the county 119
, The trap level at the end portion 120 of the n ⁻ drain region 113 or in the vicinity thereof can be reduced. Further, since the n ^- drain region 113 is a low concentration region,
The electric field intensity near the gate electrode 116 is small.

Therefore, the off-current characteristics of the thin film transistor 110 can be improved.

[0025] Moreover, n ^- thickness and n drain region 113 ^- the thickness of the vicinity of the drain region 113 are both about 400 angstroms and thin. Here, the number of trap levels that cause off-current tends to increase as the film thickness increases. Thus, n ^- thickness and n drain regions 113 ^- by the thickness of the vicinity of the drain region 113 is thin, so that the number of trap levels in that region is reduced, the off current can be further reduced . For example, n ^- thickness and n drain region 113 ^- the drain region 113 near the thickness of the various gate voltage of the thin film transistor which was 400 Å -
The drain current characteristic shown by the solid line L ₁ in FIG. 2 (a), as a comparative example, the thickness of the drain region and the drain region near the thickness was 2000 angstroms various gate voltage of the thin film transistor - drain current characteristics, FIG.
(B) a as indicated by the solid line L _2, towards the thickness and the drain region thickness in the vicinity of the drain region is as thin as 400 angstroms, small off current, off-current characteristics of the thin film transistor 110 of this embodiment is better That has been confirmed.

Further, in the thin film transistor 110 of the present embodiment, the n ^- drain region 113 near the end of the gate electrode 116 is flat, and the n ^- drain region 113 between the other end 119 of the gate electrode 116 and the end 120 of the drain electrode 113 is formed. Electric field concentration is unlikely to occur between them.

Further, in the thin film transistor 110 of this embodiment, n ^- source region 112 and the n ^- despite overlapping area between the drain region 113 and the gate electrode 116 is wide, n ^- source region 112 and the n ^- drain region 113 Is about 1 × 10 ¹⁹ cm ⁻³ while the thickness is about 400 Å, so that the gate electrode 116 and the n ⁻ source region 1
12 is the smallest. That is, in this example, the gate electrode 116 and the n ⁻ source region 11
The thickness of the depletion layer caused by questions of the potential of the 2, if its potential is constant, n ^- Observe that defined in the impurity concentration of the source region 112, a depletion layer the n ^- source region 112 The n ⁻ source region 11 is extended to reach the lower surface.
2 is set. Specifically, the gate electrode 11
6 and the n ^- when a potential is applied between the source region 112, as shown in FIG. 3 (a), the first capacitor C ₁ corresponding to the gate Bok insulating film 115, corresponding to the depletion layer 126 Second
And the capacitance C _2, the third capacitor C ₂ corresponding to the side of the substrate 111
Are connected in series, and the combined capacitance is small. On the other hand, when the n ⁻ source region 112 is thick, the lower surface of the depletion layer 126 is, as shown in FIG.
a first capacitor C corresponding to the gate insulating film 115 at an intermediate position in the thickness direction of the n ^- source region 112;
_1, only the second capacitor C ₂ corresponding to the depletion layer 126 is in a series connection state, the combined capacitance is large. Here, the reason why the thickness of n ⁻ source region 112 is set to about 400 Å is that its impurity concentration, that is, 1
A counterpart to × ¹⁰ 19 ^{cm -3,} is not limited thereto, in response to the impurity concentration, a depletion layer 126 the n ^-
The thickness of the n ⁻ source region 112 may be set so as to reach the lower surface of the source region 112 (the side of the substrate 111).

More specifically, the thickness of the n ^- source region 112 may be reduced to about 100 angstroms in view of the limitation on the process for controlling the impurity concentration.

Next, a method of manufacturing the thin film transistor of this embodiment will be described with reference to FIGS.

4 (a) to 4 (d) are process sectional views showing a part of the method of manufacturing the thin film transistor of this embodiment.

First, as shown in FIG. 4A, a low-temperature process, for example, when the temperature is 5
After depositing the amorphous silicon film by the Spack method or the LpCVD method in the atmosphere of 50 ° C. to 600 ° C.,
Forming a resist pattern 203 using a light exposure technique,
Pattern 2 by patterning amorphous silicon film
02 (amorphous silicon film) is formed. here,
After the amorphous silicon film is crystallized by irradiating a laser beam, impurities may be introduced. However, the introduction of the impurities causes a disorder in the crystal state, and thus requires a repairing process again. Therefore, in this example, after introducing the impurity, crystallization is performed, and the activation of the impurity is performed at the same time by this crystallization.

That is, after patterning the amorphous silicon film, the resist pattern 203 is removed, and FIG.
As shown in (b), another resist pattern 20
In the state where the silicon nitride layer 4 is formed, phosphorus is ion-implanted using this as a mask to form an n ₁ source region 212 (low-concentration region) and an n ⁻ drain region 2 with impurity impurity of about 5 × 10 ¹⁸ cm ^−3.
13 (low concentration region) is formed. Here, in the pattern 202 of the amorphous silicon film, a region where phosphorus is not introduced becomes a channel formation region 214.

Next, after the resist pattern 204 was stripped, the amorphous silicon film (pattern 202) was irradiated with a laser beam to anneal it, thereby polycrystallizing the amorphous silicon film and introducing it into the amorphous silicon film. Activate impurities. Alternatively, the amorphous silicon film is annealed in a nitrogen atmosphere at a temperature of about 600 ° C. for about 4 hours (solid phase growth method: SPC
Method), crystallizing the amorphous silicon film,
Activate the impurities introduced into it. In this case, if necessary, plasma hydrogen treatment is performed in an atmosphere at a temperature of 350 ° C., or rapid thermal annealing is performed on the amorphous silicon film to crystallize the amorphous silicon film. Activate the introduced impurities.

Next, as shown in FIG. 4C, after a gate insulating film 215 is formed on the surface side of the amorphous silicon film (n ^- source region 212, n ^- drain region 213 and channel formation region 214). On the surface side of the gate insulating film 215, a gate electrode 216 of metal or the like is formed. Here, the one end 217 and the other end 218 of the gate electrode 216 are connected to the n ⁻ source region 212 and the n ⁻ source region 212.
^- it has a structure that faces the end portion 219, 220 of the drain region 213.

Thereafter, as shown in FIG. 4D, after forming an interlayer insulating film 221 on the surface side of the gate electrode 216, contact holes 222 and 223 are formed therein, and the contact holes 222 and 223 are used. do it,
As shown in FIG. 1, the source electrode 124 and the drain electrode 125 are connected to the n ⁻ source region 212 and the drain electrode 213 to form the thin film transistor 110.

As described above, the thin film transistor 1 of the present embodiment
According to the manufacturing method of Example 10, after introducing an impurity into a silicon film such as an amorphous silicon film, a crystallization process is performed on the amorphous silicon film, and the crystallization process itself also serves as an impurity activation process. . In addition, in the subsequent steps, no impurity is introduced, which simplifies the process, and the crystal state of the silicon film after the crystallization treatment is not destroyed by the introduction of the impurity, so that the trap level increases. Without this, the thin film transistor 110 having good off-current characteristics can be efficiently manufactured.

Although an amorphous silicon film is used as the silicon film in this embodiment, this film may be a polycrystalline silicon film.

(Second Embodiment) Next, FIGS. 5 (a) to 5 (c)
A thin film transistor according to a second embodiment of the present invention and a method for manufacturing the same will be described with reference to FIG.・ Fig. 5 (a) ~
(C) is a process sectional view showing a part of a manufacturing process of the thin film transistor of the present example.

The thin film transistor of this embodiment has the structure shown in FIG. 5C in order to improve the on / off characteristics, similarly to the thin film transistor of the first embodiment.

[0040] That is, the thin film transistor evening 300, glass, quartz, by a surface of the insulating substrate 301 such as sapphire, phosphorus was added in an amount of about 1 × ¹⁰ 20 ^{cm -3} n ^- source region 302 (low concentration region) and the n ^- Drain region 3
03 (low-concentration region), on the surface side of which is formed a silicon thin film such as polycrystalline silicon having a thickness of about 1000 Å so as to connect the n ⁻ source region 302 and the n ⁻ drain region 303. It has a channel formation region 304. In addition, a gate insulating film 305 such as a silicon oxide film is provided on the surface side of the n ⁻ source region 302, the channel formation region 304, and the n ⁻ drain region 303. ^- overlap through the gate insulating film 305 with respect to the drain region 303 ^- the source region 302 and n.

The thin film transistor 300 having such a configuration
5A, first, as shown in FIG. 5A, for example, 1 × phosphorus is applied to the surface side of the insulating substrate 301.
N of polycrystalline silicon or the like added to about 10 ²⁰ cm ^−3
- a silicon thin film after depositing about 1500 angstroms, the n ^- selectively etching the silicon thin film, n ^- drain regions 303 (low Hama level area) ^- a source region 302 (low concentration region) and n. Thereafter, the n ⁻ source region 302 and the n ⁻ drain region 30
A channel forming region 304 made of a silicon thin film such as polycrystalline silicon having a thickness of about 1000 Å connecting them is formed on the surface side of the substrate 3. Thereafter, the whole is thermally oxidized to form a gate insulating film 305 made of a silicon oxide film, and a gate electrode material 306 made of a metal, a transparent conductive film, a polycrystalline silicon film doped with impurities, or the like is formed on the surface thereof. Form.

Next, as shown in FIG. 5B, a resist pattern 307 is formed on the surface of the gate electrode material 306 in a region where the gate electrode is to be left, using a light exposure technique or the like, and this is used as a mask. The gate electrode material 306 is selectively etched to form a gate electrode 308. Here, the end portion of the gate electrode 308, n ^- source region 302
And the end of the n ⁻ drain region 303 via the gate insulating film 305.

Next, the resist pattern 307 is removed,
Thereafter, as shown in FIG. 5C, a layer insulating film 309 made of a silicon oxide film is formed as in a normal process. Next, the contact hole 310 is formed in the interlayer insulating film 309.
Is formed, and then a source electrode 311 and a drain electrode 312 made of a metal, a transparent conductive film, or the like are respectively formed with n.
^- connected to the drain region 303 ^- the source region 302 and n.

Accordingly, the thin film transistor 300 of the present embodiment
Also, similarly to the thin film transistor according to the first embodiment, before forming the gate electrode 308, the n ⁻ source region 302 is formed.
And the n ^- to form a drain region 303, without being restricted by the heat resistance of the material constituting the gate electrode 308, n ^- source region 302 and the n- drain region 30
3 can be formed in an ideal state. Therefore, the off-state current can be improved.

(Third Embodiment) Next, FIGS. 6 (a) to 6 (d)
A thin film transistor according to a third embodiment of the present invention and a method for manufacturing the same will be described with reference to FIG.

FIGS. 6A to 6D are process sectional views showing a part of the manufacturing process of the thin film transistor of this example.

The thin film transistor of this embodiment is different from the thin film transistor of the first embodiment in that regions having different concentrations are formed in the source region and the drain region.
In order to improve the on-current characteristics in addition to the improvement of the off-characteristics, as shown in FIG. 6D, of the front side of the insulating substrate 401 made of glass or the like, n ⁺
It has a source region 412 (high-concentration low-resistance region) and an n ⁻ source region 405 (low-concentration region), and has an n ⁺ drain region 413 (high-concentration low-resistance region) on the drain region side.
And an n ^- drain region 406 (low-concentration region). Here, the end of the gate electrode 409 overlaps with the end of the low-concentration n ⁻ source region 405 and the end of the n ⁻ drain region 406 via the gate insulating film 408. On the other hand, the source electrode 420 and the drain electrode 421 are formed of the n ⁺ source region 412 and the n ⁺ drain region 41 of Takahama degree.
3 is connected.

The thin film transistor 400 having such a configuration
First, as shown in FIG. 6A, a silicon thin film such as polycrystalline silicon is deposited on an insulating substrate 401 such as glass as shown in FIG. Thereafter, a resist pattern 403 is formed by using a light exposure technique or the like, and the silicon thin film is selectively etched using the resist pattern 403 as a mask to form a silicon pattern 402.

Next, after removing the resist pattern 403, as shown in FIG. 6B, a new resist pattern 404 is formed by using a light exposure technique or the like, and phosphorus is ion-implanted using this as a mask. 1 × 10 ¹⁸ cm
^{Approximately -3} n ^- source regions 405 and n ^- drain regions 406 are formed. Here, the region not ion-implanted becomes the channel formation region 407.

Next, after removing the resist pattern 404, the whole is thermally oxidized to form a gate insulating film 408 made of a silicon oxide film as shown in FIG. 6C.
This heat treatment also has the effect of activating the implanted ions. Thereafter, a gate electrode 409 made of a metal, a transparent conductive film, a polycrystalline silicon film to which impurities are added, or the like is formed. Here, the gate electrode 409 overlaps with part of the n ⁻ source region 405 and the n ⁻ drain region 406 via the gate insulating film 408.

Next, as shown in FIG. 6D, after forming an interlayer insulating film 410 made of a silicon oxide film, a contact hole 411 is formed therein. Thereafter, phosphorus is ion-implanted using the interlayer insulating film 410 as a mask,
By irradiating a laser beam to activate the implanted ions, an n ⁺ source region 412 of about 5 × 10 ²¹ cm ^{−3 is formed.}
And an n ⁺ drain region 413 is formed.

Thereafter, the source electrode 420 and the drain electrode 421 made of a metal, a transparent conductive film or the like are connected to the n ⁺ source region 412 and the n ⁺ drain region 413, respectively, as in the normal manufacturing method.

The thin film transistor 401 having such a configuration
Also, n ⁻ overlaps with the end of the gate electrode 409.
The source region 405 and the n ⁻ drain region 406 are formed before forming the gate electrode 409.
Therefore, even if a metal or the like is used for the gate electrode 409, the n ⁻ source region 405 is not restricted by its heat resistance.
And the n ^- with sufficiently perform the activation of the introduced impurities into the drain regions 406, since the crystalline state disturbed by the introduction of impurities can be sufficiently repaired, n ^- the ends of the drain region 406 and the trap level in the vicinity Position can be reduced. Further, since the n ^- drain region 406 is a low-concentration region, the electric field intensity near the gate electrode 409 is small. Therefore, the off-current characteristics of the thin film transistor 401 can be improved.

Further, of the source region and the drain region, the region that affects the on / off characteristics and the like is made a low concentration region, while the source electrode 420 and the drain electrode 4
Since the region to which 21 is connected is a high-concentration region, the parasitic resistance is small and a large on-current can be obtained.

(Embodiment 4) On the other hand, the thin-film transistor shown in FIG. 7 instead of the thin-film transistor according to the third embodiment can improve the on-off characteristics and the on-current.

FIG. 7 is a cross-sectional view of the thin film transistor of this example in the channel direction.
On the surface side of an insulating substrate 431 made of glass, quartz, sapphire, or the like, a pattern made of a silicon thin film such as polycrystalline silicon is provided. This pattern contains phosphorus at 5 × 10 ²⁰ cm.
And ^{n +} source region 432 and ^{n +} drain region 433 including about ^-3, n comprises about 5 × ¹⁰ 18 ^{cm -3} boron ^- source region 434 and the n ^- drain region 435
And a channel formation region 436 containing boron at about 1 × 10 ¹⁷ cm ⁻³ . A gate insulating film 437 made of an insulating film such as a silicon insulating film is provided on the surface side thereof, and a gate electrode 438 made of a metal or a transparent conductive film is provided thereon. Here, the end of the gate electrode 438 is
The gate insulating film 437 overlaps the ends of the n ⁻ source region 434 and the n ⁻ drain region 435 via the gate insulating film 437. On their surface side, an interlayer insulating film 439 made of an insulating film such as a silicon oxide film is provided, and a source electrode 441 and a drain electrode 442 made of a metal or a transparent conductive film are formed through a contact hole 440 formed therein. Are connected to the n ⁺ source region 432 and the n ⁺ drain region 433.

The thin film transistor 430 having such a configuration
Although the description of the manufacturing method is omitted, the n ⁻ source region 434 and the n ⁻ drain region 435 overlapping the end of the gate electrode 438 are formed before the gate electrode 438 is formed. Gate electrode 43
Even if a metal or the like is used for 8, n ^- source region 434 and n ^- drain region 4 are not restricted by their heat resistance.
Activation of the impurities introduced into 35 can be sufficiently performed. Further, there is an effect that the crystal state broken by the introduction of the impurity can be sufficiently repaired.

Also, of the source region and the drain region, the region which affects the on / off characteristics and the like is set as a low concentration region, while the high concentration regions (n ⁺ source region 432 and n ⁺ drain region 433) are provided. , A small parasitic resistance and a large on-current can be obtained.

(Fifth Embodiment) Next, FIGS.
A thin film transistor according to a fifth embodiment of the present invention and a method for manufacturing the same will be described with reference to FIG.

FIGS. 8A to 8C are process cross-sectional views showing a part of the manufacturing process of the thin film transistor of this example.

The thin film transistor of this embodiment is different from the thin film transistor of the second embodiment in that regions having different concentrations are formed in the source region and the drain region.
In order to improve the on-current characteristics in addition to the improvement of the off characteristics, as shown in FIG. 8C, the thin film transistor 450 is formed on the source region side of the surface of the insulating substrate 453 made of glass or the like. Means that boron is 1 × 10 ²¹ cm ⁻³
N ⁺ source region 458 (high-concentration region) and n ⁻ source region 452 with boron of about 1 × 10 ¹⁹ cm ^−3.
(Low-concentration region), and n ⁺ drain region 459 of about 1 × 10 ²¹ cm ^{−3 of} boron is provided on the drain region side.
(High-concentration region) and n ^- drain region 451 (low-concentration region) of about 1 × 10 ¹⁹ cm ^{−3 of} boron.
Here, the end of the gate electrode 456 is connected to the gate insulating film 45.
5 overlaps with the low-concentration n ^- source region 452 and n ^- drain region 451. On the other hand, the source electrode 4
62 and the drain electrode 463 are connected to the high-concentration n ⁺ source region 458 and the n ⁺ drain region 459.

The thin film transistor 450 having such a configuration
First, as shown in FIG. 8 (a), as shown in FIG. 8 (a), on an insulating substrate 453 made of glass, quartz, sapphire, or the like, boron is added at about 1 × 10 ¹⁹ cm −3 and the film thickness is about 1500 Å. A low-concentration silicon thin film such as polycrystalline silicon is formed and is selectively etched to form a p ^- source region 452 and a p ^- drain region 451. Next, a channel forming region 454 made of a silicon thin film such as polycrystalline silicon having a thickness of 250 Å is formed so as to connect them on the surface side of the p ⁻ source region 452 and the p ⁻ drain region 451.
To form Thereafter, a gate insulating film 455 made of a silicon oxide film is formed on the entire surface by ECR-CVD. Subsequently, a gate electrode 456 made of a metal, a transparent conductive film, a polycrystalline silicon film to which impurities are added, or the like is formed. Here, the end of the gate electrode 456 is connected to the p ⁻ source region 452.
And the end of p ⁻ drain region 453 via gate insulating film 455.

Next, as shown in FIG. 8B, a resist pattern 4 covering predetermined regions of the P ^- source region 452 and the P ^- drain region 453 is formed by using a light exposure technique or the like.
57 is formed, and boron is ion-implanted using this as a mask. Then, a laser beam is irradiated to activate the impurities.

Next, the resist pattern 457 is removed,
Thereafter, as in the normal process, as shown in FIG. 8C, after a layer insulating film 460 made of a silicon oxide film is formed, a contact hole 461 is formed therein.
Thereafter, the source electrode 462 and the drain electrode 463 made of a metal or a transparent conductive film are connected to the p ⁺ source region 458 and the p ⁺ drain region 453, respectively.

In the thin film transistor 450 manufactured as described above, the p ^- source region 452 and the p ^- drain region 453 are formed before the formation of the gate electrode 456, and thus are similar to those of the thin film transistor according to the second embodiment. Since the p ⁺ source region 458 and the p ⁺ drain region 459 are formed in addition to the above effects, the parasitic resistance is small and a large on-current can be obtained.

(Sixth Embodiment) FIG. 9 is a sectional view showing the structure of a thin film transistor according to a sixth embodiment of the present invention.

In this figure, the thin film transistor 500 of this example is also formed on an insulating substrate 501 such as glass, quartz or sapphire, and its source region 502
Is an approximately 500 Angstroms thick, boron was added about 1 × ¹⁰ 18 ^{cm -3} p ^- silicon layer serving as p ^- a source region 503, boron 1 × ¹⁰ 21 cm
^A p ⁺ source region 504 (a low-resistance region having a high concentration and a large thickness) serving as ap ⁺ silicon film having a thickness of about 2000 angstroms to which about ^{−3 is} added. On the other hand, the drain region 505 also has a thickness of about 500 Å,
P ^- drain region 506, which is a p ^- type silicon film to which boron is added at about 1 × 10 ¹⁸ cm ^−3;
P ⁺ drain region 50 as ap ⁺ -type silicon film having a thickness of about 2000 Å to which about ²¹ cm ^{−3 is} added;
7 (a low-resistance region having a high concentration and a large film thickness). In addition, between the source region 502 and the drain region 505, a channel formation region 508 made of a silicon film or the like formed so as to be connected to these regions, and an insulating film such as a silicon oxide film covering the whole thereof. The semiconductor device includes a gate insulating film 509 and a gate electrode 510 formed of a metal, a transparent conductive film, or the like formed on the surface of the gate insulating film 509. Here, the gate electrode 510 and
The source region 502 and the drain region 505 are not configured in a self-aligned manner, and one end 511 of the gate electrode 510 and the p ⁻ source region 5 of the source region 502 are not formed.
03 (end) has a relatively large overlap area, and similarly, the other end 512 of the gate electrode 510
And the p ^- drain region 506 (end) of the drain region 505 are opposed to each other with a relatively large overlapping area.
Reference numeral 513 denotes an interlayer insulating film.
The source electrode 516 and the drain electrode 517 are connected to the p ⁺ source region 504 and the drain region 50 of the source region 502 through the 13 contact holes 514 and 515, respectively.
5 is electrically connected to the p ⁺ drain region 507.

The thin film transistor 500 having such a configuration
For example, since the p ^- drain region 506 faces the gate electrode 510 on the side of the drain tilt region 505, the electric field intensity near the gate electrode 510 is small, so that the off-current characteristics can be improved. Here, the source region 502 and the drain region 505 are not configured to be self-aligned with the gate electrode 510. That is, the source region 502 and the drain region 5 are formed by ion implantation using the gate electrode 510 as a mask.
Since the source region 502 and the drain region 505 are formed before forming the gate electrode 510 instead of forming the gate electrode 510, the heat resistance of the gate electrode 510 is low, for example, 600 ° C. Even if it does, the impurity can be activated for the source region and the drain region without being restricted by the heat resistance limit. Therefore, the state in which the crystal state is broken can be sufficiently repaired by the introduction of the impurity, so that the trap level in the drain region 505 corresponding to the end of the gate electrode 510 and the vicinity thereof can be reduced. Therefore, the off-current characteristics of the thin film transistor 500 can be further improved.

A method for manufacturing a thin film transistor having such a configuration will be described with reference to FIGS.

FIGS. 10A to 10C are process sectional views showing a part of the method of manufacturing the thin film transistor of this example.

First, as shown in FIG. 10A, an amorphous silicon thin film to which, for example, polon is added to about 1 × 10 ²⁰ cm ⁻³ is formed on an insulating substrate 601 such as glass, quartz, or sapphire by a low-temperature process. About 20
Deposit about 00 angstroms. This amorphous silicon thin film is selectively etched to form ap ⁺ region 60.
2, 603 are formed.

Next, an amorphous silicon film 604 of about 250 Å is formed on the surface side of the p ⁺ regions 602 and 603 so as to connect these regions.
A resist pattern 605 is formed thereon.

Next, as shown in FIG. 10 (b), using the resist pattern 605 as a mask, for example, boron is ion implantation, the concentration is about 5 × ¹⁰ 17 ^{cm -3} p ^-
Regions 606 and 607 are formed.

Here, the p ⁺ region 602 and the p ⁻ region 606
Become the source region 608, and the p ⁺ region 603 and the p ⁻ region 607 become the drain region 609.

A region which is masked by the resist pattern 605 and is not ion-implanted becomes a channel forming region 610.

Next, after the resist pattern 605 is peeled off, for example, in a nitrogen atmosphere at a temperature of about 600 ° C.
Anneal for about 4 hours (solid phase growth method: SPC method) to crystallize the amorphous silicon film and to make the p ⁺ region 60
2, 603 and the p ^- regions 606, 607 are activated.

Next, a gate insulating film 611 made of a silicon oxide film is entirely formed by ECR-CVD.

Next, a gate electrode material made of a metal or the like is deposited on the surface side of the gate insulating film 611, and this gate electrode material is selectively etched by using a light exposure technique or the like to form a gate electrode 612. I do. Here, when the gate electrode 612 is formed by etching, one end 613 and the other end 614 of the gate electrode 612 are
The p ^- regions 606 and 607 are overlapped on one end.

Thereafter, FIG. 10
As shown in (c), after forming an interlayer insulating film 615 made of a silicon oxide film and contact holes 616 and 617, a high concentration source region (p ⁺ region 60) of the source region is formed.
2), a source electrode conductively connected to the drain electrode and a drain electrode conductively connected to the high-concentration drain region (p ⁺ region 603) of the drain region are formed.
00 is formed.

(Seventh Embodiment) Next, FIGS.
With reference to (e), an example of a semiconductor device including a CMOS circuit constituted by thin film transistors according to the first to sixth embodiments will be described.

As shown in FIG. 11E, the CMOS circuit 700 of the semiconductor device of the present example has an n-channel thin film transistor 700a and a p-channel thin film transistor 700a on the same insulating substrate 701 made of glass, quartz, sapphire or the like. Type thin film transistor 700b, and in any of the thin film transistors, the ends of the gate electrodes 714 and 715
12 and 713 are overlapped by an n ⁻ source region 706, an n ⁻ drain region 707, and a p ⁻ source region 7.
08 and p ^- drain region 709 (low concentration region). On the other hand, the source electrodes 724 and 725 and the drain electrodes 726 and 727 are connected to the n ⁺ source region 719, the p ⁺ source region 722, the n ⁺ drain region 720 and the p ⁺ drain region 723 (high concentration Area).

In manufacturing the CMOS circuit 700 having such a structure, first, as shown in FIG. 11A, a film thickness of about 700 angstroms is formed on the surface side of an insulating substrate 701 made of glass, quartz, sapphire or the like. After a silicon thin film such as polycrystalline silicon is formed, it is selectively etched to form a silicon thin film pattern 70.
2, 703, 704 and 705 are formed.

Thereafter, phosphorus ions are implanted into the silicon thin film patterns 702 and 703 by a well-known method, and these are implanted into the n ^- source region 706 and the n ^- drain region 707 of about 5 × 10 ¹⁸ cm ^−3. I do. on the other hand,
The pattern of the silicon thin film 704 and 705 are boron ions are implanted, they 5 × ¹⁰ 18 ^{cm -3} of about p
^A source region 708 and a p ^- drain region 709.

Next, as shown in FIG. 11B, the n ⁻ source region 706 and the n ⁻ drain region 707 are
^- a source region 708 and the p ^- as the drain region 709 to each other are connected to form a channel forming region 710, 711 having a thickness made of silicon thin film such as polycrystalline silicon of about 1000 angstroms. Subsequently, the whole is thermally oxidized to form a gate insulating film 71 made of a silicon oxide film.
2, 713 are formed. This thermal oxidation treatment is performed by ion-implanted n ^- source region 706, n ^- drain region 707,
This has the effect of activating the impurities in p ^- source region 708 and p ^- drain region 709. Next, a gate electrode 714 made of metal, a transparent conductive film, doped polycrystalline silicon, or the like is formed on the gate insulating films 712 and 713.
715 is formed. Here, the gate electrodes 714 and 715
End portions of the gate insulating films 712 and 713 through n ⁻
The source region 706, the n ^- drain region 707, the p ^- source region 708, and the end of the p ^- drain region 709 overlap with each other.

Next, as shown in FIG. 11C, after forming an interlayer insulating film 716 made of a silicon oxide film, a contact hole 717 is formed therein. Then, the p ^- source region 708 and the p-
^- side of the drain region 709 (the side of the p-channel thin film transistor 700b) forming a footwear cormorants resist pattern 718, the resist pattern 718 and Sotoi insulating film 716
Is implanted with phosphorus as a mask, and 5 × 10 ²¹ cm
^{Approximately -3} n ⁺ source regions 719 and n ⁺ drain regions 720 are formed.

Next, after removing the resist pattern 718, as shown in FIG. 11D, the n ^- source region 706 and the n ^- drain region
A resist pattern 721 is formed to cover the side 07 (the side of the n-channel thin film transistor 700a). Boron is ion-implanted using the resist pattern 721 and the interlayer insulating film 716 as a mask, and ap of about 5 × 10 ²¹ cm ⁻³ is formed. ⁺
A source region 722 and ap ⁺ drain region 723 are formed.

Next, after removing the resist pattern 721, a laser beam is irradiated to activate each ion-implanted impurity. After that, as shown in FIG. 11E, the source electrodes 724 and 725 and the drain electrode 72 made of a metal, a transparent conductive film, or the like are formed as in a normal process.
6, 727 are connected to n ⁺ source region 719, p ⁺ source region 722, n ⁺ drain region 720, and p ⁺ drain region 723, respectively.

The n-channel thin film transistor 700a and the p-channel thin film transistor 700b thus formed on the same insulating substrate 701 have improved off-current characteristics and on-current characteristics.

(Eighth Embodiment) Next, as an eighth embodiment of the present invention, a configuration of an active matrix substrate with a built-in peripheral circuit of a liquid crystal display panel as a typical device having a thin film transistor will be described.

FIG. 12 is a block diagram showing the overall structure of the active matrix substrate of this example. In the figure, the active matrix substrate 800 is divided into a pixel portion 800a and peripheral circuit portions 800b and 800c (drive circuit portions). In the pixel portion 800a, as shown in FIG.
The scanning area (gate line) 801a, 801b (801) connected to the peripheral circuit section 800b (scanning line driving circuit) and the signal line 802 connected to the peripheral circuit section 800c (signal line driving circuit) form a pixel area. 803 is defined. Here, the pixel portion 800a is connected to the signal line 802 and the pixel electrode 8 based on the scanning signal from the scanning line 801a.
It has a thin film transistor 800d that switches between a connected state and a disconnected state with the side of the thin film transistor 04, and the thin film transistor 800d is required to have a characteristic of a small off-state current. On the other hand, the peripheral circuit units 800b and 800c
Is CMOS with thin film transistors of different conductivity types
A circuit is configured, and this CMOS circuit is required to operate at high speed. Therefore, the pixel portion 800
It is conceivable that a thin film transistor of the present invention is used for a, and a thin film transistor having a self-aligned structure is used for the peripheral circuits 800b and 800c.

The configuration will be described below.

FIG. 14 shows a thin film transistor formed in the pixel portion of the active matrix substrate of this example and three thin film transistors 900a formed in the peripheral circuit portion.
930a and 960a are shown side by side.

In FIG. 14, what is shown on the right side of the drawing is an n-channel thin film transistor 960a formed in the pixel portion, and what is shown in the center of the drawing is the peripheral circuit portion. An n-channel thin film transistor 930a is shown on the left side of the drawing. A p-channel thin film transistor 9 formed in a peripheral circuit portion is shown.
In the peripheral circuit portion, a CMOS circuit is formed by the P-channel thin film transistor 900a and the N-channel thin film transistor 930a.

These thin film transistors 900a, 93
0a and 960a, the n-channel thin film transistor 960a used in the pixel portion is, as described in the first to seventh embodiments, a source region 96a.
1a and drain region 962a are formed in a non-self-aligned manner with respect to gate electrode 963a, and n ^- source region 964a (low-concentration source region) and n ^- drain region 965a (low-concentration drain region) form gate electrode 96a.
It is structured to face the end of 3a. On the other hand, the p-channel thin film transistors 900a and 930a formed in the peripheral circuit group have a self-aligned structure. In the liquid crystal display panel, n of the pixel portion
Drain region 9 of channel type thin film transistor 960a
Although the pixel electrode 62a has a structure in which the pixel electrode is conductively connected, the following description shows a structure in which a normal aluminum electrode is conductively connected in the same manner as the source region 961a.

In such a horizontal active matrix substrate 950a, in the pixel portion, the n-channel thin film transistor 960a has an LDD structure and a structure in which a trap level is reduced. Has been reduced. In contrast, the n-channel and p-channel thin film transistors 900a and 930a formed in the peripheral circuit have a self-aligned structure with small parasitic capacitance. Therefore, the operation speed of the peripheral circuit section is not sacrificed.

(Ninth Embodiment) Next, the configuration of an active matrix substrate with a built-in peripheral circuit for a liquid crystal display panel according to a ninth embodiment will be described.

The active matrix substrate with built-in peripheral circuits of this example and the active matrix substrate with built-in peripheral circuits according to the eighth embodiment have the same basic configuration.
The combination of the thin film transistors used for the pixel region and the peripheral circuit portion (drive circuit portion) is different. In this example,
The off-current characteristics of the thin film transistor used for the pixel portion 800a are improved, and the number of masks used in the manufacturing process of the active matrix substrate 800 is reduced without sacrificing the operation speed of the peripheral circuit portions 800b and 800c. The cost can be reduced.

The structure of the thin film transistor will be described below.

FIG. 15 is a cross-sectional view showing the structure of the thin film transistor formed in the pixel portion of the active matrix substrate and the thin film transistor formed in the peripheral circuit portion in the liquid crystal display panel shown in FIGS.

In FIG. 15, the n-channel type thin film transistor 960 formed in the pixel portion is shown on the right side of the drawing, and the one shown in the center of the drawing is formed in the peripheral circuit portion. An n-channel thin film transistor 930 is shown on the left side of the drawing. A p-channel thin film transistor 900 formed in a peripheral circuit portion is shown.
In the peripheral circuit portion, the p-channel thin film transistor 900 and the n-channel thin film transistor 93
0 forms a CMOS circuit.

These thin film transistors 900 and 93
0 and 960, the n-channel thin film transistor 960 used in the pixel portion and the n-channel thin film transistor 930 formed in the peripheral circuit portion are all described in the first to seventh embodiments. As described above, the source regions 931 and 961 and the drain regions 932 and 962 are formed in a non-self-aligned manner with respect to the gate electrodes 933 and 963, and their n source regions 93
4, 964 (low-concentration source region) and n ^- drain regions 935, 965 (low-concentration drain region) have a structure facing the ends of the gate electrodes 933, 963, but are formed in the peripheral circuit portion. The p-channel type thin film transistor 900 has a self-aligned structure. Note that in the liquid crystal display panel, a pixel electrode is conductively connected to the drain region 962 of the n-channel thin film transistor 960 in the pixel portion. In the following description, a normal aluminum electrode is used similarly to the source region 961. The structure is shown as a conductive connection structure.

In the active matrix substrate 950 having such a structure, in the pixel portion, the n-channel thin film transistor 960 has an LDD structure and a structure in which the trap level is reduced, so that the off-state current is reduced. Has been reduced. On the other hand, since the n-channel thin film transistor 930 formed in the peripheral circuit portion does not have a self-aligned structure, the parasitic capacitance is large and the operation speed is slow as compared with the self-aligned structure. Is concerned. However, one of the n-channel and p-channel thin film transistors has a self-aligned structure with small parasitic capacitance (p-channel thin film transistor in this embodiment). Furthermore, even in a thin film transistor that does not have a self-aligned structure, the source
Since the drain region is a low-concentration region, the parasitic capacitance when a bias is applied in the direction in which the depletion layer extends can be almost ignored.

From this, the CMO with the configuration as in this example is
Even if an S circuit is formed, the operation speed is n-channel type,
The speed is comparable to the case where both the channel type thin film transistors have a self-aligned structure. Therefore, in this example, since two types of thin film transistors are formed on the active matrix substrate 950, the production of the active matrix substrate is compared with the active matrix substrate 950a according to the eighth embodiment using three types of thin film transistors. The number of masks used in the process can be reduced, and productivity can be increased.

(Tenth Embodiment) FIGS. 16A to 16D
In the case where two types of thin film transistors are formed on an active matrix substrate of a liquid crystal display panel as in the ninth embodiment, a process cross-section showing a part of a method of manufacturing each thin film transistor of a pixel portion and a peripheral circuit portion. FIG.

First, as shown in FIG. 16 (a), an amorphous silicon film 1002 is coated on a surface of a substrate 1001 made of glass, quartz, sapphire, etc.
Deposit to a thickness of about angstrom. Resist patterns 1003, 1004, 1005 are formed thereon,
Using this as a mask, phosphorus is ion-implanted so that the impurity is 1 × 1
Low concentration regions 1006, 1007 of about 0 ¹⁷ cm ⁻³ ,
1008 is formed.

Next, the amorphous silicon film 1002 is irradiated with a laser beam to anneal it, thereby polycrystallizing the amorphous silicon film and activating the impurities introduced therein.

Thereafter, as shown in FIG. 16 (b), the amorphous silicon film 1002 is selectively etched to form silicon thin film patterns 1009, 1010, 1010.
11 is formed. Here, the silicon thin film pattern 100
Reference numerals 9 and 1010 denote active regions of the p-channel and n-channel thin film transistors in the peripheral circuit portion, respectively, and the silicon thin film pattern 1011 serves as an active region of the n-channel thin film transistor of the pixel portion. Further, the low-concentration regions 1006, 007, and 1008 have n
N ^- source region 101 of channel type thin film transistor
2, 1013 (low concentration source region) and n ⁻ drain regions 1014 and 1015 (low concentration drain region). Further, regions where impurities are not introduced in the active regions 1010 and 1011 of the n-channel thin film transistor are channel forming regions 1016 and 1017.

Next, after a gate insulating film 1018 made of a silicon oxide film is formed on the entire surface by ECR-CVD, gate electrodes 1019, 1020 and 1021 made of metal or the like are formed on the surface side. I do. Here, among the gate electrodes 1019, 1020, and 1021, n-channel thin film transistors 1023 and 1024
Of the gate electrodes 1020 and 1021 to form
It is in a state of facing n ⁻ source regions 1012 and 1013 and n ⁻ drain regions 1014 and 1015 via gate insulating film 1018. In addition, an extension portion 1015 a (lower electrode) of the drain region 1015 of the thin film transistor 1024 used for the pixel portion is provided with the gate electrode 102
5 overlap to form a storage capacitor portion.

Next, using a light exposure technique or the like, FIG.
As shown in (c), the n-channel type thin film transistor 1
Boron ion implantation is performed in a state in which a resist pattern 1026 covering the formation regions of 023 and 1024 is formed.
In this ion implantation, the gate electrode 1019 is used as a mask, and in the thin film transistor 1022, a source region 1027 and a drain region 1028 having an impurity concentration of about 5 × 10 ²¹ cm ⁻³ are formed in a self-aligned manner.

Next, the resist pattern 1026 is removed, and the impurity is activated by irradiating a laser beam. This laser beam irradiation activates the impurity to lower the resistance and does not repair the crystal state broken by the introduction of the impurity. However, in the p-channel thin film transistor 1022 used for the peripheral circuit portion, It is not required that the off-state current be small. Therefore, in this step, the resistance may be reduced by activating the impurity by laser beam irradiation, and is not required to restore the crystal state.

Thereafter, as shown in FIG.
An interlayer insulating film 1029 is formed, and each thin film transistor 1022, 1023, 1
024, the source electrode 1031 and the drain electrode 1032 are conductively connected.

As described above, in the method of manufacturing an active matrix substrate of this example, the mask patterns related to the introduction of the impurities are two mask patterns 1003,
26. On the other hand, when both the n-channel type and p-channel type thin film transistors constituting the peripheral circuit portion are of a self-aligned type and the thin film transistors used for the pixel portion are to be horizontal in the present invention, 3
One mask is required. Here, as described in the ninth embodiment, the operation speed of the circuit hardly changes between the two (the eighth embodiment and the ninth embodiment). Therefore, the production cost can be reduced by reducing the number of masks without sacrificing the operation speed or the like.

In this embodiment, the n-channel type thin film transistor used in the pixel portion is used. However, the gist of the present invention is not limited to the p-channel type thin film transistor.

Further, in the liquid crystal display panel, FIG.
As shown in FIG. 3, while an extended portion is provided on the drain region side in order to configure the charge storage capacitor portion 805 in the pixel portion,
There is a tendency to adopt a structure in which the preceding scanning line is superimposed on this extended portion. In forming a storage capacitor portion having this structure, in a conventional manufacturing method as a comparative example, as shown in FIGS. 17A and 17B, a resist mask in which an end portion of a polycrystalline silicon film 1101 is opened in a window is formed. 1102
Ions are implanted in the state where the gate electrode 1104 is formed, and ion implantation of high-concentration impurities is performed again using the gate electrode 1104 as a mask. According to the method, as shown in FIGS. 16A and 16B, in the step of introducing a low-concentration impurity, the extension 1015a also automatically becomes a low-concentration region. Then, in the subsequent steps, as shown in FIG. 16B, when the gate electrodes 1019, 1020, and 1021 are formed, the previous scanning line
5 may be superimposed on the extension 1015a. Therefore, the capacity holding portion can be formed with the help of the process of manufacturing the thin film transistor 1024 in the pixel portion without adding another process.

(Eleventh Embodiment) FIGS. 18 (a) to 18 (e)
A CMOS circuit of a driving unit is constituted by an n-channel thin film transistor having a non-self-aligned structure and a p-channel thin film transistor having a small parasitic capacitance and a self-aligned structure capable of operating at high speed; It is a process sectional view showing a part of a manufacturing method of a matrix substrate with a built-in peripheral circuit of a liquid crystal display panel in which a transistor also has a non-self-aligned structure.

In the figure, n-channel type thin film transistors 1300a and 1300C have a source region and a drain region formed of silicon films having different thicknesses, and among them, the film thickness is small and the impurity concentration is 1 × 10 ^19. cm
⁻³ or less n ⁻ source regions 1310, 1311 and n
^- with respect to part of the drain region 1312 and 1313, a gate electrode 1317,1318 overlap each other via the gate insulating film 1316. On the other hand, p-channel thin film transistor 300b is, ^{p +} source region 1323 and p
⁺ Drain region 1324 is formed to be self-aligned with gate electrode 1319.

Here, the n-channel type thin film transistor 1
Of the source and drain regions 300a and 1300c, the regions formed of a thick silicon film are the n ⁺ source regions 1302 and 1303 and the n ⁺ drain regions 1304 and 1305 having high impurity concentrations, and thus have a parasitic resistance. Is prevented from lowering the ON current.

In manufacturing a matrix substrate having such a structure, first, as shown in FIG. 18A, a film having a thickness of about 2000 Å is formed on an insulating substrate 1301 such as glass, quartz, or sapphire. 5 phosphorus
An n ⁺ source region 1302 made of an n ⁺ silicon thin film such as polycrystalline silicon added to about × 10 ²¹ cm ⁻³ ;
1303 and n ⁺ drain regions 1304 and 1305 are formed, and the film thickness is about 5
00 angstrom silicon pattern 1306, 1
307, and a silicon pattern 1308 for forming the p-channel thin film transistor 300b.
Also form.

Next, as shown in FIG. 18B, a resist pattern 1309 is formed by using a light exposure technique, and ions are implanted using the resist pattern as a mask, and the pattern of silicon thin film patterns 1306 and 1307 is changed by 5 times. × 10 ⁺¹⁸ cm ^-3
About the concentration. These regions become n ^- source regions 1310 and 1311 and drain regions 1312 and 1313 of a so-called GOLDD type (gate overlap LDD) thin film transistor. On the other hand, regions of the silicon patterns 1306 and 1307 that have not been ion-implanted become channel formation regions 1314 and 1315.

Next, after the resist pattern 1309 is peeled off, the entire surface is irradiated with a laser beam to activate the implanted ions and to form the channel forming region 131.
4, 1315, the crystal grains are increased to improve the transistor characteristics.

Next, as shown in FIG. 18C, a gate oxide film 1316 made of an insulating film such as a silicon oxide film is formed on the entire surface, and a metal, a transparent conductive film and a multi-layered structure obtained by adding impurities are formed thereon. Gate electrode 131 such as crystalline silicon pus
7, 1318 and 1319 are formed. Here, the gate electrodes 1317 and 1318 are connected to the n ⁻ source region 1310, 1
311 and part of the drain regions 1312 and 1313 overlap with a gate insulating film 1316 interposed therebetween. In addition, part of the n ⁺ drain region 1305 of the thin film transistor used for the pixel portion overlaps with the gate electrode 1320 in the previous stage via the gate insulating film 1316 to form a storage capacitor.

Next, as shown in FIG. 18D, an n-channel thin film transistor 1300 is formed by using a light exposure technique.
a and n-channel type thin film transistor 130 in the image area
The resist patterns 1321 and 1322 that cover 0c are formed, and boron is ion-implanted using the resist patterns as
A p ⁺ source region 1323 and ap ⁺ drain region 1324 of about 10 ²¹ cm ⁻³ are formed. Here, the region not ion-implanted becomes a channel formation region 1325.

Next, the resist patterns 1321, 132
After removing 2, the substrate is irradiated with a laser beam to activate the impurities. Thereafter, as shown in FIG.
As shown in (e), after forming a layer insulating film 1326 made of a silicon oxide film, a contact hole 1327 is formed.
And through these contact holes 1327,
The n ⁺ source region 1302, the n ⁺ source region 1303, and the p ⁺ source region have source electrodes 1328, 1329,
1330 and the n ⁺ drain region 1304 and p
⁺ Drain region 1324 has a drain electrode 1331, 1
332 is connected. In addition, a search electrode 1333 is connected to the n ⁺ drain region 1305 of the thin film transistor in the pixel portion.

As described above, in this example, the gate electrode 13
17 and 1318, the n ^- source region 131 is formed.
To activate the 1 and n ^- drain regions 1313,
Without being restricted by the activation condition, the gate electrode 1
Since the material 318 can be selected, the gate electrode 1318 can be made of metal.

Further, when the n-channel thin film transistor 1300c having a small off-current is provided in the pixel portion, the n-channel thin film transistor 130 in the peripheral circuit group is provided.
Since the structure is the same as that of Oa, the manufacturing process can be simplified. Even in this case, since the p-channel thin film transistor 1300b forming the CMOS circuit in the peripheral circuit portion has a self-aligned structure, the operation speed is not sacrificed. Also, a p-channel type thin film transistor 1
300b has no need to consider off-current characteristics.
A high-concentration source gradient region and a drain region formed from one silicon pattern can minimize the increase in the number of steps.

(Twelfth Embodiment) In this embodiment, an n-channel thin film transistor is used in a pixel portion of a liquid crystal display with a built-in peripheral circuit, and a CMOS circuit is formed by a thin film transistor having a small parasitic capacitance and a self-aligned structure capable of high-speed operation. This is equivalent to a modification of the eighth embodiment using three types of thin film transistors.

FIGS. 19A to 19E are sectional views showing the steps.

As shown in FIG. 19E, in the active matrix substrate of this example, an n-channel thin film transistor 1400a having a so-called GOLDD structure is formed in the pixel portion of the surface of the common insulating substrate 1401, and the periphery is formed. In the circuit portion, the CMO is formed by n-channel and p-channel thin film transistors 1400b and 1400c having a self-aligned structure.
An S circuit is configured.

In manufacturing these thin film transistors, first, as shown in FIG. 19A, a polycrystalline silicon thin film is deposited on the surface of an insulating substrate 1401 made of glass or the like, for example, at about 1000 Å, and selectively deposited. To the silicon thin film pattern 1
402, 1403, 1404, 1405, 1406, 1
407 is formed. Subsequently, phosphorus ions are implanted into the entire surface to form silicon thin film patterns 1402, 1403, and 14.
04, 1405, 1406, 1407 is 5 × 10 ⁺¹⁸
The concentration is set to about cm ⁻³ .

Next, a silicon thin film pattern 1402,
1003 to connect 1403 to each other, 1404 and 1405 to each other, and 1406 and 1407 to each other.
Channel forming regions 1408 and 1401 made of a silicon thin film such as a polycrystalline silicon film of about 0 Å.
9, 1410 are formed.

Next, as shown in FIG. 19B, the entire surface is thermally oxidized to form gate insulating films 1411, 1412, and 1413 made of a silicon oxide film. This heat treatment also has the effect of activating the implanted ions. Next, the gate insulating films 1411, 1412, 141
A gate electrode 14 made of a metal, a transparent conductive film, a polycrystalline silicon film doped with impurities,
14, 1415 and 1416 are formed. Here, the gate electrode 1411 has a pattern 140 of n ^- silicon thin film.
2 and 1403 overlap with a gate insulating film 1411 interposed therebetween. On the other hand, the gate electrodes 1415 and 141
6 are n ^- silicon thin film patterns 1404, 1 respectively.
405 does not overlap.

Next, as shown in FIG. 19C, a resist pattern 1417 is formed by using a light exposure technique so as to cover at least the end of the gate electrode of the p-channel thin film transistor and the n-channel thin film transistor of the pixel portion.
1418 is formed, and phosphorus is ion-implanted using the mask as a mask to form n ⁺ -type source regions 1419, 1420 and n ^+.
Form drain regions 1421 and 1422 are formed.

Next, resist patterns 14147, 14
After removing 18, as shown in FIG. 19D, resist patterns 1423 and 1424 are formed in a region covering the n-channel transistor and the n-channel transistor in the search area by using a light exposure technique or the like. Then, boron is ion-implanted using these as masks to form p ⁺ source region 1425 and p ⁺ drain region 14 of about 5 × 10 ²¹ cm ^−3.
26 is formed.

Next, the resist patterns 1417, 141
After removing 8, as shown in FIG. 19 (e), a laser beam is irradiated to activate the impurities. Later,
As in a normal process, the source electrodes 1427, 1428, 1429 and the drain electrodes 1430, 1431, 1432 made of a metal, a transparent conductive film or the like are respectively connected to n ⁺ source regions 1419, 1420, p ⁺ source regions 1425, n
⁺ Drain regions 1421 and 1422 and p ⁺ drain region 1426, a so-called GOLDD cotton n-channel thin film transistor 1400a is formed in the search portion, and a self-aligned n-channel type and p-type thin film transistor are formed in the peripheral circuit portion. Channel type thin film transistor 1400b, 1
Form 400c.

[0135]

As described above, according to the present invention, in the source region and the drain region, the region overlapping with the end of the gate electrode via the gate insulating film is formed in a step before the gate electrode. It is characterized by a low agricultural level. Therefore, according to the present invention, when activating the impurity introduced into the source region or the drain region, the gate electrode is still formed. Therefore,
Impurities can be activated without being restricted by the heat resistance of the constituent materials of the gate electrode, and the collapse of the crystal state caused by the introduction of impurities can be sufficiently repaired, reducing trap levels in the drain region and its vicinity. can do. Further, since the drain region overlaps with the gate electrode in the low concentration region, the electric field intensity there is small. Therefore, the off-current characteristic of the thin film transistor can be improved.

When the low-concentration region is a region in which the silicon film is subjected to crystallization after the impurity is introduced, the number of steps is reduced and the productivity is increased. After the treatment, the crystal state does not collapse due to the introduction of impurities, and the off-current characteristics are further improved.

When the thickness of the low concentration region is equal to the thickness of the channel formation region, the surface is flattened and there is no local concentration of the electric field, so that the off-current characteristic is improved. If the thickness of the low-concentration region is smaller than the thickness of the depletion layer defined by the impurity concentration, the depletion layer reaches the lower surface of the low-concentration region. , The parasitic capacitance decreases.

When a thick region or a high-concentration region connected to the low-incidence gradient region is provided in the source region and the drain region, they reduce the parasitic resistance, so that the operating speed is not sacrificed.

In a liquid crystal display panel having the above-mentioned thin film transistor (n-channel thin film transistor) in a pixel portion, the n-channel thin film transistor is advantageous in the CMOS circuit of the drive circuit portion, while the p-channel thin film transistor and the p-channel thin film transistor constituting the CMOS circuit are advantageous. When a self-aligned structure is adopted for the thin film transistor, the respective steps can be used to the maximum extent, the steps can be simplified, and a high-speed operation of the drive circuit can be realized. Here, in the self-aligned thin film transistor, severe conditions for off-state current characteristics cannot be given to the drive circuit portion. Therefore, by forming the thin film transistor as an integrated high-concentration region, an increase in the number of steps can be minimized. You can stop it.

Further, in the liquid crystal display panel, when the drain region is provided with an extended region which is formed simultaneously with the low-concentration region and the like and in which a storage capacitor is to be formed between the drain region and the previous gate line, The storage capacitor can be formed while using the above process.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a thin film transistor according to a first embodiment of the present invention.

2A is a graph showing off-current characteristics of the thin-film transistor shown in FIG. 1, and FIG. 2B is a graph showing off-current characteristics of a thin-film transistor according to a comparative example.

3A is an explanatory diagram showing a parasitic capacitance of the thin film transistor shown in FIG. 1, and FIG. 3B is an explanatory diagram showing a parasitic capacitance of a thin film transistor according to a comparative example.

4 (a) to 4 (d) are process sectional views showing a part of a method for manufacturing the thin film transistor shown in FIG. 1. FIG.

FIGS. 5A to 5C are process cross-sectional views showing a part of a method for manufacturing a thin film transistor according to a second embodiment of the present invention.

FIGS. 6A to 6D are process cross-sectional views showing a part of a method for manufacturing a thin film transistor according to a third embodiment of the present invention.

FIG. 7 is a sectional view showing a structure of a thin film transistor according to a fourth embodiment of the present invention.

FIGS. 8A to 8C are process cross-sectional views showing a part of a method for manufacturing a thin film transistor according to a fifth embodiment of the present invention.

FIG. 9 is a sectional view showing a structure of a thin film transistor according to a sixth embodiment of the present invention.

10 (a) to 10 (c) are cross-sectional views showing steps of a method for manufacturing the thin film transistor shown in FIG. 9;

FIGS. 11A to 11E are process cross-sectional views illustrating a part of a method of manufacturing a CMOS circuit (semiconductor device) including a thin film transistor according to a seventh embodiment of the present invention.

FIG. 12 is a block diagram illustrating a configuration of a liquid crystal display panel.

FIG. 13 is a plan view showing a configuration of each pixel region of a pixel portion of the liquid crystal display panel shown in FIG.

FIG. 14 is a sectional view of a thin film transistor formed on an active matrix substrate of a liquid crystal display panel according to an eighth embodiment of the present invention.

FIG. 15 is a sectional view of a thin film transistor formed on an active matrix substrate of a liquid crystal display panel according to a ninth embodiment of the present invention.

FIGS. 16 (a) to (d) show a tenth embodiment of the present invention.
FIG. 9 is a process cross-sectional view illustrating a part of the method for manufacturing the thin film transistor formed on the active matrix substrate of the liquid crystal display panel according to the example.

17 (a) and 17 (b) are cross-sectional views showing steps of a method for manufacturing a capacitor holding portion in a pixel portion in a conventional liquid crystal display panel.

FIGS. 18 (a) to (e) show an eleventh embodiment of the present invention.
FIG. 9 is a process cross-sectional view illustrating a part of the method for manufacturing the thin film transistor formed on the active matrix substrate of the liquid crystal display panel according to the example.

FIGS. 19 (a) to (e) show a twelfth embodiment of the present invention.
FIG. 9 is a process cross-sectional view illustrating a part of the method for manufacturing the thin film transistor formed on the active matrix substrate of the liquid crystal display panel according to the example.

FIG. 20 is a cross-sectional view illustrating a structure of a transistor.

FIG. 21 is a graph showing off-current characteristics of a conventional thin film transistor.

FIGS. 22A to 22D are cross-sectional views illustrating another conventional method for manufacturing a thin film transistor.

Claims (22)

[Claims] 1. A channel forming region capable of forming a channel between a source region and a drain region on a surface side of a substrate, and a gate electrode facing the surface side of the channel forming region via a gate insulating film. A region that overlaps with the end of the gate electrode via the gate insulating film in the source region and the drain region,
A thin film transistor, which is a low intensity region formed in a step before the gate electrode. 2. The thin film transistor according to claim 1, wherein the impurity concentration of the low concentration region is 1 × 10 ²⁰ cm ⁻³ or less. 3. The low-concentration region according to claim 1, wherein the low-concentration region is a region in which an impurity is introduced into a silicon film formed on a surface side of the substrate and then subjected to crystallization treatment. A thin film transistor, comprising: 4. The semiconductor device according to claim 1, wherein the source region and the drain region are
A thin film transistor comprising a low resistance region connected to the low concentration region with a high impurity concentration. 5. The low-resistance region according to claim 1, wherein each of the source region and the drain region is connected to the low-concentration region with a greater thickness than the low-concentration region. A thin film transistor, comprising: 6. The thin film transistor according to claim 1, wherein the channel formation region, the source region, and the drain region are regions formed in different steps. . 7. The thin film transistor according to claim 1, wherein the thickness of the low concentration region is equal to the thickness of the channel formation region. 8. The low-concentration region according to claim 1, wherein the thickness of the low-concentration region is determined by the impurity concentration of the low-low region when a potential is applied to the gate electrode. A thin film transistor having a thickness smaller than a thickness of a depletion layer formed in a state where the thickness is defined. 9. The thin film transistor according to claim 1, wherein the low concentration region has a thickness of about 500 Å or less. 10. A solid-state device comprising the thin-film transistor defined in any one of claims 1 to 9. 11. A thin film transistor according to claim 1, wherein said thin film transistor is of a reverse conductivity type to said thin film transistor, and said source and drain regions are self-aligned with respect to a gate electrode. A solid-state device comprising: a CMOS circuit configured by using a thin film transistor formed in the semiconductor device. 12. A display device characterized by having the thin film transistor defined in any one of claims 1 to 9 as a pixel transistor of an active matrix array. 13. The drain region according to claim 12, wherein the drain region includes a constituent part thereof. A display device, which is formed simultaneously and has an extension region in which a storage capacitor is to be formed between the scanning line and a preceding scanning line. 14. The driving circuit section according to claim 12, wherein said driving circuit section is formed on the same substrate together with said active matrix array.
The circuit includes a non-self-aligned thin film transistor having the same structure as the thin film transistor, and a thin film transistor having a conductivity type opposite to the thin film transistor and formed in a self-aligned manner with respect to the gate electrode. Display device. 15. A driving circuit formed on the same substrate together with said active matrix array according to claim 12 or 13, wherein said CMOS circuit is formed in a self-aligned n-channel with respect to a gate electrode. A display device comprising a thin film transistor and a p-channel thin film transistor. 16. The thin film transistor according to claim 14, wherein the thin film transistor is formed on the substrate.
A display device, wherein the thickness of the source region and the drain region of the self-aligned thin film transistor is equal to the thickness of the low concentration region of the non-self aligned thin film transistor. 17. The self-aligned thin-film transistor according to claim 14, wherein the source region and the drain region of the self-aligned thin-film transistor have an impurity concentration of about 1%.
A is × ¹⁰ 20 ^{cm -3} or higher, the low-concentration region of a non self-aligned thin film transistor of said display device, wherein the impurity concentration is about 1 × ¹⁰ 20 ^{cm -3} or less. 18. The method for manufacturing a thin film transistor according to claim 1, wherein the step of forming the low concentration region on the surface side of the substrate is performed at least before the step of forming the gate electrode. Manufacturing method of a thin film transistor. 19. The method according to claim 18, wherein at least a silicon film on which the low-concentration region is to be formed is formed, and a crystallization process performed on the silicon film after introducing the impurity into the silicon film is performed. A method for manufacturing a thin film transistor, which also serves as a thin film transistor. 20. The method according to claim 18, wherein the crystallization treatment is a laser annealing method for irradiating the silicon film with a laser beam to crystallize the silicon film and activate impurities therein. Specialized teaching method of manufacturing thin film transistors. 21. The solid-phase growth method according to claim 18, wherein the crystallization treatment includes annealing the silicon film at a low temperature for a long time to crystallize the silicon film and activate impurities therein. A method for manufacturing a thin film transistor, comprising: 22. The crystallization process according to claim 18, wherein the crystallization process is a rapid thermal anneal method of performing lamp annealing on the silicon film to crystallize the silicon film and activating impurities therein. A method for manufacturing a thin film transistor.