JPH11330463A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of a transistor, since the possibility of the penetration of an impurity through a gate insulation film becomes low due to the lightly doped impurity at the side of the gate insulation film in a gate electrode. SOLUTION: In a semiconductor device, consisting of an insulation-gate-type field effect transistor 10, a gate electrode 12 of the insulation-gate-type field effect transistor 10 is made of silicon or silicon germanium containing an impurity, the concentration of the impurity in the gate electrode 12 becomes lower, closer it is toward the side of the gate insulation film 11 of the insulation-gate- type field effect transistor 10. After a semiconductor film for forming the germanium electrode 12 is formed, crystallization annealing is made by excimer laser annealing(ELA) and the patterning is made to the gate electrode 12 for formation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device formed of an insulated gate field effect transistor having a gate electrode of silicon or silicon germanium and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a conventional insulated gate type field effect transistor, for example, MOS (Metal-Oxide-Semiconductor) is used.
9) The structure of the transistor will be described with reference to the schematic configuration sectional view of FIG. 9A and the impurity concentration profile in the gate electrode shown in FIG.

As shown in FIG. 9A, a gate electrode 112 is formed on a substrate 100 made of a silicon substrate with a gate insulating film 111 interposed therebetween. -Drains 113 and 114 are formed. And FIG. 9 shows (2)
As shown in FIG. 5, the impurity (boron) concentration profile in the gate electrode 112 has a substantially uniformed concentration profile. In (2) of FIG. 9, the vertical axis indicates the boron concentration, and the horizontal axis indicates the position.

Next, a conventional method for manufacturing an insulated gate field effect transistor will be described below. First, as shown in FIG. 10A, a substrate 100 made of a silicon substrate having an active region 101 and an element isolation region 102 is provided.
A gate insulating film 111 is formed on the active region 101 of FIG.

Next, as shown in FIG. 10B, a semiconductor film 121 made of silicon or silicon germanium is formed on the gate insulating film 111. At this time, the semiconductor film 121 is also formed on the element isolation region 102. The semiconductor film 121 is doped with an impurity. Alternatively, the semiconductor film 121 may be formed including impurities.

Then, as shown in FIG. 10C, after the semiconductor film 121 is patterned to form the gate electrode 112, crystallization annealing for activating the gate electrode 112 is performed by excimer laser light irradiation. Performed by Thereafter, as shown in (4) of FIG.
12 are formed in the active region 101 on both sides of the MOS transistor 1.
10 was formed.

In the above manufacturing method, in order to make the gate electrode low-resistance and high-performance, for example, 900 ° C., 30 °
It is necessary to perform thermal annealing for more than one minute. Then R
TA (Rapid Thermal Annealing) is one promising technology, but it is difficult to irradiate with sub-second accuracy. In the case where a silicon film or a semiconductor film made of a silicon germanium film formed by the above sputtering is activated and annealed, an inert element such as argon in a film formation atmosphere remains in the formed film, and this is a solid phase. Is to prevent crystallization.

Therefore, activation annealing with less diffusion is required. Excimer laser annealing (hereinafter referred to as ELA, ELA) is used as such annealing.
Stands for Excimer Laser Annealing). This ELA
Can prevent crystallization in the solid phase from being hindered by an inert element remaining in the film.
7th ESSDERC (European Solid-State Device Res
earch Conference) (Germany), (1997) T.Stonicki et a
l., pp. 216-219.

The ELA described above is a promising technique for activation annealing in the future, since it hardly heats the base. LCD (Liquid Crystal Device) manufacturing technology has begun to be used for crystallization of TFT (Thin Film Toransistor). Also, it has already begun to be used for activation of source / drain.

[0010]

In MOS transistors that have been miniaturized with the recent increase in the degree of integration of semiconductor devices, the thickness of the gate oxide film has been reduced. Especially p
In a MOS transistor having a gate electrode composed of a gate semiconductor film, boron diffuses to the interface between the lower gate oxide film and the silicon substrate, causing a problem that the threshold value fluctuates. This problem of penetration of boron is even more pronounced when boron difluoride having a deep implantation depth is doped into the gate electrode by ion implantation than when boron is ion-implanted [IEEE (Instit
ute of Electrical and Electronics Engineers) Tran
sactions on Electron Devices (USA), 37 [11] (1990) J
anmye James Sung, Chin-Yuan Lu, p.2312-2321].

In the conventional semiconductor device described with reference to FIG. 10, the concentration of boron in the vicinity of the gate insulating film of the p-type gate electrode doped with boron as an impurity is particularly large in the thermal process performed after patterning the gate electrode. , A phenomenon occurs that the boron penetrates the gate insulating film. As a result, the impurity concentration of the channel region changes, and the threshold voltage does not become an appropriate value, thereby deteriorating the transistor characteristics.

In the conventional manufacturing method, since the crystallization annealing for activation is performed after the semiconductor film is patterned into the gate electrode, the difference in the amount of heat stored in the base between the active region and the element isolation region is obtained. The annealing temperature varies depending on the temperature. For this reason, uniform crystallization is difficult, resulting in deterioration of transistor characteristics.

As described above, in annealing using a gate as a mask in the process of forming a fine MOS transistor, heat is accumulated in a semiconductor thin film by ELA on finely patterned polysilicon, and uniform crystallization is achieved. It is difficult to perform this process, and when the underlying insulating film is thin, a higher energy density is required than on a thick insulating film, as described in the Japan Journal of Applied Physics, 32 P
art2,7B (1993) H.Tsukamoto, H.Yamamoto, T.Noguchi, T.
Suzuki, P.L967-970.

[0014]

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device and a method of manufacturing the same to solve the above-mentioned problems.

That is, the semiconductor device comprises an insulated gate field effect transistor, the gate electrode of which is made of silicon or silicon germanium containing impurities, and the impurity concentration in the gate electrode is insulated gate field effect transistor. Becomes lower toward the gate insulating film side.

In the above semiconductor device, since the impurity concentration on the gate insulating film side of the gate electrode is low, the possibility that impurities penetrate the gate insulating film is reduced, and the reliability of the transistor is improved.

A first method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device comprising an insulated gate type field effect transistor, wherein a substrate having an active region and an element isolation region is used, and a gate insulating film is formed on the active region. Forming a film, forming a semiconductor film made of silicon or silicon germanium and containing impurities on the gate insulating film, and performing crystallization annealing for activation by irradiating the semiconductor film with ultraviolet pulse light And a step of patterning the crystallized semiconductor film to form a gate electrode.

In the first method of manufacturing a semiconductor device, since the semiconductor film is crystallized and annealed before patterning the semiconductor film into a gate electrode, the heat generated by the annealing spreads in the lateral direction of the semiconductor film, and the influence of the underlayer influences. Hard to receive. Therefore, the annealing can be performed at a uniform temperature regardless of whether the underlying layer is the active region or the element isolation region, so that the semiconductor film is uniformly crystallized. Since the gate electrode is formed of the semiconductor film on which such uniform crystallization is performed, the transistor characteristics can be improved.

A second method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device comprising an insulated gate field effect transistor, which is made of activated silicon or silicon germanium containing impurities, and which has a concentration of this impurity. A step of forming a gate electrode that becomes lower toward the gate insulating film side of the insulated gate field effect transistor, and performing a heat step after forming the gate electrode at a temperature that hardly changes the impurity concentration profile. Is the way.

In the second method for manufacturing a semiconductor device, since the impurity concentration on the gate insulating film side in the gate electrode is low, the possibility that impurities penetrate the gate insulating film is reduced, and the reliability of the transistor is improved. . In addition, since the thermal process after forming the gate electrode is performed at a temperature applied in the thermal process without changing the concentration profile of the impurity, the possibility that the impurity penetrates the gate insulating film is further reduced, The reliability of the transistor is improved.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment relating to a semiconductor device comprising an insulated gate field effect transistor according to the present invention will be described with reference to FIG. In FIG. 1, (1) shows a schematic configuration diagram, and (2) shows an example of an impurity concentration profile in a gate electrode.

As shown in FIG. 1A, a substrate 1 made of a silicon substrate has an active region 2 electrically shunted by an element isolation region 3. This active area 2
A gate insulating film 11 is formed thereon, for example, by a silicon oxide film. On this gate insulating film 11, a gate electrode 12 is formed. The gate electrode 12 is made of, for example, silicon germanium doped with an impurity. Here, as an example, boron which is a p-type impurity is doped. Source / drain 13 and 14 are formed on the substrate 1 on both sides of the gate electrode 12.

As shown in FIG. 1B, the boron concentration profile (shown by a solid line) in the gate electrode 12 has a profile that becomes lower toward the gate insulating film 11 side. On the other hand, the conventional concentration profile (shown by a dotted line) is almost uniform in the gate electrode. In FIG. 1B, the ordinate indicates the boron concentration, and the abscissa indicates the position. As described above, the insulated gate field effect transistor 10 is configured.

The above-mentioned insulated gate field effect transistor 1
In the case of 0, the boron concentration on the gate insulating film 11 side of the gate electrode 12 is low, so the possibility that boron penetrates the gate insulating film 11 is reduced, and the reliability of the transistor is improved.

The above-mentioned insulated gate field effect transistor 1
Numeral 0 is a so-called bulk silicon MOS transistor. For example, a similar gate electrode structure can be applied to a TFT formed on an SOI (Silicon on Insulator) substrate.

It is of course possible to use a silicon substrate as the base substrate 1 as described above. Further, a substrate in which a silicon oxide film is formed over a silicon substrate, a quartz substrate, an alkali-free glass substrate, or a resin substrate may be used. When these substrates are used, it is necessary that a semiconductor layer to be an active region of a transistor be formed.

The gate insulating film 11 may be a silicon oxide film, a silicon oxynitride film, or a laminated film thereof. The film formation method includes thermal oxidation, thermal nitridation, and chemical vapor deposition (hereinafter, referred to as CVD).
Chemical Vapor Deposition) or sputtering.

Although the gate electrode 12 is formed of a silicon germanium film, it may be a silicon film, for example. The film formation method is sputtering or CV
Method D (for example, low pressure CVD, ultra high vacuum CVD,
Plasma enhanced CVD method or the like).

Next, an embodiment relating to a first method for manufacturing a semiconductor device comprising an insulated gate field effect transistor of the present invention will be described with reference to the manufacturing process diagram of FIG. FIG.
In the following, a CMOS process will be described as an example, and the same components as those described with reference to FIG.

As shown in FIG. 2A, an element isolation process is performed on a substrate 1 made of a bulk silicon substrate. That is, the conventional local oxidation method [for example, LOCOS (Loca
(l Oxidation of Silicon) method] or a trench method to form an element isolation region 3 for electrically isolating an nMOS region and a pMOS region. Further, a p-well 2p is formed in the nMOS region, and an n-well 2n is formed in the pMOS region. Then, for example, by thermal oxidation, p
The gate insulating film 11 is formed on the well 2p and the n-well 2n.
Is formed to a thickness of 5 nm with, for example, silicon oxide.

Next, as shown in FIG. 2B, a semiconductor film 21 is formed on the gate insulating film 11, the element isolation region 3 and the like by, for example, sputtering, for example, using silicon germanium (SiGe _x : 0 <X ≦ X). 0.5), for example, 80
It is formed to a thickness of nm. At this time, the semiconductor film 21 is formed such that boron is doped, for example, at a maximum of about 5 × 10 ²⁰ atoms / cm ³ .

Further, following the formation of the semiconductor film 21 by sputtering, the silicon film 22
It is formed to a thickness of 0 nm. By forming the cap of the silicon film 22 on the semiconductor film 21 in this manner, a normal silicon process can be performed, and the cleaning process can use the conventional cleaning conditions. Note that each of the above films can be formed by a chemical vapor deposition (hereinafter, referred to as CVD, which is abbreviation of Chemical Vapor Deposition) instead of sputtering.

Next, the semiconductor film 21 is doped with boron by an ion implantation method. As an example of the ion implantation conditions, the implantation energy is set to 7 keV and the dose is set to 4 × 10 ¹⁵ / cm ² . In the case of the semiconductor film 21 made of silicon germanium containing about 50% germanium, the band gap can be narrowed,
In a CMOS, the threshold value needs to be controlled only for the p-channel transistor.

Subsequently, as shown in FIG. 2C, ELA is performed on the semiconductor film 21. For example, irradiation is performed in a single shot of a two-chip batch shot, and the irradiation energy density at that time is, for example, 500 mJ / cm ² . As a result, even the semiconductor film 21 formed by sputtering can be effectively crystallized and the resistance can be reduced. Since the silicon germanium film forming the semiconductor film 21 has a lower melting point than the silicon film, crystallization can be performed with a particularly low irradiation energy density. For example, when controlling to a uniform energy beam, chip or wafer batch ELA is also advantageous. In the above ELA, for example, 220 mJ / cm
It may be irradiated by two shots in the ^second energy density.

Next, as shown in FIG. 2D, a resist mask used for etching for forming a gate electrode is formed by a normal resist coating and lithography technique, and then the semiconductor film 21 is etched by an etching technique to form a gate. Electrodes 12 (12n), 12 (12p)
To form In this etching, the gate insulating film 11 is also etched to expose the p well 2p and the n well 2n. After that, the resist mask is removed.

After that, source and drain are formed. First, in order to form the source / drain of the n-channel MOS transistor, a resist mask (not shown) having an opening in the formation region of the n-channel MOS transistor is formed by usual resist coating and lithography techniques.
Then, ion implantation is performed. This ion implantation, for example,
Arsenic (As ⁺ ) is used as an impurity, the implantation energy is set to ¹⁵ keV, and the dose is set to 2 × 10 ¹⁵ / cm ² .

After that, the resist mask is removed.
Next, a resist mask (not shown) having an opening in the formation region of the p-channel MOS transistor is formed by ordinary resist coating and lithography techniques. Then, ion implantation is performed. This ion implantation is performed, for example, by using boron difluoride (BF ₂ ⁺ ) as an impurity, setting the implantation energy to 10 keV, and setting the dose to 2 × 10 ¹⁵ / cm ² .

Thereafter, the resist mask is removed.
Next, annealing is performed at 940 ° C. for 10 minutes. As a result, n wells 2n on both sides of gate electrode 12p
Source / drain 13p, 14p are formed, and source / drain 13n, 14n are formed in p well 2p on both sides of gate electrode 12n.

However, when forming an LDD in the above process, although not shown, before forming the above-mentioned source / drain, when forming an n-channel MOS transistor, for example, arsenic is used as an impurity, The implantation energy is 7 keV and the dose is 2 × 10 ¹⁴ /
The ion implantation is performed by setting to cm ² . When a p-channel MOS transistor is formed, for example, boron difluoride is used as an impurity and the implantation energy is set to 5 k.
Ion implantation is performed with the eV and the dose set at 2 × 10 ¹⁴ / cm ² . Then, after forming the sidewall,
The source / drain is formed. When forming the LDD, a resist mask is formed in the same manner as when forming the source / drain.

Thereafter, although not shown, a normal process of forming an interlayer insulating film, a process of forming a metal wiring, and the like are performed to form an n-channel insulated gate field effect transistor 10n and a p-channel insulated gate field effect transistor. The transistor 10p is completed.

The n-channel insulated gate field-effect transistor 10n and the p-channel insulated gate field-effect transistor 10p formed by the above-described manufacturing method are as follows.
It is a so-called bulk silicon MOS transistor,
For example, the above manufacturing method can be applied to a TFT formed on an SOI substrate.

It is of course possible to use a silicon substrate as the base substrate 1 as described above. Alternatively, as the substrate 1, a substrate in which a silicon oxide film is formed over a silicon substrate, a quartz substrate, a glass (non-alkali glass) substrate, a resin substrate, or a film substrate can be used. However, it is necessary that a semiconductor layer to be an active region of a transistor is formed on these substrates.

Although the semiconductor film 21 is made of a silicon germanium film, it may be a silicon film, and the film may be a non-doped film or a boron-doped film. However, in the case of a non-doped film, it is necessary to dope impurities by a subsequent doping technique. The method for forming the semiconductor film 21 is sputtering,
Or CVD method (for example, low pressure CVD, ultra high vacuum C
VD, plasma enhancement CVD).

The gate insulating film 11 may be a silicon oxide film, a silicon oxynitride film, or a laminated film thereof. The film formation method includes thermal oxidation, thermal nitridation, C
Any of VD and sputtering may be used.

Excimer laser light or all solid-state laser light can be used as the ultraviolet pulse light. The irradiation method is multi shot, single batch shot,
Any of the scanning shots may be used.

In the first method of manufacturing a semiconductor device, the semiconductor film 21 is subjected to crystallization annealing before patterning the semiconductor film 21 into the gate electrodes 12n and 12p. Spread, making it less susceptible to the influence of the groundwork. Therefore, regardless of whether the base is the active region substrate 1 or the element isolation region 3, annealing can be performed at a substantially uniform temperature, so that the semiconductor film 21 is substantially uniformly crystallized. The gate electrode 1 is formed of the semiconductor film 21 having such uniform crystallization.
Since 2n and 12p are formed, the transistor characteristics can be improved.

Next, the relationship between the sheet resistance of the semiconductor film 21 and the pulse energy density of ELA was examined. Excimer laser light having a wavelength of 308 nm was used, and the number of times of irradiation was two shots. As a result, at a pulse energy density of 160 mJ / cm ² , the sheet resistance is about 790Ω /
□ At a pulse energy density of 185 mJ / cm ^2, the sheet resistance is about 540 Ω / □, 210 mJ / cm ²
The sheet resistance is about 42 at the pulse energy density of
0 Ω / □, and it was found that the sheet resistance decreased as the pulse energy density increased.

Next, the C of the insulated gate type field effect transistor manufactured according to the manufacturing process described with reference to FIG.
FIG. 3 shows the V characteristics. In the figure, the vertical axis shows the capacitance ratio C / Cox, and the horizontal axis shows the gate voltage. However, the thickness of the gate insulating film 11 here is 9 nm.

FIG. 3A shows a case where a gate electrode is formed of silicon germanium formed by sputtering,
LA (pulse energy density = 160 mJ / cm ² , 1
85 mJ / cm ² , 210 mJ / cm ² ) are the CV characteristics of the p-channel transistor, where the flat band voltage Vfb = 0.10 V to 0.11 V. Although not shown, the CV characteristics of a p-channel transistor formed by sputtering a gate electrode of silicon germanium and performing ELA (pulse energy density = 310 mJ / cm ² ) are almost the same, and the flat band voltage Vfb = 0.095V.

FIG. 3B shows a case where a gate electrode is formed of silicon germanium formed by sputtering.
C of p-channel transistor annealed at 40 ° C
V characteristics, and the flat band voltage Vfb = 0.66V. (C) shows a gate electrode formed of polysilicon formed by low pressure CVD and annealed at 940 ° C.
This is the CV characteristic of the channel transistor, and the flat band voltage Vfb is 1.32 V. (D) forms a gate electrode with polysilicon formed by low pressure CVD, and
CV of n-channel transistor annealed at 0 ° C
This is a characteristic, and the flat band voltage Vfb = −0.17 V.

As shown in FIG. 3, a p-channel transistor in which a gate electrode is formed of silicon germanium formed by sputtering in (a) and ELA is performed is a normal p-channel transistor as described in (c) above. The flat band voltage Vfb is lower than that of the polysilicon gate due to the lower band gap. Further, the flat band voltage Vfb is lower than that of a silicon germanium gate MOS capacitor manufactured by annealing at 940 ° C. for 30 minutes as described in (b). A CV characteristic close to that of an n-channel transistor formed at a temperature of 940 ° C. by forming a gate electrode with a simple polysilicon is shown because of the short-time annealing by ELA.
It can be said that the diffusion of boron was suppressed.

Next, the degree of penetration of boron under the annealing condition was examined. For the sample, 9
forming a gate insulating film with a silicon oxide film having a thickness of nm,
The gate electrode was formed on the gate electrode by sputtering with a p ⁺ silicon germanium film having a thickness of 80 nm and a polysilicon cap film having a thickness of 10 nm, and the annealing conditions were set as follows. The annealing condition of the sample was 940 ° C. for 30 minutes, the annealing condition of the sample was ELA (300 mJ / cm ² ), and the annealing condition of the sample was ELA (215 mJ / cm ² ).

As another sample, a gate insulating film was formed of a silicon oxide film having a thickness of 9 nm on a silicon substrate, and a gate electrode was formed thereon of p ⁺ silicon having a thickness of 90 nm by low pressure CVD. The annealing conditions were set as follows. The annealing condition of the sample was 940 ° C. for 30 minutes, and the sample was subjected to only ion implantation without annealing.

It should be noted that boron is ion-implanted in order to form ap ⁺ gate. The ion implantation conditions are as follows: implanted energy is 7 keV and dose is 4 × 10 ¹⁵
Pieces / cm ² .

FIGS. 4 to 6 show the concentration profiles of boron (left vertical axis) and the composition ratio profiles of germanium (left vertical axis) in the gate electrodes of the above samples. The density profiles are shown in FIGS. In each of the figures, the horizontal axis indicates the position,
Indicates the surface of the gate electrode, and indicates the depth direction as the position increases. Note that the germanium composition ratio x indicates x of silicon germanium (Si _1-x Ge _x ).

As shown in FIGS. 4 to 8, the concentration of boron is reduced as the and get closer to the gate insulating film.
This means that the concentration of boron in the gate electrode is almost uniform. As a result, the degree of penetration of boron was substantially the same as that of and, and was substantially the same, and the degree of penetration of the original was greater. Therefore, the impurity concentration profile after performing the ELA is almost the same as that immediately after the ion implantation, and the penetration of boron does not occur. On the other hand, 940 ° C, 3
It can be said that the 0 minute annealing causes the penetration of boron.

As described above, the concentration distribution of boron when ELA is performed is substantially the same as the concentration distribution of boron when only ion implantation is performed without annealing. It can be said that the diffusion of boron hardly occurred because no heat was applied.

Next, an embodiment of a second method for manufacturing a semiconductor device comprising an insulated gate field effect transistor according to the present invention will be described below. In this description, the same components as those described with reference to FIGS. 1 and 2 are denoted by the same reference numerals.

First, a gate electrode made of activated silicon or silicon germanium containing impurities and having a lower concentration of the impurities toward the gate insulating film of the insulated gate field effect transistor is formed.

In the step of forming the gate electrode, as described with reference to FIG. 2A, the substrate 1 having the element isolation region 3 for electrically isolating the MOS formation region serving as the active region. Is used. This substrate 1 is made of, for example, a silicon substrate. Then, a gate insulating film 11 is formed on the substrate 1 by a normal manufacturing method.

Next, a semiconductor film 21 made of a silicon film or a silicon germanium film is formed on the gate insulating film 11 by, for example, sputtering. Subsequently, the semiconductor film 21 is doped with impurities by an ion implantation method. Here, boron is ion-implanted. The ion implantation conditions are the same as those described with reference to FIG. Alternatively, the semiconductor film 21 can be formed of a silicon film or a silicon germanium film containing boron as an impurity by CVD or sputtering.

Thereafter, as described with reference to FIG. 2C, the semiconductor film 21 is irradiated with pulsed ultraviolet light to anneal the semiconductor film 21. As described with reference to FIG. 2, excimer laser light or all-solid-state laser light is used as the ultraviolet pulse light. The irradiation conditions are the same as described above.

Thereafter, the semiconductor film 21 is patterned on the gate electrode 12 as described with reference to FIG.

The thermal process in the subsequent process is performed at a temperature that hardly changes the concentration profile of the impurity boron doped in the semiconductor film 21. For example, in the case of annealing, 950 ° C. or less, 3
It should be about 0 minutes or less. Under such conditions, the impurity profile in the gate electrode 12 hardly moves.

In the second method of manufacturing a semiconductor device, since the impurity (boron) concentration on the gate insulating film 11 side in the gate electrode 12 is low, the possibility that boron penetrates the gate insulating film 11 is reduced, and the transistor Reliability is improved. In addition, the heat process after forming the gate electrode 12 is performed at a temperature applied in the heat process without changing the concentration profile of boron in the gate electrode 12, so that the boron penetrates the gate insulating film 11. The likelihood is further reduced and the reliability of the transistor is improved.

[0066]

As described above, according to the semiconductor device of the present invention, since the impurity concentration of the gate electrode on the gate insulating film side is reduced, the possibility that the impurity penetrates the gate insulating film is reduced. The reliability of the transistor can be improved.

According to the first manufacturing method of the present invention, the crystallization annealing of the semiconductor film is performed before the semiconductor film is patterned into the gate electrode. It is possible to uniformly crystallize the semiconductor film without receiving the same. for that reason,
Since the gate electrode can be formed using a semiconductor film on which uniform crystallization has been performed, transistor characteristics can be improved.

According to the second manufacturing method of the present invention, since the impurity concentration of the gate electrode on the gate insulating film side is low, the possibility that the impurity penetrates the gate insulating film is reduced, and the reliability of the transistor is improved. be able to. In addition, the thermal process after forming the gate electrode is performed at a temperature applied in the thermal process does not change the impurity concentration profile, so that the possibility that the impurity penetrates the gate insulating film is further reduced, and the transistor is reduced. Reliability can be improved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of an embodiment relating to a semiconductor device including an insulated gate field effect transistor of the present invention.

FIG. 2 is a manufacturing process diagram of an embodiment according to a first manufacturing method of the present invention.

FIG. 3 is a CV characteristic diagram of the insulated gate field effect transistor manufactured by the first manufacturing method of the present invention.

FIG. 4 is an explanatory diagram of a boron concentration profile and a germanium composition profile in a gate electrode of a sample.

FIG. 5 is an explanatory diagram of a boron concentration profile and a germanium composition profile in a gate electrode of a sample.

FIG. 6 is an explanatory diagram of a boron concentration profile and a germanium composition profile in a gate electrode of a sample.

FIG. 7 is an explanatory diagram of a boron concentration profile and a germanium composition profile in a gate electrode of a sample.

FIG. 8 is an explanatory diagram of a boron concentration profile and a germanium composition profile in a gate electrode of a sample.

FIG. 9 is an explanatory diagram of a conventional insulated gate field effect transistor.

FIG. 10 is a manufacturing process diagram of a conventional insulated gate field effect transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Insulated gate field effect transistor, 11 ... Gate insulating film, 12 ... Gate electrode

Claims (24)

[Claims] 1. A semiconductor device comprising an insulated gate field effect transistor, wherein a gate electrode of the insulated gate field effect transistor is made of silicon or silicon germanium containing an impurity, and the concentration of the impurity in the gate electrode is the same as that of the insulation. A semiconductor device characterized in that it becomes lower toward the gate insulating film side of the gate type field effect transistor. 2. The semiconductor device according to claim 1, wherein the gate insulating film is formed of a silicon oxide film, a silicon oxynitride film, or a stacked film of a silicon oxide film and a silicon oxynitride film. apparatus. 3. A method of manufacturing a semiconductor device comprising an insulated gate field effect transistor, comprising: using a substrate having an active region and an element isolation region;
Forming a gate insulating film on the active region, forming a semiconductor film made of silicon or silicon germanium and containing impurities on the gate insulating film, and irradiating the semiconductor film with pulsed ultraviolet light to activate the semiconductor film. A method for manufacturing a semiconductor device, comprising: a step of performing crystallization annealing for crystallization; and a step of forming a gate electrode by patterning the crystallized semiconductor film. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the gate insulating film is formed of a silicon oxide film, a silicon oxynitride film, or a stacked film of a silicon oxide film and a silicon oxynitride film. A method for manufacturing a semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the semiconductor film is formed by forming a non-doped silicon film or a non-doped silicon germanium film on the gate insulating film, and then forming the non-doped silicon film or A method for manufacturing a semiconductor device, comprising forming a non-doped silicon germanium film by doping impurities. 6. The method for manufacturing a semiconductor device according to claim 4, wherein the semiconductor film is formed by forming a non-doped silicon film or a non-doped silicon germanium film on the gate insulating film, and then forming the non-doped silicon film or A method for manufacturing a semiconductor device, comprising forming a non-doped silicon germanium film by doping impurities. 7. The method for manufacturing a semiconductor device according to claim 3, wherein the semiconductor film is formed by forming a silicon film containing impurities or a silicon germanium film containing impurities on the gate insulating film. A method for manufacturing a semiconductor device, comprising: 8. The method for manufacturing a semiconductor device according to claim 4, wherein the semiconductor film is formed by forming a silicon film containing impurities or a silicon germanium film containing impurities on the gate insulating film. A method for manufacturing a semiconductor device, comprising: 9. The method for manufacturing a semiconductor device according to claim 3, wherein the ultraviolet pulse light is excimer laser light or all solid-state laser light. 10. The method of manufacturing a semiconductor device according to claim 4, wherein said ultraviolet pulsed light is excimer laser light or all-solid-state laser light. 11. The method of manufacturing a semiconductor device according to claim 5, wherein the ultraviolet pulse light is excimer laser light or all solid-state laser light. 12. The method of manufacturing a semiconductor device according to claim 6, wherein the ultraviolet pulse light is excimer laser light or all solid-state laser light. 13. The method of manufacturing a semiconductor device according to claim 7, wherein said ultraviolet pulse light is excimer laser light or all-solid-state laser light. 14. The method of manufacturing a semiconductor device according to claim 8, wherein the ultraviolet pulse light is excimer laser light or all solid-state laser light. 15. A method for manufacturing a semiconductor device comprising an insulated gate field effect transistor, comprising: activated silicon or silicon germanium containing an impurity, wherein the concentration of the impurity is reduced by a gate insulating film of the insulated gate field effect transistor. A step of forming a gate electrode which becomes lower toward the side, wherein a heat step after the formation of the gate electrode is performed at a temperature which hardly changes the concentration profile of the impurity. Method. 16. The method for manufacturing a semiconductor device according to claim 15, wherein the gate insulating film is formed of a silicon oxide film, a silicon oxynitride film, or a stacked film of a silicon oxide film and a silicon oxynitride film. A method for manufacturing a semiconductor device. 17. The method for manufacturing a semiconductor device according to claim 15, wherein the step of forming the gate electrode uses a substrate having an active region and an element isolation region, and forms a gate insulating film on the active region. Forming a semiconductor film made of a silicon film or a silicon germanium film on the gate insulating film; doping the semiconductor film with an impurity; irradiating the semiconductor film with ultraviolet pulsed light; A method for manufacturing a semiconductor device, comprising: annealing a film; and patterning the semiconductor film into a gate electrode. 18. The method of manufacturing a semiconductor device according to claim 16, wherein the step of forming the gate electrode uses a substrate having an active region and an element isolation region.
Forming a gate insulating film on the active region, forming a semiconductor film made of a silicon film or a silicon germanium film on the gate insulating film; doping impurities into the semiconductor film; A method for manufacturing a semiconductor device, comprising: irradiating a pulsed ultraviolet light to anneal the semiconductor film; and patterning the semiconductor film into a gate electrode. 19. The method for manufacturing a semiconductor device according to claim 15, wherein the step of forming the gate electrode uses a substrate having an active region and an element isolation region.
Forming a gate insulating film on the active region, forming a semiconductor film made of a silicon film or a silicon germanium film on the gate insulating film while containing impurities, and irradiating the semiconductor film with pulsed ultraviolet light And annealing the semiconductor film, and patterning the semiconductor film into a gate electrode. 20. The method of manufacturing a semiconductor device according to claim 16, wherein the step of forming the gate electrode uses a substrate having an active region and an element isolation region.
Forming a gate insulating film on the active region, forming a semiconductor film made of a silicon film or a silicon germanium film on the gate insulating film while containing impurities, and irradiating the semiconductor film with pulsed ultraviolet light And annealing the semiconductor film, and patterning the semiconductor film into a gate electrode. 21. The method of manufacturing a semiconductor device according to claim 17, wherein the ultraviolet pulse light is excimer laser light or all-solid-state laser light. 22. The method of manufacturing a semiconductor device according to claim 18, wherein the ultraviolet pulse light is excimer laser light or all-solid-state laser light. 23. The method of manufacturing a semiconductor device according to claim 19, wherein the ultraviolet pulse light is excimer laser light or all solid-state laser light. 24. The method of manufacturing a semiconductor device according to claim 20, wherein the ultraviolet pulse light is excimer laser light or all solid-state laser light.