JPH11330432A - Semiconductor memory device, its writing method, and storage medium with the writing method stored therein - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain the gradation of memory cells due to overcurrent and enhance the reliability through method, wherein a current value flowing in at least one of a drain and a control gate electrode is controlled by a current control means. SOLUTION: A current value selected from four finds of current values I1 to I4 is applied on memory cells, whereby data are written to the memory cells. That is, a current value selected from the current value of the four kinds, of the current values I1 to I4 in response to a data signal from an external unit flows in the drain of the memory cells, and electric charges accumulated in a floating gate pass through a tunnel oxide film to be extracted. The current values I1 to I4 which are controlled by a constant current asymptotically reach specified currents I1 ' to I4 ', respectively, when a specified period of time elapses. A time t0 designates a specified write time. At the time point when the time t0 has elapsed after one of the currents I1 to I4 flowed into the memory cells, a current is stopped and with this write operations is ended.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device capable of storing data, and more particularly to a multivalued semiconductor memory device capable of storing three or more storage states, and a method for writing the same and a method for writing the same. It relates to a storage medium that has been set.

[0002]

2. Description of the Related Art In a semiconductor memory device which has been put into practical use at present, only two kinds of storage states, "0" and "1", are given to one memory cell. Therefore, the storage capacity of one memory cell is limited. 1 bit (= binary), whereas one memory cell (“00”, “01”, “10”, “1”)
1 "), and four threshold voltages corresponding to each of the stored information, for example, (1V, 2V, 3
V, 4V), that is, a semiconductor memory device in which one memory cell has a storage capacity of 2 bits (= 4 values) has been proposed.

An example of the above-described multi-valued semiconductor memory device is described in, for example, Japanese Patent Application Laid-Open No. H6-195987.

Japanese Patent Application Laid-Open No. H6-195987 discloses that when providing the above-mentioned four types of storage information, the stored information is made to correspond to four types of voltage values and any one of the four types of voltage values is provided. Is applied to a memory cell for writing data.

There is also described a method in which the stored information is made to correspond to four kinds of signals having different time widths, and any one of these signals is applied to a memory cell for writing data.

[0006]

However, according to the method described in Japanese Patent Application Laid-Open No. H6-195987, when the storage state to be written in one memory cell is varied by different voltage values, particularly when the voltage is initially applied, In the state, this voltage is directly applied to the memory cell.

[0007] When a constant voltage is applied to the memory cell, a current corresponding to the voltage value flows directly to the memory cell. Here, the drain of the memory cell and the control gate
Electrons are injected into the floating gate from the drain through the tunnel oxide film due to the potential difference between the drain and the gate. However, when an overcurrent flows through the drain, the tunnel oxide film is damaged by high-energy electrons. Become.

As a result, the threshold value of the memory cell fluctuates, making it difficult to maintain a predetermined storage state, or when the damage of the tunnel oxide film is large, the memory cell itself is destroyed. There was a fear.

The present invention has been made to solve such a problem. In a multi-level semiconductor memory device capable of storing three or more storage states, deterioration of a memory cell due to overcurrent is prevented. It is an object of the present invention to provide a semiconductor memory device which is suppressed and has improved reliability.

[0010]

A semiconductor memory device according to the present invention is a memory having at least a charge storage layer, a control gate electrode formed on the charge storage layer via an insulating film, and a source / drain. A cell; and write control means for writing multi-valued data corresponding to one threshold value selected from at least three different threshold values to the memory cell, wherein the write control means comprises at least three threshold values. There is a current control means for controlling different kinds of current values, and the current control means controls a current value flowing at least to one of the drain or the control gate electrode.

In one embodiment of the semiconductor memory device of the present invention, the current control means is a control means for keeping the current value at a predetermined constant value.

In one embodiment of the semiconductor memory device according to the present invention, the threshold value is set large according to the magnitude of the current value controlled by the current control means.

A writing method of a semiconductor memory device according to the present invention is directed to a memory cell having at least a charge storage layer, a control gate electrode formed on the charge storage layer via an insulating film, and a source / drain. A method of selectively writing one of at least three different types of data, comprising: a first step of selecting one current value from among at least three predetermined current values; Flowing the selected current value to one of a drain and the control gate electrode.

In one embodiment of the writing method of the semiconductor memory device according to the present invention, the current values controlled to the at least three predetermined values are determined based on different levels of threshold voltages of the memory cells.

In the storage medium of the present invention, the first and second steps constituting the writing method of the semiconductor storage device are stored so as to be readable by a computer.

A semiconductor device according to the present invention includes a first insulating layer formed on a semiconductor substrate, a gate electrode formed on the first insulating layer, and one of the semiconductor substrates on one side of the gate electrode. A first conductive region formed thereon, a second conductive region formed on the other semiconductor substrate on one side of the gate electrode, and a current generating circuit capable of changing a current value in multiple stages; and And current control means for controlling a value of a current flowing through one of the first and second conductive regions by the current generating circuit.

In one embodiment of the semiconductor device of the present invention, a lower electrode connected to one of the first and second conductive regions and a dielectric layer formed on the lower electrode are provided. And an upper electrode formed on the dielectric layer, wherein the lower electrode, the dielectric layer, and the upper electrode function as a capacitor.

In one embodiment of the semiconductor device according to the present invention, the first conductive region functions as a source, and the second conductive region functions as a drain. Current control means for controlling a value of a flowing current, wherein the gate electrode functions as a charge storage layer, and a control gate electrode formed on the charge storage layer via a second insulating layer; Charge accumulation means for introducing charges into the layer.

In one embodiment of the semiconductor device of the present invention, the semiconductor device is a multi-level semiconductor memory device capable of storing three or more storage states.

In one embodiment of the semiconductor device according to the present invention, the charge accumulating means includes a charge amount adjusting means for changing the charge amount in multiple stages, and at least three different thresholds by the charge amount adjusting means. Charge introducing means for introducing data corresponding to one threshold value selected from the above into the charge storage layer as a charge amount.

In one embodiment of the semiconductor device of the present invention, the current control means has a variable resistance means having a function of changing a resistance value.

In one embodiment of the semiconductor device of the present invention,
The current generating circuit includes means for varying a current value based on a predetermined data value.

[0023]

According to the present invention, at least three kinds of current values controlled to predetermined values by the current control means are generated, and one current value selected from these current values is applied to the memory cell. Since the upper limit of each current value applied to the memory cell is reliably controlled to a current value that the memory cell can withstand, it is possible to perform a write operation without applying an overcurrent to the memory cell. . In addition, in the present invention, these controlled current values are set to at least 3
By preparing the types, it is possible to store the multi-valued information in one memory cell so that the current value corresponds to each of the threshold values of the multi-valued memory cell.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a part of a memory cell array of an EEPROM which is a nonvolatile semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a block diagram showing a main configuration of the EEPROM of this embodiment. FIG. 3 shows the E formed on a silicon semiconductor substrate.
FIG. 2 is a schematic sectional view showing one memory cell of an EPROM.

In FIG. 1, each of the memory cells 10 to 13 has a floating gate 106. A word line 20 is connected to the control gates of the memory cells 10 and 11, respectively.
A word line 21 is connected to the control gates of the memory cells 12 and 13, respectively.

However, in practice, each word line and each control gate are integrally formed of, for example, polysilicon, and the word line itself is provided in the region of each memory cell. Is configured.

On the other hand, a bit line 22 is connected to the drains of the memory cells 10 and 12, and a bit line 23 is connected to the drains of the memory cells 11 and 13, respectively. Further, the sources of the memory cells 10 to 13 are connected to a common source line 109.

FIG. 2 shows a main configuration of the EEPROM of the present embodiment.

Word lines 20 and 21 connected to the control gates of the memory cells 10 to 13 are connected to the column decoder 2, while bits connected to the drains of the memory cells 10 to 13 are provided. Lines 22 and 23 are connected to a row decoder 3 via a row selector 4.

An address signal input via the address buffer 5 is sent to the decoders 2 and 3, and the decoders 2 and 3 select word lines and bit lines, respectively. Will be

As shown in FIG. 3, each of the memory cells 10 to 13 has phosphorus (P) on a surface region of an element active region 102 defined by an element isolation structure such as a field oxide film on a p-type silicon semiconductor substrate 101. P) and arsenic (As)
A source 103 and a drain 104, which are a pair of impurity diffusion layers formed by ion implantation of n-type impurities such as
Channel region C between source 103 and drain 104
Each of the island-shaped floating gates 106, each of which has a pattern formed thereon via a tunnel oxide film 105, and a floating gate 1
And a control gate 108 which is patterned and formed with a floating gate 106 through a dielectric film 107 made of an ONO film or the like and which is capacitively coupled to the floating gate 106.

In FIG. 2, the voltage from the write voltage generating circuit 6 is applied to the memory cells selected by the row decoder 3 via the current control circuit 8 to each of the memory cells 10-1.
3 is applied to the drain 104 or the control gate 108. Here, the current flowing into the drain 104 or the control gate 108 is controlled by the current control circuit 8, and the upper limit value is determined.

FIG. 4 is a characteristic diagram schematically showing each current value controlled by the current control circuit 8. As shown in FIG. In FIG. 4, the vertical axis indicates the current value, and the horizontal axis indicates time. The current control circuit 8 can control the voltage from the write voltage generation circuit 6 to set four types of current values. In FIG. 4, I ₁ , I ₂ , I ₃ , and I ₄ indicate the set current values. Further, a curve shown by a dotted line shows a change in current when a voltage from the write voltage control circuit 6 is directly applied to the drain 104 of the memory cell without passing through the current control circuit 8.

The one selected from these four types of current values
By applying one current value to the selected memory cell, data is written to the memory cell. That is,
A current value selected from the four types of current values flows to the drain 104 of the memory cell in response to an external data signal, and the charges stored in the floating gate 106 pass through the tunnel oxide film 105. Pulled out.

Each current value I ₁ controlled to a constant current
~I ₄ is asymptotically to a predetermined time elapses as shown in FIG. 4 reaches a predetermined current I ₁ '~I _4'. T ₀ shown in FIG.
Indicates a predetermined writing time. I _{1 in the} memory cell
When the time t ₀ from flowing any current of ~I ₄ has elapsed, to stop the current. Thus, the write operation ends.

In FIG. 4, the curves from the current values I _{1 to} I ₄ to the current values I ₁ ′ to I ₄ ′ are different from each other in FIG.
As shown in FIG. 3, a band corresponding to each current value is provided between the drain 104 of the memory cell and the substrate potential (V ₀ ).
Band tunneling current I ₀ is because the flow.

The band-to-band tunnel current I ₀ decreases as the writing of the memory cell proceeds and the potential of the floating gate 106 rises with respect to the silicon semiconductor substrate 101. Therefore, the speed is different when the band of the write different supply current - decrease in interband tunneling current I ₀ is different from.

As described above, the EEPRO according to the present embodiment
M corresponds to each of four threshold values (1 V, 2 V, 3 V, 4 V) as shown in FIG. 5 by flowing one current value selected from the constant currents I _{1 to} I ₄ to the memory cell. The stored information can be stored. The magnitude of each threshold value corresponds to each of the current values I _{1 to} I ₄ , and as the current value increases, the amount of charge extracted from the floating gate 106 increases, so that the threshold value of the memory cell decreases. Will be set.

FIG. 6 shows a specific configuration of the current control circuit 8 shown in FIG. The current control circuit 8 includes four types of load transistors (Tr1) having different thresholds as shown in FIG.
To Tr4), electric resistances (R1 to R4) having four different resistance values as shown in FIG. 6B, or capacitors (C1 to C4) as shown in FIG. 6C, and electric resistances (r1 to r).
4) and a load means 8b composed of a diode.

According to the present invention, as shown in FIG.
Transistor Tr1 having a threshold (corresponding to I ₁₎
When the first transistor Tr2 having a different second threshold value the threshold (corresponding to the I _2), first, with different third threshold and the second threshold Transistor T
r3 (corresponding to I ₃ ), a transistor Tr 4 (I ₃ ) having a fourth threshold value different from the first, second, and third threshold values.
(Corresponding to ₄ ), but a multi-valued non-volatile memory in which at least three different thresholds can be set may be used instead.

This multi-level nonvolatile memory cell has the configuration shown in FIG. 3 and has a certain threshold value depending on the amount of charge introduced into the floating gate electrode. In this memory, the threshold is set as it is, unless it is electrically erased. If it is desired to set (change) a new threshold value, the charge introduced into the floating gate is electrically erased, then the amount of charge in the floating gate is changed, and the threshold value is set again. Is possible. That is,
This memory can be set to a plurality of threshold values by changing the amount of charge of the floating gate electrode in multiple stages.

As described above, the load means 8b has four stages of loads for setting the four types of current values I ₁ , I ₂ , I ₃ , and I _4, and these loads are set by the selection means 8a. It is possible to select one of them.

Next, a method of using the EEPROM of this embodiment will be described. First, a writing method using the EEPROM will be described. At the time of writing, after one of the memory cells 10 to 13 is selected by the column decoder 2 and the row decoder 3 according to the address signal from the address buffer 5, the binary data string from the input / output circuit 9 is used as storage information. The write operation of the selected memory cell is performed as shown in FIG.

First, when writing the storage information "11",
By applying a predetermined voltage to the control gate 108 of the memory cell,
The source 103 is opened, and the drain 104 is set to the ground potential. At this time, the current flowing through the drain 104 is changed as shown in FIG.
~ Passed through one of the four levels of load means 8b in (c), as shown in FIG. 4, for controlling a current flowing through the drain 104 to the constant current I _4. At this time, electrons are sufficiently injected from the drain 104 to the floating gate 106, and the threshold voltage of the memory cell becomes about 4V. This storage state is set to “11”.

Next, when writing the storage information "10",
The control gate 108 of the memory cell is set to the ground potential, the source 103 is opened, and the drain 1
04 is applied with a predetermined voltage. At this time, the current flowing through the drain 104 is passed through one of the four-stage load means 8b shown in FIGS. 6A to 6C, and the current flowing through the drain 104 is made constant as shown in FIG. controlling the current I _1.

At this time, electrons are extracted from the floating gate 106 through the tunnel oxide film 105, and the threshold voltage (V _T ) shifts. Then, the threshold voltage of the memory cell becomes about 3V. This storage state is set to “10”.

Next, when writing the storage information "01",
The control gate 108 of the memory cell is set to the ground potential, the source 103 is opened, and a predetermined voltage is applied to the drain 108. At this time, the current flowing through the drain 104 is changed as shown in FIG.
~ Passed through one of the four levels of load means 8b in (c), as shown in FIG. 4, for controlling a current flowing through the drain 104 to the constant current I _2. At this time, electrons are extracted from the floating gate 106 through the tunnel oxide film 105, and the threshold voltage of the memory cell becomes about 2V. This storage state is set to “01”.

Next, when writing the storage information "00",
The control gate 108 of the memory cell is set to the ground potential, the source 103 is opened, and a predetermined voltage is applied to the drain 104. At this time, the current flowing through the drain 104 is changed as shown in FIG.
~ Passed through one of the four levels of load means 8b in (c), as shown in FIG. 4, for controlling a current flowing through the drain 104 to the constant current I _3. At this time, electrons are extracted from the floating gate 106 through the tunnel oxide film 105, and the threshold voltage of the memory cell becomes about 1V. This storage state is set to “00”.

Therefore, in this EEPROM writing method, by recognizing the threshold value and selecting one of the constant currents I _{1 to} I ₄ , "00", "01", "10", "
It is possible to write arbitrary data of 11 ″. Alternatively, writing may be performed by applying the respective constant currents I _{1 to} I ₄ to the control gate 108 with the drain 104 as the ground potential. In this case, the current value I
Since the amount of charge stored in the floating gate 106 in accordance with the size of ₁ ~I ₄ increases, the threshold current value I ₁ ~I
Increases with ₄ .

Next, a reading method using the EEPROM will be described. At the time of reading, one of the memory cells 10 to 13 by the column decoder 2 and the row decoder 3 according to the address signal from the address buffer 5,
For example, after selecting the memory cell 11, the read operation of the memory cell 11 is performed as described below. FIG. 7 is a flowchart showing each step of the read operation.

As shown in FIG. 5, the storage information read from the selected memory cell 11 has four peaks (quaternary values) having a threshold voltage (V _T ) of about 1 V, about 2 V, about 3 V, and about 4 V. ) Is shown. In FIG. 5, when the threshold voltage _VT is detected in the range indicated by R1, the storage state is "00", and when the threshold voltage _VT is detected in the range indicated by R2. Has a storage state of “01”. When the threshold voltage _VT is detected in the range indicated by R3, the storage state is changed to "1".
0 ", and the threshold voltage V _T falls within the range indicated by R4.
Is detected, the storage state is "11".

Therefore, first, the storage state is "R1 or R1".
2 ”or“ R3 or R4 ”, that is, the upper bit of the storage information stored in the memory cell 11 is“ 0 ”.
The determination is made using the transistor Tr1. In this case, as shown in FIG. 7, the order of 5V is applied to the source 3 and drain 4 and a gate electrode 6 (step S1), the detecting the drain current in the sense amplifier 21, the threshold voltage V _T and the transistor Tr1 The magnitude relationship with the threshold voltage is determined (step S2). At this time, if the threshold voltage V _T is larger than the threshold voltage of the transistor Tr1, that is, if more current flowing through the channel region C of the memory cell current of the transistor Tr1 is large upper bit is "1" and it is determined, if the threshold voltage V _T is smaller than the threshold voltage of the transistor Tr1, that is, if when the current flowing through the memory cell 11 than the current flowing through the transistor Tr1 is larger upper bit is "0" It is determined and output from the output terminal D1 as the upper bit of the storage information prior to the lower bit (step S3, step S4).

[0053] Then, if the threshold voltage V _T is larger than the threshold voltage of the transistor Tr1, the transistor Tr2 with the same read operation, the memory cell 11
Comparing the current flowing through the current and the transistor Tr2 flows to (step S5), and if the threshold voltage V _T is smaller than the threshold voltage of the transistor Tr1 determines similar read operation using the transistor Tr3 (Step S6).

In step S5, the threshold voltage V _T
There greater than the threshold voltage of the transistors Tr1, the threshold voltage V _T is the transistor Tr in the aforementioned read operation
2, the memory cell 11
Is determined to be "1", and is output from the output terminal D0 (step S5).
7). Therefore, in this case, the storage information read from the memory cell 11 is “11”.

On the other hand, in step S5, if the threshold voltage V _T is smaller than the threshold voltage of the transistor Tr2 is stored information stored in the memory cell 11 is "1
It is determined to be "0" and output from the output terminal D0 (step S8) .Therefore, in this case, the storage information read from the memory cell 11 is "10".

[0056] Further, in step S6, if the threshold voltage V _T is smaller than the threshold voltage of the transistor Tr1, that is, when the current of the memory cell 11 is greater than the current of the transistor Tr1, then transistor Tr3
If the threshold voltage of the memory cell 11 is higher than the threshold voltage of the memory cell 11, the lower bit is determined to be "1" and is output from the output terminal D0 as the lower bit of the storage information (step S9). Therefore, in this case, the storage information read from the memory cell 11 is “01”.

Meanwhile, when the threshold voltage V _T in the above reading operation is smaller than the threshold voltage of the transistor Tr1, i.e. the memory cell 1 than the current of the transistor Tr1
If the current of 1 is large, it is compared with the threshold voltage of the transistor Tr3. If the threshold voltage of the memory cell is small, the lower bit is determined to be "0" and output as the lower bit of the storage information. The signal is output from the terminal D0 (step S10). Therefore, in this case, the storage information read from the memory cell 11 is “00”.

In the present embodiment, the case where the storage information is quaternary (two bits) has been described, but the present invention is not limited to this. For example, if the storage state is 3
In the case of bits (8 values), eight threshold voltages are stored in the storage states “000”, “001”, “010”, “01”.
1 "," 100 "," 101 "," 110 "," 11
1 ", and one of the eight storage states may be specified by a predetermined determination operation at the time of reading. Further, the storage information is not binary data, but may be 0, 1, or the like.
2, the storage state is “0”,
1 ”,“ 2 ”,“ 00 ”,“ 01 ”,“ 0 ”
2 "," 10 "," 11 "," 12 "," 20 "," 2
It is also possible to use 1 "and" 22 ". In such a case, the former will express the storage state as ternary, and the latter as ninth.

As described above, in the present embodiment, four types of current values I _{1 to} I ₄ controlled to a predetermined value by the current control circuit 8 are generated, and _one current value selected from these current values is generated. The value is applied to one of the memory cells 10-13. Since the upper limit of each current value applied to the memory cells 10 to 13 is reliably controlled to a current value that the memory cells 10 to 13 can withstand,
It is possible to perform a write operation without applying an overcurrent to the memory cell.

Further, in the present embodiment, by preparing at least three types of these controlled current values, the threshold value of a multi-level memory cell capable of storing binary (= 1 bit) or more data is set. It is possible to store multi-value information in one memory cell by associating the current values with each other.

Further, the present invention is not limited to an EEPROM, but includes, for example, a memory capacitor for storing signal charges and an access transistor for selecting the memory capacitor. The present invention is also applicable to a multi-valued DRAM which is a volatile memory that sets a charge accumulation state by applying a predetermined reference voltage and stores storage information corresponding to the reference voltage.

For example, in the case of a multi-level DRAM, the configuration is as shown in FIG. By selectively forming a field oxide film 202 (element isolation insulating structure) on the surface of the p-type silicon substrate 201, a plurality of transistor formation regions are partitioned in a predetermined region where a memory cell array is formed. .

A gate oxide film 203 formed on the surface of the p-type silicon substrate 201 in the transistor formation region, a word electrode 204 traversing the transistor formation region, and a pair of n ⁺ type diffusion layers (source / source) on both sides of the word electrode 204 (Drain) 205. Also, the p-type silicon substrate 20
1 and a first contact hole above one of the n ⁺ -type diffusion layers 205 on both sides of the first word electrode 204 formed on the first interlayer insulating film 206. C1, the stacked polysilicon film 207 (first conductive film) formed in and near the first contact hole, the capacitor insulating film 208 formed on the stacked polysilicon film 207, and the capacitor. A polysilicon film 209 (a counter electrode) is formed. Further, the second interlayer insulating film 21 formed on the p-type silicon substrate 201
0, a third interlayer insulating film 211 (BPSG film), and second contact holes (bit line contact holes) formed in the first, second, and third interlayer insulating films 206, 210, 211.
C2 and a bit line 212 such as tungsten silicide formed in the contact hole C2. Further, this multi-level conversion is applicable not only to EEPROMs and DRAMs but also to various other semiconductor memories.

Further, the program code itself for operating various devices and the program code are supplied to a computer so as to realize the functions of the writing method, the reading method, and especially the storage / erasing method described in the present embodiment. For example, a storage medium 31 storing such program code shown in FIG. 2 belongs to the category of the present invention.

The program code stored in the storage medium 31 is read out by the storage / reproduction device 32 to operate the computer. As a storage medium for storing such a program code, for example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, magnetic tape, nonvolatile memory card, ROM, or the like can be used.

When the computer executes the supplied program code, not only the functions of the above-described embodiment are realized, but also the OS (operating system) or other operating system running on the computer. Such a program code is also included in the present invention when the functions of the above-described embodiments are realized in cooperation with application software or the like.

Further, after the supplied program code is stored in the memory provided on the function expansion board of the computer or the function expansion unit connected to the computer, the function expansion board or the function expansion unit is specified based on the instruction of the program code. The present invention also includes a system in which a CPU or the like provided in the system performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

[0068]

According to the present invention, in a multi-valued semiconductor memory device capable of storing three or more storage states, deterioration of a memory cell due to an overcurrent can be suppressed. Therefore, it is possible to provide a multi-level semiconductor memory device with improved reliability.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a part of a memory cell array of an EEPROM according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a main configuration of an EEPROM according to one embodiment of the present invention.

FIG. 3 is a schematic sectional view showing a memory cell of an EEPROM according to one embodiment of the present invention.

FIG. 4 is a characteristic diagram showing a current value flowing through a memory cell of the EEPROM according to the embodiment of the present invention.

FIG. 5 is a characteristic diagram showing a distribution of threshold voltages in an EEPROM according to an embodiment of the present invention.

FIG. 6 is a schematic diagram showing a current control circuit of the EEPROM according to one embodiment of the present invention.

FIG. 7 shows an example of an EEPROM 4 according to an embodiment of the present invention.
Flow chart showing each step when reading stored information of value
It is a chart.

FIG. 8 shows a multi-valued DRA according to a modification of the embodiment of the present invention.
It is a schematic sectional drawing which shows M.

[Explanation of symbols]

 2 column decoder 3 row decoder 4 row selector 5 address buffer 6 write voltage generation circuit 8 current control circuit 8a selection means 8b load means 9 input / output circuit 10, 11, 12, 13 memory cell 20, 21, word line 22, 23 bit line DESCRIPTION OF SYMBOLS 31 Storage medium 32 Storage / reproducing apparatus 101 Silicon semiconductor substrate 102 Element active region 103 Source 104 Drain 105 Tunnel oxide film 106 Floating gate 107 Dielectric film 108 Control gate 109 Source line

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/788 29/792

Claims (13)

[Claims] A memory cell including at least a charge storage layer, a control gate electrode formed on the charge storage layer via an insulating film, and a source / drain; Write control means for writing multi-valued data corresponding to one selected threshold value into the memory cell, wherein the write control means includes a current control means for controlling at least three different current values. And a current control means for controlling a value of a current flowing through at least one of the drain and the control gate electrode by the current control means. 2. The semiconductor memory device according to claim 1, wherein said current control means is a control means for keeping said current value at a predetermined constant value. 3. The semiconductor memory device according to claim 1, wherein said threshold value is set large according to the magnitude of said current value controlled by said current control means. 4. A memory cell comprising at least a charge storage layer, a control gate electrode formed on the charge storage layer via an insulating film, and a source / drain, wherein at least three
A method for selectively writing one of different kinds of data, comprising: a first step of selecting one current value from a current value controlled to at least three predetermined values; and at least the drain or the drain of the memory cell. A second step of passing the selected current value to one of the control gate electrodes. 5. The semiconductor memory device according to claim 4, wherein said current values controlled to said at least three predetermined values are determined based on different levels of threshold voltages of said memory cells. Method. 6. A recording medium, wherein the first and second steps constituting the writing method for a semiconductor memory device according to claim 4 or 5 are stored so as to be readable from a computer. 7. A first insulating layer formed on a semiconductor substrate; a gate electrode formed on the first insulating layer; and a gate electrode formed on one of the semiconductor substrates on one side of the gate electrode. A first conductive region; a second conductive region formed on the other semiconductor substrate on one side of the gate electrode; a current generating circuit capable of changing a current value in multiple stages; and the current generating circuit. A current control means for controlling a value of a current flowing through one of the first and second conductive regions. 8. A lower electrode connected to one of the first and second conductive regions, a dielectric layer formed on the lower electrode, and a lower layer formed on the dielectric layer. The semiconductor device according to claim 7, further comprising an upper electrode, wherein the lower electrode, the dielectric layer, and the upper electrode function as a capacitor. 9. The first conductive region functions as a source, the second conductive region functions as a drain,
The current control means is a current control means for controlling a current value flowing through the drain, wherein the gate electrode functions as a charge storage layer, and is formed on the charge storage layer via a second insulating layer. 8. The semiconductor device according to claim 7, further comprising: a control gate electrode; and charge storage means for introducing a charge into the charge storage layer. 10. The semiconductor device according to claim 8, wherein the semiconductor device is a multi-level semiconductor memory device capable of storing three or more storage states. 11. The charge accumulating means includes: a charge amount adjusting means for varying a charge amount in multiple stages; and the charge amount adjusting means changing the charge amount to one threshold value selected from at least three different threshold values. 10. The semiconductor device according to claim 9, further comprising: charge introducing means for introducing corresponding data into the charge storage layer as a charge amount. 12. The semiconductor device according to claim 7, wherein said current control means has a variable resistance means having a function of changing a resistance value. 13. The semiconductor device according to claim 7, wherein said current generating circuit includes means for varying a current value based on a predetermined data value.