JPH11313054A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL(phase-locked loop) circuit capable of the phase lock processing of a pilot signal in simple circuit configuration without preparing plural crystal oscillators corresponding to the frequencies of various pilot signals. SOLUTION: At a frequency converting part 30, a CPU 31 fetches pilot frequency information provided separately from the pilot signal extracted by a multiplier 12 and by confirming the contents of this pilot frequency information through the CPU 31, it is judged whether the frequency of the pilot signal is changed or not. Based on the prescribed frequency information including this judged result, differential data are generated for converting the frequency of the pilot signal extracted by the multiplier 12 to the frequency of a reference signal V2 generated by a crystal oscillator 21 and these differential data are converted to a reference signal V3 by a DDS 32 and a D/A converter 33 and multiplied by the pilot signal by a multiplier 34 later.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Locked Loop) circuit for phase-locking a received pilot signal in a system such as satellite broadcasting and satellite communication.

[0002]

2. Description of the Related Art As is well known, in a system such as satellite broadcasting and satellite communication, a PLL circuit for phase-locking a received pilot signal is configured as shown in FIG. In this system, for example, in order to use a satellite line, an individually assigned pilot signal is required.

In FIG. 2, an incoming signal from a satellite supplied to an input terminal 11 is multiplied by an oscillation signal output from a VCXO (Voltage Controlled Oscillator) 13 by a multiplier 12 to produce an arbitrary pilot signal. Converted, distributor 1
4 and is taken out from the output terminal 15.

On the other hand, the pilot signal is supplied to a distributor 14
Is supplied to one input terminal of the frequency converter 16.
The frequency converter 16 has a crystal oscillator 1 connected to the other input terminal.
7 is supplied with a reference signal V1 having a constant frequency, and is converted into a frequency specified for reception processing by multiplying the input pilot signal by the reference signal V1. The output of the frequency converter 16 passes through a BPF (Band Pass Filter) 18 to extract a signal of a main frequency band component.
After the phase is shifted by 0 °, it is supplied to one input terminal of the phase comparator 20. The other input terminal of the phase comparator 20 is supplied with a reference signal V2 of a constant frequency generated from the crystal oscillator 21.

[0005] The frequency of the reference signal V 2 generated from the crystal oscillator 21 is the same as the frequency of the output of the 90 ° phase shifter 19. That is, the frequency converter 16
Means that the pilot signal is converted into a signal having the same frequency as the reference signal V2 generated from the crystal oscillator 21.

The phase comparator 20 generates a difference signal having a frequency corresponding to the phase difference component between the output of the 90 ° phase shifter 19 and the reference signal V 2, and outputs the difference signal to the loop filter 22. The loop filter 22 converts the input difference signal into a DC voltage level, and outputs the DC voltage level to the VCXO 13 as a control voltage. For this reason, the VCXO 13 is controlled such that the frequency of the oscillation signal has no phase difference with the arrival signal from the satellite.

By the way, in the above-mentioned PLL circuit, a crystal oscillator is used as an oscillator in order to improve frequency accuracy. Therefore, if this crystal oscillator is used, a highly accurate and stable frequency can be extracted.However, when the frequency of the pilot signal is changed, or when used for a system with a different frequency of the pilot signal, the oscillation is performed at a different frequency. It is necessary to prepare a plurality of crystal oscillators, and to switch or exchange the plurality of crystal oscillators each time according to the frequency of the pilot signal. This gives the user the trouble of switching or exchanging a plurality of crystal oscillators in accordance with various pilot signals, and the provision of a plurality of crystal oscillators in accordance with the frequency of the pilot signal provides a circuit. Has become complicated and expensive.

[0008]

As described above, in the conventional PLL circuit, a plurality of crystal oscillators corresponding to the frequency of the pilot signal must be prepared when the PLL circuit is used in a system having a different frequency of the pilot signal. For this reason, there is a problem that the circuit becomes complicated and the price is increased. Further, it is necessary to switch or exchange a plurality of crystal oscillators in accordance with the frequency of the pilot signal, which causes a problem that the user is required to perform unnecessary work.

An object of the present invention is to eliminate the need for preparing a plurality of crystal oscillators in accordance with the frequencies of different pilot signals even when used in a system having different pilot signal frequencies, and to provide a pilot circuit with a simple circuit configuration. An object of the present invention is to provide a PLL circuit capable of realizing a signal phase lock process.

[0010]

According to the present invention, there is provided a signal extracting means for extracting an arbitrary pilot signal from an incoming radio wave from a satellite, and multiplying the pilot signal extracted by the signal extracting means with a local oscillation signal. Frequency conversion means for converting the frequency of the pilot signal to a frequency specified for reception processing, fixed oscillation means for generating a fixed oscillation signal having the same frequency as the frequency obtained by the frequency conversion means, and fixed oscillation means A fixed oscillation signal output from
Phase comparing means for comparing the phase of the output of the frequency converting means with a signal whose phase is shifted by 90 °; and a difference signal obtained by the phase comparing means for controlling a phase difference between a pilot signal extracted from the signal extracting means. The present invention is directed to a PLL circuit including a signal extraction control unit that converts the signal into an oscillation frequency signal and provides the signal to a signal extraction unit.

In order to achieve the above object, the frequency conversion means sets the frequency of the pilot signal to the same as the frequency of the fixed oscillation signal generated from the fixed oscillation means based on the separately provided pilot frequency information. Frequency conversion control means for generating such a local oscillation signal, and multiplication for converting the frequency of the pilot signal to the frequency of the fixed oscillation signal by multiplying the local oscillation signal generated by the frequency conversion control means and the pilot signal. Means.

According to this configuration, at the stage of converting the pilot signal to the frequency specified for the reception processing,
By taking in pilot frequency information provided separately from the pilot signal and confirming the contents of the pilot frequency information, it is determined whether or not the frequency of the pilot signal transmitted from the satellite has been changed. Based on the predetermined information including the result, a local oscillation signal for converting the frequency of the pilot signal to the frequency of the fixed oscillation signal used in the subsequent phase comparison processing is generated. Then, by multiplying the pilot signal by the local oscillation signal, the frequency of the pilot signal is converted to the frequency of the fixed oscillation signal used in the phase comparison processing.

As a result, there is no need to prepare a plurality of crystal oscillators in accordance with the change in the frequency of the pilot signal, and it is not necessary to switch or exchange a plurality of crystal oscillators in accordance with the change in the frequency of the pilot signal. It is possible to execute the phase lock processing corresponding to a system with different pilot signals without incurring a complicated configuration of the circuit or increasing the price.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows an embodiment of the present invention. In FIG. 1, the same parts as those in FIG.

Here, the configuration and operation of the entire PLL shown in FIG. 1 will be described. An incoming signal from a satellite supplied to an input terminal 11 is multiplied by an oscillation signal output from a VCXO 13 by a multiplier 12. The signal is converted into an arbitrary pilot signal, and is extracted from the output terminal 15 via the distributor 14. Further, the pilot signal is supplied to the frequency conversion unit 30 by the distributor 14 and is multiplied by the reference signal in the frequency conversion unit 30 to be converted into a frequency specified for reception processing. The output of the frequency conversion unit 30 is BP
After passing through F18, for example, a signal of a main frequency band component from which a television signal component has been removed is extracted, and the 90 ° phase shifter 19 shifts the phase by 90 °. Supplied to The other input terminal of the phase comparator 20 is supplied with a reference signal V2 of a constant frequency generated from the crystal oscillator 21.

The phase comparator 20 generates a difference signal having a frequency corresponding to the phase difference component between the output of the 90 ° phase shifter 19 and the reference signal V2. The difference signal obtained by the phase comparator 20 is converted to a DC voltage level by the loop filter 22, and then output to the VCXO 13 as a control voltage. Therefore, the VCXO 13 is controlled such that the frequency of the oscillation signal has no phase difference with the signal arriving from the satellite.

Next, the configuration of the frequency conversion unit 30 which is a feature of the present invention will be described. That is, the frequency conversion unit 30 receives the pilot frequency information provided separately from the incoming signal input to the input terminal 11,
And a DDS (Direct Digital Synthesizer) 32 for generating arbitrary frequency data based on the output of the CPU 31, and a D / D converter for converting the frequency data generated from the DDS 32 into a reference signal V3 which is an analog signal.
A converter 33 is provided.

First, the CPU 31 subtracts the frequency of the reference signal V2 generated from the crystal oscillator 21 from the frequency of the pilot signal extracted by the multiplier 12, based on separately provided pilot frequency information. In this case, CP
U31 previously stores the frequency generated by the crystal oscillator 21 in a memory circuit or the like (not shown). And CPU3
1 can monitor whether or not the frequency of the pilot signal at the time of reception has been changed by confirming the contents of the pilot frequency information. Whenever the frequency is changed, this changed information is used as address information. The reference signal V stored in the memory circuit is given to the memory circuit.
It is also possible to read out the second frequency information.

Upon receiving the difference data from the CPU 31, the DDS 32 generates frequency data corresponding to the difference data, and outputs the frequency data to the D / A converter 33. The DDS 32 operates based on a separately supplied clock signal.
When (N is an integer) MHz, 1 / N times frequency data is output.

The D / A converter 33 converts the frequency data output from the DDS 32 into an analog signal and outputs the analog signal to one input terminal of a multiplier 34 as a reference signal V3. The multiplier 34 inputs a pilot signal via the distributor 14 to the other input terminal and multiplies the pilot signal by the reference signal V3 to thereby adjust the frequency of the pilot signal to the frequency of the reference signal V2 generated from the crystal oscillator 21. Convert to

Next, the operation of the frequency conversion unit 30 will be described using numerical values. Here, the frequency of the pilot signal is 80
0 MHz and the frequency of the reference signal V2 generated from the crystal oscillator 21 is 10 MHz.
1 is a frequency 800 obtained from pilot frequency information.
The difference data of 790 MHz is generated by subtracting the frequency 10 MHz of the reference signal V2 from the MHz. And 79
The difference data of 0 MHz is given to the DDS 32 and
The data is converted into frequency data of 0 MHz, and thereafter, converted into a reference signal V3 of a frequency of 790 MHz by a D / A converter 33 and supplied to a multiplier. Then, the multiplier 34 generates a pilot signal having a frequency of 800 MHz and a frequency of 790 MHz.
A signal having a frequency of 10 MHz is generated by multiplying the signal by the reference signal V3 of z. For this reason, the frequency conversion unit 30 can generate a constant frequency of 10 MHz required for the phase comparison processing of the phase comparator 20 from the pilot signal.

Therefore, according to the above-described embodiment, in the frequency conversion section 30, the pilot frequency information provided separately from the pilot signal is fetched by the CPU 31, and the contents of the pilot frequency information are confirmed by the CPU 31 so that the satellite It is determined whether or not the frequency of the pilot signal transmitted from the side has been changed. Based on predetermined frequency information including this determination result, the frequency of the pilot signal extracted by the multiplier 12 is determined by the phase comparator 20. Of the reference signal V2 used in the phase comparison process of FIG. Then, the difference data is sequentially passed through the DDS 32 and the D / A converter 33 to be converted into a reference signal V3. Thereafter, the reference signal V3 is multiplied by a pilot signal by a multiplier 34, thereby obtaining a pilot signal. Is converted to the same frequency as the reference signal V2 used in the phase comparison processing. In short, by changing the difference data generated by the CPU 31, the reference signal V3 to be given to the multiplier 34 can be changed.

Therefore, it is not necessary to prepare a plurality of crystal oscillators according to the change in the frequency of the pilot signal, and it is not necessary to switch or exchange the plurality of crystal oscillators in accordance with the change in the frequency of the pilot signal. With the same circuit configuration as in the past, it is possible to execute the phase lock processing corresponding to a system with a different pilot signal without further increasing the price.

It should be noted that the PLL circuit according to the present invention is particularly intended for a circuit that performs a phase lock process in the circuit so as to eliminate a phase difference caused by a movement of a satellite as a communication partner. . Further, since the above-mentioned PLL circuit can support a system in which a pilot signal is different, the PLL circuit can be implemented, for example, to perform communication with a plurality of different satellites by switching the frequency each time.

It should be noted that the present invention is not necessarily limited to the scope of the above-described embodiment, and it goes without saying that various modifications can be made without departing from the scope of the present invention.

[0026]

As described in detail above, according to the present invention,
Even when used in a system with different pilot signal frequencies, there is no need to prepare or switch multiple crystal oscillators to match the different pilot signal frequencies, and the phase of the pilot signal is simple with a simple circuit configuration. It is possible to provide a PLL circuit that can realize the lock processing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a PLL circuit according to the present invention.

FIG. 2 is a block diagram showing a conventional PLL circuit.

[Explanation of symbols]

 12 multiplier, 13 VCXO, 14 distributor, 18 BPF, 19 phase shifter, 20 phase comparator, 21 crystal oscillator, 22 loop filter, 30 frequency converter, 31 CPU , 32 ... DDS, 33 ... D / A converter, 34 ... Multiplier.

Claims (4)

[Claims] 1. A signal extracting means for extracting an arbitrary pilot signal from an incoming radio wave from a satellite, and a pilot signal extracted by the signal extracting means is multiplied by a local oscillation signal to receive a frequency of the pilot signal. Frequency conversion means for converting to a frequency specified for processing, fixed oscillation means for generating a fixed oscillation signal having the same frequency as the frequency obtained by the frequency conversion means, and a fixed oscillation signal output from the fixed oscillation means. A phase comparator for comparing the phase of the output of the frequency converter with a signal shifted by 90 °, and controlling a phase difference between a pilot signal extracted from the signal extractor and a difference signal obtained by the phase comparator. And a signal extraction control means for converting the oscillation frequency into a signal having an oscillation frequency for performing The number conversion means is a frequency conversion control for generating a local oscillation signal such that the frequency of the pilot signal is the same as the frequency of the fixed oscillation signal generated from the fixed oscillation means, based on separately provided pilot frequency information. Means, by multiplying the pilot signal by a local oscillation signal generated from the frequency conversion control means,
A PLL circuit comprising: a multiplying means for converting a frequency of the pilot signal into a frequency of the fixed oscillation signal. 2. A calculating means for calculating a difference between a frequency of the pilot signal and a frequency of a fixed oscillation signal generated from the fixed oscillation means, based on pilot frequency information provided separately. 2. The PLL circuit according to claim 1, further comprising: a local oscillation signal generation unit that generates the local oscillation signal based on the difference data calculated by the calculation unit. 3. The local oscillation signal generating means according to claim 1,
3. The PLL circuit according to claim 2, wherein said local oscillation signal is generated according to a clock signal provided separately. 4. A direct digital synthesizer for generating arbitrary frequency data based on the differential data calculated by the calculating means, and a local oscillation signal generated by the direct digital synthesizer. 3. The PLL circuit according to claim 2, further comprising a digital / analog converter for converting frequency data into an analog signal.