JPH11308077A - Matched filter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a matched filter circuit which has the diffusion coefficient variable by considering that the diffusion coefficient must by changed in the future, in accordance with a use state and externally designating a diffusion coefficient. SOLUTION: This matched filter circuit provides a switch circuit 44 corresponding to a sample hold circuit 42 of a row that corresponds to a diffusion coefficient to be changed among sample hold circuits 42, which are arranged in accordance with rows of only several minutes of the maximum diffusion coefficient in each column of only several minutes of the maximum diffusion coefficient. This matched filter circuit turns off the corresponding switch circuit 44, in accordance with a diffusion coefficient by a controlling means 45 and electrically cuts off sample and hold circuits 42 after that.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matched filter circuit used in a receiver of a spread spectrum communication system for mobile communication or wireless LAN, and more particularly to a matched filter circuit capable of adjusting a spreading factor when used.

[0002]

2. Description of the Related Art In general, in a spread spectrum communication system, a transmission side performs two-stage modulation of transmission data on a transmission band and performs narrow-band modulation (primary modulation) and spread modulation (secondary modulation). Then, the received signal is despread to take out the primary modulated data, and then the baseband signal is reproduced by a normal detection circuit.

Here, as a circuit (despreading circuit) for despreading the spread-modulated signal, a sliding correlator or a matched filter circuit that performs synchronization acquisition and performs a correlation operation with the synchronization phase after the synchronization acquisition is used. ing.

A conventional sliding correlator will be specifically described with reference to FIG. FIG. 3 is a configuration block diagram of a conventional sliding correlator. As shown in FIG. 3, a conventional sliding correlator has an A / D
It comprises a converter 1, a multiplier 2, a PN code register 3, an adder 4, and a delay element 5.

[0005] The A / D converter 1 converts a received CDMA modulated analog signal into a digital signal and outputs the digital signal. The multiplier 2 multiplies a spread code (PN code; Pseudo Noise code) input from the PN code register 3 by a digital signal input from the A / D converter 1 and outputs the result.

The PN code register 3 generates and outputs a spread code. The adder 4 adds and combines the signal input from the multiplier 2 and the signal fed back via the delay element 5, and outputs the combined signal. The delay element 5 delays the signal input from the adder 4 by one chip time and feeds it back to the adder 4 for output.

The signal output by the adder 4 is output to the outside as a correlation output every time one symbol time elapses.

That is, the conventional sliding correlator converts the CDMA modulated analog signal into an A / D converter 1.
Is converted into a digital signal, the multiplier 2 multiplies the digital signal by the spread code input from the PN code register 3, and the adder 4 feeds back the signal via the delay element 5 and 2 and outputs the result. The delay element 5 delays the added signal by one chip time and feeds it back to the adder 4 for output. When the calculation is started, a correlation output at the phase is obtained after one symbol time has elapsed.

Therefore, the calculation is started from the phase of each chip, and the correlation output after the lapse of one symbol time is obtained, so that the phase of the chip with the maximum correlation output becomes the symbol start position (synchronous phase). It can be detected.

[0010] Such a conventional sliding correlator is relatively simple, has a small number of gates, and consumes little power. However, there is a problem that it takes a long time to acquire a correlation output after synchronization acquisition.

In view of this, a method of achieving synchronization acquisition in a short time by arranging a plurality of sliding correlators corresponding to the number of chips only in parallel and causing each sliding correlator to calculate a correlation output at a timing shifted by one chip is also considered. However, the circuit scale is large and not practical.

Further, a matched filter circuit can be used as the despreading circuit. The matched filter circuit is as shown in FIG. FIG. 4 is a configuration block diagram of a conventional matched filter circuit. The matched filter circuit includes an A / D converter 11 as shown in FIG.
, A sample-and-hold circuit 12, a multiplying means 13, and P
It comprises an N code register 14 and an adder 15.

The A / D converter 11 receives an input of a CDMA-modulated analog signal, converts the signal into a digital signal, and outputs the digital signal.

The sample-and-hold circuit 12 has flip-flop circuits (D-FF) connected in multiple stages by the number of chips per symbol. Each time a digital signal is input from the A / D converter 11, the sample-hold circuit 12 The digital signal input from the D-FF is held, and the currently held digital signal is sequentially stored in the D-FF of the subsequent stage.
Output to the FF and output to the multiplication means 13. The first stage D-FF holds the digital signal input from the A / D converter 11 instead of the digital signal input from the previous stage D-FF.

That is, the sample and hold circuit 12
Equipped with as many output terminals as chips per symbol
The digital signal input from the A / D converter 11 is output while being sequentially moved to a rear output terminal for each chip.

The multiplying means 13 comprises a sample and hold circuit 1
2 provided with a plurality of multipliers provided corresponding to the respective D-FFs, and multiplying the digital signal input from the corresponding D-FF by the corresponding PN code input from the PN code register 14. And outputs it as a digital signal.

The PN code register 14 is similar to the PN code register 3 of the sliding correlator except that the PN code corresponding to each chip is output to the multiplier of the corresponding multiplication means 13. ing.

The adding means 15 adds the signals input from the multiplying means 13 all at once and outputs the result as a correlation output.

Next, the operation of the conventional matched filter circuit will be described. The CDMA-modulated analog signal is converted into a digital signal by an A / D converter 11, held for each chip by a sample-and-hold circuit 12, sequentially sent backward, and output to a multiplying means 13.

Then, the multiplying means 13 receives as many signals as the number of chips, multiplies the corresponding PN codes inputted from the PN code register 14 and outputs the result. Then, the adding means 15 adds and synthesizes the signals output from the multiplying means 13 all at once, and outputs the resultant to the outside as a correlation output.

In such a matched filter circuit, the correlation output for each phase can be obtained all at once, so that the time required to achieve synchronization acquisition and obtain the correlation output is short, but the number of gates increases in accordance with the number of chips. As a result, power consumption increases.

[0022]

As described above, the conventional sliding correlator has a problem that it takes a long time to acquire the synchronization, and the matched filter circuit has a problem that the power consumption increases. Therefore, it is conceivable to configure a sliding correlator or a matched filter with an analog circuit. Specifically, a device using a correlator using a switched capacitor as a despreading circuit as an element for performing analog processing has been considered. A despreading circuit using a switched capacitor will be described with reference to FIGS. FIG. 5 is a circuit diagram showing a configuration of a correlator using a switched capacitor as a sample and hold circuit, and FIG. 6 is a circuit diagram of the sample and hold circuit.

As shown in FIG. 5, a correlator using a switched capacitor includes a multiplier 21 and a plurality of sample-and-hold circuits 22 provided corresponding to the number of chips per symbol.

The multiplier 21 receives an input of the CDMA-modulated analog signal, multiplies it by a separately input PN code, and outputs the result. Each sample and hold circuit 2
2 are arranged in parallel, and hold a signal input from the multiplier 21 when a signal indicating a timing for performing sample and hold (hereinafter, referred to as “S / H timing signal”) is received. Further, a signal indicating the timing of performing addition (hereinafter, referred to as “addition timing signal”)
Is output to one signal line (hereinafter, referred to as an "output signal line") at the point of time when the input is received. The specific configuration of the sample and hold circuit 22 will be described later.

Here, the S / H timing signal is sequentially and selectively output to each sample and hold circuit 22 every chip time, and the addition timing signal is simultaneously output to the sample and hold circuit 22 every symbol time. It is supposed to be.

Next, the sample and hold circuit 22 will be described. As shown in FIG. 6, the sample and hold circuit 22 includes a sample and hold timing terminal (S / H),
Data input terminal (IN) and data output terminal (OUT)
And an addition timing terminal (ADD), and includes a first FET 31, a capacitor 32, and a second FET 33.

An FET (Field Effect Transistor) has a gate terminal (G), a source terminal (S), and a drain terminal (D), and is controlled by a voltage (gate voltage) applied to the gate terminal (G). It is a semiconductor element that can control a current flowing between the source terminal (S) and the drain terminal (D).

Here, the source terminal (S) of the first FET 31 is connected to the data input terminal (IN), and the gate terminal (G) of the first FET 31 is connected to the sample hold timing terminal (S / H). Is connected. Also, the drain terminal (D) of the first FET 31 and the second FET
33 is connected to one of the source terminal (S) of the capacitor 32 and one of the terminals of the capacitor 32.
Grounded.

Further, an addition timing terminal (ADD) is connected to the gate terminal (G) of the second FET 33, and a drain terminal (D) of the second FET 33 is connected to the output terminal (OUT). . Output terminal (OUT)
Are connected to an output signal line common to each sample and hold circuit 22.

The first FET 31 is connected to the gate terminal (G) via a sample / hold timing terminal (S / H).
/ H timing signal is input, the source terminal (S)
A current flows between the drain terminal (D) and the drain terminal (D), and a signal input to the source terminal (S) is output from the drain terminal (D). That is, the first FET 31 receives the signal output from the multiplier 21 via the data input terminal (IN), and inputs the signal output from the gate terminal (G).
At the timing when the S / H timing signal is input to the D / A converter via the drain terminal (D).

The capacitor 32 stores the signal output from the first FET 31 via the drain terminal (D), and discharges the stored signal when the second FET 33 is turned on. .

When the addition timing signal is input to the gate terminal (G) via the addition timing terminal (ADD), a current flows between the source terminal (S) and the drain terminal (D). It flows, and the signal stored in the capacitor 32 is output from the drain terminal (D) from the source terminal (S). The second FET
The drain terminal (D) 33 is a data output terminal (OU)
T), the signal output from the second FET 33 is output to the outside via the data output terminal (OUT).

That is, a sliding correlator using a switch and a capacitor receives an input of a CDMA-modulated analog signal, and a multiplier 21 applies the signal to the PN signal.
The sample and hold circuit 22 that receives the input of the S / H timing signal multiplies the signal by the code and sequentially holds the signal output from the multiplier 21.

Each sample-and-hold circuit 22 receives the input of the addition timing signal after one symbol time has elapsed.
Simultaneously output the signals held therein to an output signal line, and obtain a signal obtained by adding and synthesizing the signals held by each sample and hold circuit 22 via the output signal line.

Since such a sliding correlator does not use an A / D converter, the power consumption can be reduced. Therefore, as shown in FIG. 7, the sliding correlators are arranged in parallel by the number of chips and used as a matched filter circuit. It is also realistic to make it work. FIG. 7 is a circuit diagram of a matched filter circuit using a switched capacitor.

The matched filter circuit shown in FIG.
In the sliding correlator, the sample / hold circuits 22 are arranged in parallel by the number of chips, and the timing at which the S / H timing signal is input to each sample / hold circuit and the timing at which the addition timing signal is input are described. There are features.

That is, as shown in FIG. 7, the S / H timing signals are input to the plurality of sample-and-hold circuits 42 of each column at timings sequentially shifted by one chip time. The input of the S / H timing signal is shifted by one chip time for each column. More specifically, signal lines (hereinafter, referred to as “S / H signal lines” and denoted by “C” in the figure) to which the S / H timing signals are sequentially transmitted are provided by the number of chips. The sample / hold circuits 42 of each column are diagonally connected to the sample / hold timing terminals (S / H) of the sample / hold circuits 42 from the first row to the first column and the kth column.

For example, the sample and hold circuit 42 in the second row and the first column and the sample and hold circuit 4 in the first row and the second column
2, S / H timing signals are input at the same timing.

Further, the addition timing signal is supplied to a signal line provided for each column (hereinafter referred to as "addition timing signal line").
) Are simultaneously input to a plurality of sample and hold circuits 42 in each column. In FIG. 7, the addition timing signal line is indicated by the symbol "A". Here, the addition timing signal is input at a timing shifted by one chip time for each column. Further, one output signal line (“B” in FIG. 7) is connected to each of the output terminals (OUT) of the plurality of sample and hold circuits 42 in each column.

Next, the operation of the matched filter using the switched capacitor will be described.
The multiplier 41 receiving the input of the A-modulated analog signal multiplies the PN code by the analog signal and outputs the result.

Then, the sample / hold circuit 42 in the first row and first column receives the input of the S / H timing signal and holds the signal output from the multiplier 41. And
After the elapse of one chip time, the sample and hold circuit 42 in the second row and the first column and the sample and hold circuit 42 in the first row and the second column hold the signal output from the multiplier 41.

Then, when one chip time elapses, the sample-and-hold circuits 42 in the third row and first column, the second row and second column, and the first row and third column output signals output from the multiplier 41. Will be retained.

As described above, when the sample-hold circuits 42 in the first column hold signals, the sample-hold circuits 42 in the first column receive the input of the addition timing signal all at once, and Is output to an output signal line corresponding to the above, and the signals held by each sample-hold circuit 42 in the first column are added and synthesized to the output signal line.

Further, after the elapse of one chip time, the sample-hold circuits 42 in the second column hold signals, and the sample-hold circuits 42 in the second column simultaneously input the addition timing signal. Then, a signal is output to the output signal line corresponding to the second column, and 2
The signals held by the sample and hold circuits 42 in the column are added and synthesized.

In this way, a correlation signal having each chip as an initial phase can be obtained on an output signal line corresponding to each column.

However, such a matched filter circuit has a spreading factor (number of chips) of, for example, 4, 8, 16, 32,
64, 128, 256
Although no consideration was given to changing the spreading factor based on an external signal, it is considered necessary to change the spreading factor in the future according to the use situation.

The present invention has been made in view of the above circumstances, and has as its object to provide a matched filter circuit in which the spreading factor is made variable by designating the spreading factor from outside.

[0048]

According to a first aspect of the present invention, there is provided a matched filter circuit comprising: a CDMA modulated analog signal;
A multiplier that multiplies the code, a plurality of sample and hold circuits arranged in a matrix direction, and a plurality of sample and hold circuits arranged in a row immediately after the sample and hold circuit corresponding to the spreading factor to be changed with respect to the plurality of sample and hold circuits , And control means for controlling ON / OFF of the switch circuit, wherein the plurality of sample-and-hold circuits hold the signal multiplied by the multiplier in the column direction for each symbol time for each chip. The unit is the basic correlator block,
The basic correlator block is a sample-and-hold circuit for holding, for each chip, a signal for one symbol time delayed by one chip in the row direction, and the plurality of switch circuits are turned on or off in row units. If there is, electrically connect the sample-hold circuit of the preceding stage in the column direction of the switch circuit and the sample-hold circuit of the subsequent stage in the column direction,
If it is off, it is a switch circuit that electrically separates the sample-hold circuit at the preceding stage in the column direction of the switch circuit from the sample-hold circuit at the subsequent stage in the column direction, and the control means controls the sample-hold circuit corresponding to the diffusion rate to be changed. It is a control means for turning off the switch circuit provided in the row immediately after and turning on another switch circuit provided in the row preceding the switch circuit,
The spreading factor can be adjusted at the time of use, and the parasitic output of the sample and hold circuit, which is separated and not used, does not adversely affect the addition accuracy, and the accuracy of the correlation output can be maintained.

According to a second aspect of the present invention, there is provided a matched filter circuit as set forth in the first aspect, wherein a plurality of switch circuits are arranged in a row next to the last stage of the sample and hold circuit. Is a switch circuit that connects a signal line of a sample-and-hold circuit preceding the switch circuit to a ground terminal when the switch circuit is turned on under the control of the control means, thereby suppressing wasteful power consumption.

According to a third aspect of the present invention, there is provided a matched filter circuit as set forth in the second aspect, wherein the control means is arranged to control a row immediately after the sample-and-hold circuit corresponding to the spreading factor to be changed. The control means turns off the switch circuit provided in the switch and turns on the other switch circuits excluding the switch circuit, thereby suppressing wasteful power consumption.

[0051]

Embodiments of the present invention will be described with reference to the drawings. In the matched filter circuit according to the embodiment of the present invention, a switch circuit is provided in a row immediately after a sample / hold circuit corresponding to a diffusion rate to be changed, and the subsequent sample / hold circuit is electrically operated by the switch circuit. The diffusion rate can be changed at the time of use.

A matched filter circuit (this circuit) according to the embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a circuit diagram of a matched filter circuit according to an embodiment of the present invention, and FIG.
FIG. Note that, similarly to FIG. 7, the output signal line is denoted by the symbol “A”, the addition timing signal line is denoted by the symbol “B”, and the S / H signal line is denoted by the symbol “C”. I do.

The present circuit, as shown in FIG.
And a plurality of sample-and-hold circuits 42 of the number of rows corresponding to the maximum spreading factor (the number of squares of the maximum spreading factor) for each column of the maximum spreading factor (number of chips), and a variable spreading factor. The switch circuit 44 includes a plurality of switch circuits 44 provided in a row immediately after the sample and hold circuit 42 in the corresponding row, and control means 45 for controlling the switch circuits 44.

Here, "column" means an array extending in the vertical direction in FIG. 7, and "row" means an array extending in the horizontal direction in FIG. In the claims, for the sake of convenience, the sample-and-hold circuits 42 are arranged by the number corresponding to the maximum spreading factor, and each column (the output signal line is shared) provided with the switch circuit 44 in the row immediately after the row corresponding to the spreading factor. A plurality of sample and hold circuits 42 and a plurality of switch circuits 4
4) is referred to as a “basic correlator block”.

The multiplier 41 receives the input of the CDMA-modulated analog signal, multiplies it by a separately input PN code, and outputs the result. Sample hold circuit 42
Are the same as those of the sample-and-hold circuit 22 shown in FIG. 6, each receiving the input of the S / H timing signal,
It holds the signal input from the multiplier 41, receives the addition timing signal, and outputs it simultaneously to the corresponding output signal line.

The sample-and-hold circuit 42 is provided as shown in FIG.
2 except that the switch circuit 44 is wired in the row next to the sample and hold circuit 42 in the row corresponding to the diffusion rate to be changed. That is, the switch circuit 44 sets the spreading factor to 4, 8, 16, 32,.
In the case of adjusting to 56, between the fourth row and the fifth row of the sample hold circuit 42 of each column (the row immediately after the fourth row of the sample hold circuit 42) and between the eighth row and the ninth row , Between the 16th and 17th rows,..., Immediately after the sample-hold circuit 42 on the 256th row (the last stage).

The switch circuit 44 is externally turned ON / OF.
When a signal for designating F is input and a signal for turning on is received, the sample / hold circuit 42 in the row after the switch circuit 44 adds the S / H signal line from the previous row to the sample / hold circuit 42. The timing signal line is connected to the output signal line.

The switch circuit 44 is connected to an external OF
When receiving the signal F, the switch circuit 4
The S / H signal line from the previous row, the addition timing signal line, and the output signal line are not connected to the sample and hold circuit 42 in the row after the fourth row. The circuit 42 is electrically disconnected. The specific configuration of the switch circuit 44 will be described later.

The control means 45 outputs a signal for instructing ON / OFF to the switch circuit 44 in accordance with the spreading factor. More specifically, the control means 45 immediately follows the row of the sample and hold circuit 42 having only the corresponding spreading factor. Switch circuit 44 in
FF and other switch circuits 44 ON
It is assumed that. For example, when the spreading factor is “4”, the control unit 45 outputs a signal to turn off to the switch circuit 44 located next to the fourth row, and outputs a signal to turn on to the other switch circuits 44. Output.

Here, the switch circuit 44 will be described with reference to FIG.
More specifically, the switch circuit 44 includes:
As shown in FIG. 2A, a first switch 51 for connecting an S / H signal line and a second switch 51 for connecting an addition timing signal line.
, And a third switch 53 for connecting the output signal line. Here, the first
The switch 51, the second switch 52, and the third switch 53 are turned on or off in conjunction with each other.

Further, the switch circuit 44 is provided as shown in FIG.
As shown in the figure, the first FET 5 connecting the S / H signal line
5 and a second FET 5 connecting the addition timing signal line
6 and a third FET 57 connecting the output signal line.

Here, each of the first FETs 55 and the second
The gate terminal (G) of each of the FET 56 and the third FET 57 is connected to each other, and each of the source terminal (S) and the drain thereof receives a signal of an instruction to turn on the gate terminal (G). The terminal (D) is connected.

Incidentally, the switch of the switch circuit 44 is normally O
N, and may be OFF only when a signal is applied.

Next, the operation of this circuit will be described for the case where the spreading factor is 4. First, the control unit 45 outputs a signal to turn off to the switch circuit 44 corresponding to the spreading factor and outputs a signal to turn on to the other switch circuits 44 in response to an instruction input from the outside.

Then, upon receiving the input of the CDMA-modulated analog signal, the multiplier 21 multiplies the PN code by the analog signal and outputs the result.

Then, the sample / hold circuit 42 in the first row and first column receives the input of the S / H timing signal and holds the signal output from the multiplier 41. And
After the elapse of one chip time, the sample and hold circuit 42 in the second row and the first column and the sample and hold circuit 42 in the first row and the second column hold the signal output from the multiplier 41.

When one more chip time has elapsed, three rows and one
Each of the sample and hold circuits 42 in the column, the second row, the second column, and the first row, the third column holds the signal output from the multiplier 41.

When the sample and hold circuits 42 in the first to fourth rows of the first column hold signals, the sample and hold circuits 4 in the first to fourth rows of the first column
2 simultaneously receive the input of the addition timing signal and output a signal to the output signal line corresponding to the first column, and the signal held by each sample and hold circuit 42 in the first column is added to the output signal line. It is obtained by being synthesized.

Further, after the elapse of one chip time, the sample and hold circuits 42 in the first to fourth rows in the second column hold signals, and the sample and hold circuits in the first to fourth rows in the second column are used. The circuit 42 simultaneously receives the input of the addition timing signal and outputs a signal to the output signal line corresponding to the second column, and the signal held by each sample-hold circuit 42 in the second column is output to the output signal line. It can be obtained by addition and synthesis. In this way, the signals held by the sample and hold circuits 42 up to the fourth row for each column are added and synthesized.

In this circuit, if the spreading factor is 8, for example, according to the spreading factor, the switch circuit 44 immediately after the sample-hold circuit 42 in the eighth row is turned off, and the sample-hold in the ninth and subsequent rows is turned off. If the circuit 42 is electrically disconnected and the spreading factor is 256, the last-stage switch circuit 44 immediately after the sample and hold circuit 42 in the 256th row
Becomes OFF, and all the sample and hold circuits 42 are connected. That is, according to this circuit,
Switch the unused sample-and-hold circuit 42 to the switch circuit 4
4 electrically separates the diffusion rate, which has the effect of adjusting the diffusion rate during use.

According to the present circuit, when the addition timing signal is input to the sample and hold circuit 42, the output signal line connected to the output terminal (OUT) of the unused sample and hold circuit 42 is separated by the switch circuit 44. Therefore, even when the spreading factor is small and the number of unused sample and hold circuits 42 is large, the parasitic capacitance of the wiring of the unused sample and hold circuit 42 does not adversely affect the addition accuracy, and the accuracy of the correlation output is reduced. There is an effect that can be maintained.

Further, in the row next to the last-stage switch circuit 44, the S / H signal line, the addition timing signal line, and the output signal line are connected to the ground terminal (Gnd) and grounded. Can be considered. In this way, the operation of the sample and hold circuit 42 after the switch circuit 44 corresponding to the designated spreading factor can be reliably stopped, and the generation of charge / discharge current for the unused sample and hold circuit 42 is prevented.
Even if the spreading factor is small, there is an effect that generation of useless power consumption can be suppressed.

Further, if only the sample-and-hold circuit 42 for one column is used in this circuit, it can be used as a sliding correlator that can adjust the spreading factor when used. If such a sliding correlator is used when synchronization is supplemented, there is an effect that power consumption can be further reduced because a small number of circuit parts are used.

[0074]

According to the first aspect of the present invention, the control means turns off the switch circuit provided immediately after the sample and hold circuit in the row corresponding to the spreading factor, and the control circuit is provided in the row before that. Since the other switch circuits are turned on and the matched filter circuit electrically disconnects the sample-and-hold circuit corresponding to the row after the turned-off switch circuit, there is an effect that the spreading factor can be adjusted during use,
In addition, the parasitic capacitance of the wiring of the sample hold circuit that is separated and not used does not adversely affect the addition accuracy, and the accuracy of the correlation output can be maintained.

According to the second and third aspects of the present invention, when the last switch circuit is turned on, a matched filter circuit for connecting the signal line of the preceding sample and hold circuit to the ground terminal Gnd is used. There is an effect that generation of charge / discharge current to the hold circuit is prevented, and generation of useless power consumption can be suppressed even if the diffusion rate is small.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a matched filter circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a switch circuit 44;

FIG. 3 is a configuration block diagram of a conventional sliding correlator.

FIG. 4 is a configuration block diagram of a conventional matched filter circuit.

FIG. 5 is a circuit diagram illustrating a configuration of a correlator using a switched capacitor as a sample and hold circuit.

FIG. 6 is a circuit diagram of a sample and hold circuit.

FIG. 7 is a circuit diagram of a matched filter circuit using a switched capacitor.

[Explanation of symbols]

1,11 ... A / D converter, 2,21,41 ... Multiplier,
3, 14: PN code register, 4: Adder, 5
... delay elements, 12, 22, 42 ... sample and hold circuits, 13 ... multiplication means, 15 ... addition means, 31, 3
3, 55, 56, 57 ... FET, 32 ... capacitor,
44 switch circuit 45 control means 51 5
2,53 ... Switch

Claims (3)

[Claims] A CDMA modulated analog signal and PN
A multiplier that multiplies the code, a plurality of sample and hold circuits arranged in a matrix direction, and a plurality of sample and hold circuits arranged in a row immediately after the sample and hold circuit corresponding to the spreading factor to be changed with respect to the plurality of sample and hold circuits And a control means for controlling ON / OFF of the switch circuit. The plurality of sample-and-hold circuits hold a signal multiplied by the multiplier in a column direction for each symbol time for each chip. The unit is a basic correlator block, and the basic correlator block is delayed by one chip in the row direction.
A sample-and-hold circuit for holding a signal for a symbol time for each chip, wherein the plurality of switch circuits are turned on or off in row units; This is a switch circuit that electrically connects the sample-hold circuit of the next stage to the sample-hold circuit of the next stage, and if it is off, it electrically disconnects the sample-hold circuit of the previous stage in the column direction of the switch circuit and the sample-hold circuit of the next stage in the column direction. The control means turns off the switch circuit provided in the row immediately after the sample-and-hold circuit corresponding to the spreading factor to be changed, and turns on another switch circuit provided in the row preceding the switch circuit. A matched filter circuit characterized by the following. 2. A plurality of switch circuits arranged in the next row of the last stage of the sample hold circuit, when turned on under the control of the control means, connect the signal line of the sample hold circuit in the preceding stage of the switch circuit to the ground terminal. 2. The matched filter circuit according to claim 1, wherein the switch circuit is a switch circuit. 3. The control means for turning off a switch circuit provided in a row immediately after a sample and hold circuit corresponding to a spreading factor to be changed, and turning on other switch circuits excluding the switch circuit. 3. The matched filter circuit according to claim 2, wherein the matched filter circuit is a means.