JPH11306772A - Writing method for nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a writing method for nonvolatile semiconductor memory in which gate disturb phenomenon of a non-select cell can be suppressed without causing any delay of writing speed at the time of writing of a select cell. SOLUTION: Memory cells each having a source region, a drain region, a floating gate electrode and a control gate electrode are arranged in matrix. The drain region, source region and control gate electrode of each cell or a cell unit comprising a plurality of cells are connected, respectively, with a bit line, a source line and a word line. Only the initial pulse voltage (first time pulse voltage) of being applied to a selected word line for the purpose of writing is lower than the subsequent pulse voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to an EPROM type nonvolatile semiconductor memory device which performs a write operation by hot electron injection.

[0002]

2. Description of the Related Art FIG. 9 shows a configuration example of a nonvolatile semiconductor memory device such as a flash memory or an EPROM. The memory cells 100 are arranged in a matrix, and each memory cell 100 has a large number of bits. FIG. 10 shows a basic configuration of the memory cell 100. A source region 21 and a drain region 22 for each cell are provided on a surface portion of the semiconductor substrate 20.
Are formed apart from each other, a floating gate electrode (floating gate electrode) 24 is arranged on the semiconductor substrate 20 between the two regions 21 and 22 via an insulating film 23, and an insulating film is formed on the floating gate electrode 24. A control gate electrode (control gate electrode) 26 extends through the gate 25, and the drain region 22 of each cell is connected to a bit line, the source region 21 is connected to a source line, and the control gate electrode 26 is connected to a word line. .

As shown in FIG. 10, a read operation is performed by applying a positive potential of 1 to 2 volts to a drain region 22, grounding a source region 21, applying Vcc to a control gate electrode 26, and checking whether a channel current flows. This is done by detecting whether or not it is not.

In data writing, as shown in FIG. 11, Vcc is applied to a drain region 22 and a source region 21 is applied.
Is grounded, a high voltage Vpp (for example, +12 volts) is applied to the control gate electrode 26, hot electrons are generated near the drain, the generated hot electrons are injected into the floating gate electrode 24, and the threshold voltage of the memory cell is reduced. This is done by raising it.

That is, at the time of writing, the drain region 22 of the selection transistor is provided with the source region 21 of the ground potential and the intermediate potential Vcc (for example, 5.5) higher than the substrate potential.
Volts) is applied, and at the same time, a higher potential Vpp (for example, +12 volts) than the drain potential is applied to the control gate electrode 26 of the select transistor, thereby generating hot electrons near the drain and causing the floating gate electrode 2 to generate hot electrons.
Inject into 4.

[0006]

However, during the above-described write operation, a high potential of, for example, +12 volts is applied to the control gate electrode 26 of the non-selected cell connected to the same word line as the selected cell. I will. For this reason, the gate voltage is pulled by the high control gate potential, electrons are injected from the substrate into the floating gate electrode 24 of the non-selected cell, and the threshold voltage of the non-selected cell is changed, that is, a so-called gate disturb phenomenon occurs.

In order to increase the data write speed, it is necessary to increase the potential applied to the control gate electrode 26 of the selected cell. In this case, the control gate of the unselected cell connected to the same word line is required. A high potential is also applied to the electrode 26, and the gate disturb phenomenon is further strengthened. Conversely, the gate disturb phenomenon can be suppressed by lowering the potential of the control gate electrode 26 at the time of writing. However, in that case, there is a problem that the writing speed becomes slow.

An object of the present invention is to provide a writing method for a nonvolatile semiconductor memory device capable of suppressing the gate disturb phenomenon of an unselected cell without slowing down the writing speed when writing to a selected cell. To provide.

[0009]

Means for Solving the Problems The present inventors have found the following. That is, when the control gate potential at the time of writing was changed (11 volts, 11.4 volts, 12 volts, 12.6 volts, and 13 volts), the change in the threshold voltage Vt from the start of application was measured. The result is
As shown in FIG. As shown by the relationship between the control gate potential Vcg and the write characteristics, it was found that the change in the threshold voltage Vt (write speed) hardly depends on the control gate voltage Vcg until the write time was 10 μs.

Therefore, the invention according to claim 1 is characterized in that a voltage lower than the write voltage is applied at an initial stage of writing before applying a predetermined voltage to a word line selected for writing. Features.

Therefore, compared to the conventional writing method in which a high voltage is always applied to the selected word line during the writing operation, the writing method of the present invention allows the writing speed to remain unchanged and the writing operation time to be reduced. The sum of the net voltages applied to the control gate electrodes of the selected cells can be reduced. As a result, the gate disturb phenomenon of the unselected cells can be suppressed.

Here, as described in the second aspect, one cycle from the start of voltage application to the word line selected for writing.
It is practically preferable to reduce the applied voltage for a period of up to 0 μsec.

Further, as described in claim 3, the applied voltage for writing is given by a pulse voltage having a fixed time width, and if only the initial pulse voltage is lower than the subsequent pulse voltages, it becomes practically impossible. It will be preferable.

Further, as described in the fourth aspect, the applied voltage for writing is given by a pulse voltage having a fixed time width. If only the first pulse voltage is lower than the subsequent pulse voltages, it is practically possible. It will be preferable.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of the flash memory, and FIG. 2 is a sectional view taken along line AA of FIG.

As shown in FIG. 2, P as a semiconductor substrate
In the single-crystal silicon substrate 1, a P-type silicon layer 1a
Is formed with a P-well layer 1b. An N ⁺ type source region (impurity diffusion region) 2 and an N ⁺ type drain region (impurity diffusion region) 3 for each cell are provided in the surface layer portion of the P well layer 1b.
Are formed apart from each other. Further, the P well layer 1b
In FIG. 1, a band-like N ⁺
A source common line (impurity diffusion region) 4 extends and the source region 2 of each memory cell is connected by the source common line 4.

As shown in FIG. 2, a floating gate electrode (floating gate) made of polycrystalline silicon is provided on a single crystal silicon substrate 1 via a thin silicon oxide film (tunnel oxide film) 5 as an insulating film. The floating gate electrode 6 has a rectangular shape and extends so as to pass between the source region 2 and the drain region 3. A strip-shaped control gate electrode (control gate electrode) 8 is disposed on the floating gate electrode 6 via a silicon oxide film (inter-gate insulating film) 7 as an insulating film.
The control gate electrode 8 is made of polycrystalline silicon, and extends in parallel with the common source line 4 as shown in FIG.

As shown in FIG. 2, a silicon oxide film 9 is disposed on the single crystal silicon substrate 1 including the periphery of the control gate electrode 8. A drain wire 11 made of aluminum is arranged on the silicon oxide film 9, and the drain wire 11 is electrically connected to the drain region 3 through a contact hole (opening) 10. In the present embodiment, a drain contact hole 10 common to two transistor cells is provided. Also, as shown in FIG. 1, contact holes (openings) 12a, 12b, 13a, 13 provided in the silicon oxide film 9 are formed.
The source wiring (not shown) is electrically connected to the source common line 4 through b. In the present embodiment, 8
Source contact hole 1 for each transistor cell
2a, 12b, 13a and 13b are provided.

FIG. 3 shows a peripheral circuit. X decoder 1
5 and a Y decoder / sense amplifier / write circuit 16. X decoder 15 has word lines 1, 2, 3,.
, N and j are connected to the control gate electrode 8 of each cell. The Y decoder / sense amplifier / write circuit 16 is connected to the drain region 3 of each cell via bit lines 1, 2, 3,..., M and k. The Y decoder / sense amplifier / write circuit 16 has source lines 1, 2, 3,.
, M and k are connected to the source region 2 of each cell.

Next, the operation of the flash memory configured as described above, particularly, the write operation will be described with reference to FIG. FIG. 4 shows an applied voltage waveform of the bit line (drain potential Vd) and an applied voltage waveform of the word line (control gate potential Vcg) at the time of writing. Writing is performed by injecting hot electrons generated near the drain into the floating gate electrode 6 by applying a control gate voltage Vcg higher than the drain voltage Vd. In this embodiment, the applied voltage is constant. It is given by a pulse voltage having a time width (10 μsec), and terminates the write operation when a predetermined threshold voltage is reached. In this example, the voltage application time for writing is set to 50 μsec.

In this way, this operation is performed for each bit in a state where a large number of memory cells are arranged. More specifically, for example, the write operation is performed in the memory cell 100 (word; n, bit;
m), as shown in FIG. 4, the X decoder 15 applies a pulse voltage of 11 volts to the word line n only once for the first time, and thereafter applies a pulse voltage of 12 volts four times. Only to the word line n. Further, a pulse (voltage) of 5.5 V is applied to the bit line m by the Y decoder / sense amplifier / write circuit 16. Note that the source line m is set to the ground potential. The application of the pulse voltage between the gate and the drain is performed synchronously.

By applying this voltage, the drain voltage Vd
(= 5.5 volts) higher than the control gate voltage Vcg (=
12 volts) is applied, and hot electrons generated near the drain are injected into the floating gate electrode 6. As a result, the memory cell 100 (n, m) has a predetermined threshold voltage V
t.

As described above, the initial stage of the write operation (to 10)
μsec), a low voltage of 11 volts is applied to the word line (control gate electrode 8), and the subsequent write operation (10
〜50 μsec), writing is performed by applying a high voltage of 12 volts to the word line (control gate electrode 8).

In the case of this example, the control gate potential Vcg shown in FIG.
As shown by the relationship between the voltage and the write characteristics, at least 11 volts to 1
In the range of the voltage Vcg of 3 volts, the writing speed hardly depends on the control gate voltage Vcg. Therefore, as shown in FIG. 4, the control gate voltage Vcg at the time of writing is
11 volts during 0 microseconds and 12 volts between 10 and 50 microseconds.
The writing speed does not change between the case where a volt is applied and the case where a high voltage of, for example, 12 volts is always applied as shown in FIG.

FIG. 6 shows the result of evaluating the write characteristics due to the difference in the write method. FIG. 6 shows that there is no difference in the write characteristics between the conventional write method shown in FIG. 5 and the write method of the present embodiment shown in FIG.

On the other hand, FIG. 7 shows the results of evaluation and comparison of gate disturb characteristics between the conventional writing method shown in FIG. 5 and the writing method of the present embodiment shown in FIG.
More detailed measurement conditions in this case are 5 ms for the control gate potential Vcg = 12 volts as the conventional method. In this method, after applying a voltage for 1 ms at a control gate potential Vcg = 11 volts, the control gate potential Vcg is applied.
= 12 volts for 4 ms. That is,
The total application time is 5 ms.

In FIG. 7, the central value of ΔVt (ΔVt1 value in the figure) is about 0.085 volts in the conventional method, while the central value of ΔVt (ΔVt10 value in the figure) is in the method of the present embodiment. Was about 0.06 volts. this is,
Since the voltage applied to the common word line differs between the conventional writing method and the writing method of the present embodiment at the beginning of the writing operation (between 0 and 10 μs in this example), the voltage is applied to the control gate electrode 8. This is because a difference occurs in the net voltage amount. That is, the net amount of applied voltage is smaller in the case of the write operation of the present embodiment.

At the time of writing, in the non-selected cells connected to the common word line, the source region 2 and the drain region 3
Is the ground potential, and the same high voltage as that of the selected cell is applied to the control gate electrode 8. Therefore, electrons are injected from the substrate of the non-selected cell to the floating gate electrode 6 by the tunnel effect through the tunnel insulating film 5 interposed between the substrate and the floating gate electrode 8, for example, and the threshold voltage of the non-selected cell is lowered. fluctuate.

Therefore, the lower the voltage applied to the common word line, the smaller the amount of electrons injected into the floating gate electrode 6 generated in the non-selected cells. Therefore, as shown in FIG.
The gate disturb phenomenon (change in the threshold voltage of the non-selected cells) can be suppressed by the writing method according to the present embodiment in which the net applied voltage amount during writing is small.

As described above, according to the writing method of the present embodiment, the gate disturb phenomenon can be suppressed without changing the writing speed. Thus, this embodiment is
It has the following features. (A) A voltage lower than the write voltage is applied in the initial stage of writing before applying a predetermined voltage to the word line selected for writing. Therefore,
Compared to the conventional write method in which a high voltage is always applied to the selected word line during the write operation, this write method applies the write speed to the control gate of the non-selected cell without changing the write speed. Since the sum of the net voltages to be performed can be reduced, the gate disturb phenomenon can be suppressed.

That is, as shown in FIG. 4, in a write initial operation in which the write speed does not depend on the control gate voltage, the potential applied to the selected word line is set to the low voltage Vcg1 and the floating gate electrode 6 of the selected cell is charged to a certain degree with electrons. Is injected, and after the threshold voltage is increased to some extent, in a subsequent write operation in which the write speed depends on the control gate potential, the voltage is applied to the selected word line in order to realize the required write speed. Voltage Vcg2
Is set to a voltage higher than Vcg1. As a result, in the write operation, compared to the conventional write method in which a high potential such as Vcg2 is always applied to the selected word line, the write method does not change the write operation time, and Since the sum of the net voltages applied to the control gates of the unselected cells can be reduced, the gate disturb phenomenon can be suppressed. (B) Since the applied voltage is lowered for a period of 10 μs from the start of the voltage application to the word line selected for writing, it becomes practically preferable. (C) The applied voltage for writing is given as a pulse voltage having a fixed time width, and only the initial pulse voltage is applied.
Since it is lower than the subsequent pulse voltage, it becomes practically preferable. (D) The applied voltage for writing is given as a pulse voltage having a fixed time width.
Since it is lower than the subsequent pulse voltage, it becomes practically preferable.

A feature of the present invention is that an initial write voltage pulse applied to the control gate applies a voltage lower than the subsequent pulse voltage. Therefore, FIG. 4 shows an example of the case of the same time pulse as an example. However, a low voltage is applied at, for example, 10 μsec at the beginning of writing, and the time width of the voltage pulse applied to the control gate after that is necessary for writing as a whole. It is sufficient that the application time is as short as possible, and it is not always necessary to use a single time pulse.

[Brief description of the drawings]

FIG. 1 is a plan view of a flash memory according to an embodiment;

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a circuit diagram showing an electrical configuration of a peripheral circuit.

FIG. 4 is a waveform chart for explaining an applied pulse.

FIG. 5 is a waveform diagram for explaining applied pulses for comparison.

FIG. 6 is a measurement diagram showing a relationship between a writing time and a threshold voltage.

FIG. 7 is a measurement diagram showing a change in threshold voltage.

FIG. 8 is a measurement diagram showing a change in threshold voltage.

FIG. 9 is a diagram showing a cell arrangement of a flash memory.

FIG. 10 is a cross-sectional view of a memory for explaining a read operation;

FIG. 11 is a cross-sectional view of a memory for explaining a writing operation;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P type single crystal silicon substrate, 2 ... Source region, 3 ... Drain region, 4 ... Source common line, 5 ... Silicon oxide film,
6: floating gate electrode, 7: silicon oxide film, 8: control gate electrode.

Claims (4)

[Claims] A source region and a drain region for each cell are formed at a distance from each other in a surface layer portion of a semiconductor substrate; a floating gate electrode is disposed on the semiconductor substrate between the two regions via an insulating film; A control gate electrode extends over the gate electrode via an insulating film, and further, a drain region in each cell or a cell unit including a plurality of cells arranged in a matrix is a bit line, and a source region is a source line. A method of writing data in a nonvolatile semiconductor memory device in which a control gate electrode is connected to a word line, wherein the voltage is lower than the write voltage in an initial stage of writing prior to applying a predetermined voltage to a word line selected for writing. A writing method for a nonvolatile semiconductor memory device, wherein a low voltage is applied. 2. The writing method for a nonvolatile semiconductor memory device according to claim 1, wherein the applied voltage is reduced during a period from the start of voltage application to a word line selected for writing to 10 μs. 3. The nonvolatile semiconductor memory device according to claim 1, wherein the applied voltage for writing is given as a pulse voltage having a predetermined time width, and only the initial pulse voltage is lower than the subsequent pulse voltages. Writing method. 4. The nonvolatile semiconductor memory device according to claim 1, wherein the applied voltage for writing is given as a pulse voltage having a fixed time width, and only the first pulse voltage is lower than subsequent pulse voltages. Writing method.