JPH11306016A - Register indirect branching instruction and branching instruction execution method with condition - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a power consumption of a processor in a delay term which occurs until a register indirect branching instruction and a branching instruction with a condition are read and executed and to reduce a consumption on the memory caused by having a no operation(NOP) instruction written on the program memory. SOLUTION: When an instruction read out of a program memory 102 and latched by an instruction latch circuit 103 is a register indirect instruction or a branching instruction with a condition, the instruction latch circuit 103, an instruction decode latch circuit 105 or operation of these peripheral circuits are partially and selectively stopped by an instruction fetch stop signal or an instruction decode stop signal outputted from an NOP control circuit 109 during the following delay period, so a power consumption is suppressed. Moreover, since decode data regarding the NOP instruction are designed to be automatically inserted after the register indirect branching instruction or the branching instruction with a condition so as to fill in this delay term, it becomes unnecessary to write the NOP instruction on the program memory 102 and the consumption of a storage space on the memory is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for executing a register indirect branch instruction and a conditional branch instruction in a processor or the like for general-purpose equipment.

[0002]

2. Description of the Related Art FIG. 2 shows a functional configuration of a processor according to one prior art, particularly a portion relating to execution of a register indirect branch instruction and a conditional branch instruction. The processor shown in this figure includes a program memory control circuit 101 that controls reading of an instruction from a program memory 102. The program memory control circuit 101 supplies a latch control signal to the instruction latch circuit 103, and causes the instruction read from the program memory 102 to be latched by the instruction latch circuit 103. Instruction decode circuit 10
Reference numeral 4 generates instruction decode data by decoding the instruction latched by the instruction latch circuit 103. The instruction decode latch circuit 105 stores the instruction decode data obtained by the instruction decode circuit 104,
Latch is performed according to a latch control signal from the program memory control circuit 101. In this prior art, a latch control signal supplied from a program memory control circuit 101 to an instruction latch circuit 103 and an instruction decode latch circuit 1
05, the instruction fetch operation of latching the data read from the program memory 102 by the instruction latch circuit 103, and the instruction decode data obtained from the instruction decode circuit 104. The instruction decoding operation latched by the latch circuit 105 is simultaneously executed in parallel in a pipeline manner. Further, these processes are repeatedly executed at predetermined cycles.

When an instruction on the instruction latch circuit 103 is a register indirect branch instruction, instruction decode data indicating that the instruction is a register indirect branch instruction is latched by the instruction decode latch circuit 105. In response to this, the branch destination address stored as data on the general-purpose register 106 is stored in the program memory control circuit 10.
Read to 1. Program memory control circuit 101
Uses the read branch destination address as the read address,
Data is read from the program memory 102 and latched by the instruction latch circuit 103. by this,
A register indirect branch instruction for accessing the program memory 102 with reference to a branch destination address stored in the general-purpose register 106 is executed.

When the instruction latched by the instruction latch circuit 103 is a conditional branch instruction, instruction decode data indicating this is latched by the instruction decode latch circuit 105, and the contents of the condition flag 107 are controlled by the program memory control. Referenced by the circuit 101. The program memory control circuit 101 sets the condition flag 107
If the branch condition given by (1) matches the condition related to the conditional branch instruction, the address is output to read the instruction at the branch destination from the program memory 102. As a result, when a certain condition is satisfied, a conditional branch instruction that sets an address related to the program memory 102 to a certain address and branches execution of the program is executed.

In executing these register indirect branch instructions and conditional branch instructions, in the above-described prior art, there is a problem that a storage space in the program memory 102 is used extra by a no operation (NOP) instruction. However, there is a problem that power is consumed by the processor to execute the NOP instruction. That is, in order to execute a register indirect branch instruction or a conditional branch instruction, an instruction fetch operation of latching an instruction from the program memory 102 by the instruction latch circuit 103,
An instruction decoding operation of decoding an instruction from the instruction decode circuit 104 and latching the obtained instruction decode data by an instruction decode latch circuit 105; and determining a branch destination or branching by referring to the general-purpose register 106 or the condition flag 107 Three types of operations, that is, a register or flag reference operation of determining whether or not to perform the operation, must be performed step by step. Therefore, a delay of at least two cycles occurs between the reading of the register indirect branch instruction or the conditional branch instruction from the program memory 102 and the execution of the instruction. Conventionally, the instruction fetch operation and the instruction decode operation are continuously executed without any trouble during the two cycles related to the delay.
Two OP instructions were inserted. Thus, to compensate for the two-cycle delay that occurs from the reading of an instruction to its execution, N
If the OP instruction is inserted, power consumption for executing the two NOP instructions occurs, and the NO
A storage space on the program memory 102 is used to store the P instruction.

[0006]

SUMMARY OF THE INVENTION One object of the present invention is to reduce the power generated by a processor in two cycles related to the delay between reading and executing a register indirect branch instruction or a conditional branch instruction. . One of the objects of the present invention is to prevent the storage space on the program memory from being used a lot by inserting two NOP instructions after a register indirect branch instruction or a conditional branch instruction on the program memory. The purpose is to reduce the amount of memory used.

In order to achieve the above object, a register indirect branch instruction according to the present invention comprises an instruction fetch operation for reading an instruction on a program memory under the control of a program memory control circuit and latching the instruction by an instruction latch circuit; An instruction decoding operation of decoding an instruction on the latch circuit and latching the instruction decode data obtained by the instruction decode latch circuit, and performing a program when the instruction decode data on the instruction decode latch circuit is data indicating a register indirect branch instruction A register indirect branch instruction execution method for simultaneously executing a register reference operation of giving a branch destination address on a register to a program memory control circuit to be a read address from a memory to a program memory control circuit in a predetermined cycle and in a pipeline manner. Instruction decode operation When the instruction on decree latch circuit is a register indirect branch instruction is found, it stops the instruction fetch operation in the current cycle and the next cycle,
The instruction decode operation is stopped in the next cycle and the next cycle, and while the instruction decode operation is stopped, N
The present invention is characterized in that instruction decode data relating to an OP instruction is used for register reference operation instead of instruction decode data on an instruction decode latch circuit.

Further, the conditional branch instruction execution method according to the present invention includes an instruction fetch operation for reading an instruction on a program memory under control of a program memory control circuit and latching the read instruction on an instruction latch circuit, and an instruction on the instruction latch circuit. And a condition flag for giving a branch condition when the instruction decode data on the instruction decode latch circuit is data indicating a conditional branch instruction. And a flag reference operation for giving a flag to the program memory control circuit at the same time in a predetermined cycle and in a pipelined manner in a conditional branch instruction execution method. The current cycle The instruction fetch operation is stopped in the next cycle, the instruction decode operation is stopped in the next cycle and the next cycle, and the instruction decode data relating to the NOP instruction is decoded on the instruction decode latch circuit while the instruction decode operation is stopped. It is characterized in that a flag reference operation is performed instead of data.

A processor according to the present invention controls a program memory control circuit for reading an instruction from a program memory, and latches the instruction read from the program memory in accordance with a latch control signal from the program memory control circuit. Instruction latch circuit, an instruction decode circuit for decoding an instruction on the instruction latch circuit, an instruction decode latch circuit for latching instruction decode data obtained thereby according to a latch control signal from a program memory control circuit, and an instruction decode latch circuit A reference means for giving the branch destination or the branch condition to the program memory control circuit when the above instruction decode data is data relating to an instruction that indirectly determines a branch destination or a branch condition. In the instruction latch circuit If the instruction determines the branch or branch condition indirectly, the instruction fetch stop signal for the program memory control circuit is turned on in the current cycle and the next cycle, and the instruction decode for the program memory control circuit is stopped in the next cycle and the next cycle. A NOP control circuit for turning on a signal, and a switching circuit for providing instruction decode data relating to a NOP instruction to a process relating to a referenced means instead of instruction decode data on an instruction decode latch circuit while an instruction decode stop signal is on The program memory control circuit stops the instruction latch operation by the instruction latch circuit while the instruction fetch stop signal is on, and the instruction decode data latch circuit while the instruction decode stop signal is on. To stop instruction decode data latch operation by And wherein the door.

As described above, according to the present invention, when an instruction such as a register indirect branch instruction or a conditional branch instruction that indirectly determines a branch destination or a branch condition using a register or a flag is read from the program memory. In addition, since a part of the operation related to the instruction fetch and the decoding is stopped from the time the instruction is read until the instruction is executed, power consumption by the processor can be suppressed. Further, in a cycle related to a delay from the time when such an instruction is read from the program memory to the time when the instruction is executed, N
Since the OP instruction is automatically inserted, it is not necessary to insert a two-cycle NOP instruction after the register indirect instruction or the conditional branch instruction on the program memory, and therefore, the storage space controlled on the program memory Can be reduced.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. Note that the same reference numerals are given to the same or corresponding components as those of the conventional technology shown in FIG.
The description is partially omitted.

FIG. 1 shows a functional configuration of a processor according to an embodiment of the present invention, particularly a portion related to execution of a register indirect branch instruction and a conditional branch instruction. In this embodiment, a switching circuit 108 is provided at a stage subsequent to the instruction decode latch circuit.
There is provided a NOP control circuit 109 for generating an instruction fetch stop signal and an instruction decode stop signal in response to the stop control signal generated by 4A.

In this embodiment, if the instruction on the instruction latch circuit 103 is a register indirect branch instruction or a conditional branch instruction, the instruction decode circuit 104A
A stop control signal is supplied to the control circuit 109, and the NOP control circuit 109 turns on the instruction fetch stop signal in response thereto. The program memory control circuit 101A keeps the instruction latch circuit 103 while the instruction fetch stop signal is on.
Is turned off, and the latch of the instruction from the program memory 102 is stopped.

In the next cycle, the NOP control circuit 109 newly turns on the instruction decode stop signal while keeping the instruction fetch stop signal on. The program memory control circuit 101A turns off the latch control signal for the instruction decode latch circuit 105 in response to the instruction decode stop signal turning on. Therefore, in this cycle, the latch operations of both the instruction latch circuit 103 and the instruction decode latch circuit 100 are stopped.

In the next cycle, NO
The P control circuit 109 turns off the instruction fetch stop signal while keeping the instruction decode stop signal on. Therefore, in this cycle, the instruction latch operation from the program memory 102 by the instruction latch circuit 103 is restarted.
The latch operation of the instruction decode data by the instruction decode latch circuit 105 continues to be stopped.

In the next cycle, NO
The P control circuit 109 turns off both the instruction fetch stop signal and the instruction decode signal. Thus, the instruction decode latch circuit 105 also restarts the instruction decode data latch operation.

The switching circuit 108 operates while the instruction decode latch circuit 105 stops latching the instruction decode data, that is, the instruction decode latch circuit 10
While the latch control signal for No. 5 is off, the instruction decode data relating to the NOP instruction is input instead of the instruction decode data latched by the instruction decode latch circuit 105. Therefore, the instruction decode latch circuit 1
While the latch control signal 05 is off, the contents of the general-purpose register 106 and the condition flag 107 are not referred to by the program memory control circuit 101A.

Therefore, after a register indirect branch instruction or a conditional branch instruction is read from the program memory 102 and latched by the instruction latch circuit 103, the instruction is generated before the instruction is executed in the program memory control circuit 101A. The two-cycle delay does not result in increased power consumption by the processor. That is,
Instruction latch circuit 103 and instruction decode latch circuit 105
And the peripheral operation is partially stopped, so that power consumption is suppressed. Further, since the NOP instruction to be inserted during the two-cycle delay period is automatically inserted in the switching circuit 108 in the form of NOP instruction decode data, there is no need to store the NOP instruction on the program memory 102. The occupation amount of the storage space on the program memory 102 is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a main configuration of a processor according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a main part of a processor according to one related art.

[Explanation of symbols]

101A program memory control circuit, 102 program memory, 103 instruction latch circuit, 104A instruction decode circuit, 105 instruction decode latch circuit, 106
General-purpose register, 107 condition flag, 108 switching circuit, 109 NOP control circuit.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Hideaki Yoshida 5-1-1 Shimorenjaku, Mitaka City, Tokyo Japan Radio Co., Ltd.

Claims (3)

[Claims] An instruction fetch operation in which an instruction on a program memory is read under the control of a program memory control circuit and latched by an instruction latch circuit, and instruction decoded data obtained by decoding the instruction on the instruction latch circuit is transmitted to the instruction latch. An instruction decoding operation to be latched by the decode latch circuit, and when the instruction decode data on the instruction decode latch circuit is data indicating a register indirect branch instruction, the branch destination address on the register is set as a read address from the program memory. In a register indirect branch instruction execution method for simultaneously executing a register reference operation to be given to a memory control circuit every predetermined cycle and in a pipeline manner, an instruction on an instruction latch circuit is a register indirect branch instruction by an instruction decode operation Turned out to be Sometimes, the instruction fetch operation is stopped in the current cycle and the next cycle, the instruction decode operation is stopped in the next cycle and the next cycle, and the instruction decode data of the no-operation instruction is decoded while the instruction decode operation is stopped. A register indirect branch instruction execution method, wherein a register reference operation is performed instead of instruction decode data on a latch circuit. 2. An instruction fetch operation in which an instruction on a program memory is read out and latched by an instruction latch circuit under the control of a program memory control circuit, and an instruction on the instruction latch circuit is decoded and instruction decode data obtained by the instruction is read. An instruction decoding operation for latching by the decode latch circuit, and a flag reference operation for giving a condition flag to the program memory control circuit to give a branch condition when the instruction decode data on the instruction decode latch circuit is data indicating a conditional branch instruction. In a conditional branch instruction execution method in which the instruction in the instruction latch circuit is determined to be a conditional branch instruction by an instruction decode operation, Instruction fetch operation in the next cycle Was stopped,
In the next cycle and the next cycle, the instruction decode operation is stopped, and during the stop of the instruction decode operation, the instruction decode data relating to the no-operation instruction is used for the flag reference operation instead of the instruction decode data on the instruction decode latch circuit. And a conditional branch instruction execution method. 3. A program memory control circuit for controlling reading of an instruction from a program memory, an instruction latch circuit for latching an instruction read from the program memory according to a latch control signal from the program memory control circuit,
An instruction decode circuit for decoding an instruction on an instruction latch circuit, an instruction decode latch circuit for latching instruction decode data obtained by the instruction control signal from a program memory control circuit, and an instruction decode data on the instruction decode latch circuit Reference means for giving the branch destination or the branch condition to the program memory control circuit when the data is data relating to an instruction that indirectly determines the branch destination or the branch condition. When the above instruction is an instruction for indirectly determining a branch destination or a branch condition, an instruction fetch stop signal for the program memory control circuit is turned on in the current cycle and the next cycle, and the program memory control circuit is turned on in the next cycle and the next cycle. Instruction decode stop signal for A NOP control circuit for turning on, and a switching circuit for performing a process related to the referred means instead of the instruction decode data on the instruction decode latch circuit for the instruction decode data related to the no operation instruction while the instruction decode stop signal is on. The program memory control circuit stops the instruction latch operation by the instruction latch circuit while the instruction fetch stop signal is on, and operates by the instruction decode data latch circuit while the instruction decode stop signal is on. A processor for stopping an instruction decode data latch operation.