JPH11288400A - Pci bridge device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit amount of a PCI(peripheral component interconnect) bridge device. SOLUTION: The pseudo configuration spaces 4, 5...6 of a device connected to a secondary side pseudo PCI bus 7 are realized. For that, a secondary side pseudo PCI interface part 19 obtains the information (function number to be shown to a primary side PCI bus 1) of the device immediately after reset. A decoding part 20 makes the information of the device and IDSEL to be outputted to the secondary side pseudo PCI bus 7 correspond to each other. Then, upon detecting a configuration cycle, a primary side PCI interface part 18 relays the cycle together with the secondary side pseudo PCI interface part 19 and the decoding part 20 replaces the bits of a part of the information of the device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PCI bridge device for connecting a primary PCI bus and a secondary PCI bus. Here, PCI is Periphera
l Component Interconnect is an abbreviation for PCI bus. A PCI bus is a PCI that is used by hundreds of PC-related manufacturers, mainly Intel Corporation.
This refers to the local bus architecture formulated by the Special Interest Group.

[0002]

2. Description of the Related Art A processor has a plurality of devices, for example,
When connecting a modem, an accelerator, a sound, and the like to a bus, the number of connectable devices is limited due to the bus capability. Therefore, conventionally, the bus is hierarchized. For example, in the case of a two-layer bus configuration, a connectable device is provided by interposing a PCI bridge device between the primary PCI bus on the processor side and the secondary PCI bus on the device. We are trying to increase the number.

[0003]

However, since the above-described conventional PCI bridge device is standardized, there is a problem that the amount of circuit increases if the PCI bridge is designed according to this plan.

[0004] It is an object of the present invention to provide a PCI bridge device in which the circuit amount is reduced while conforming to the PCI standard.

Another object of the present invention is to obtain a device having a plurality of functions of an existing device equivalently.

[0006]

SUMMARY OF THE INVENTION A PCI bridge device of the present invention is interposed between a primary PCI bus and a secondary PCI bus, and has a configuration space for a target device connected to the secondary PCI bus. Is realized in oneself in a pseudo manner. The primary PCI bus is configured such that the target device connected to the secondary PCI bus appears to have one function of the device connected to the primary PCI bus.

Preferably, the PCI bridge device of the present invention stores information of the target device (information such as a function number of the target device and resources required by the target device, etc.) immediately after the reset, in a configuration space of the target device. And a decoding unit that replaces a part of bits of the device information at the time of reading a configuration cycle, in correspondence with the IDSEL signal on the secondary PCI bus. .

Preferably, the PCI bridge device of the present invention is a PCI bridge device for the target device having a plurality of functions, wherein the pseudo configuration space is realized for each of the functions. And

[0009] Preferably, the PCI bridge device according to the present invention is characterized in that some target devices are substantially provided in itself.

[0010]

Next, an embodiment of the present invention will be described.

The PCI bridge device of the present invention is interposed between the primary PCI bus and the secondary PCI bus, and simulates the configuration space of the target device connected to the secondary PCI bus within itself. Realized The primary PCI bus is configured so that the target device connected to the secondary PCI bus appears to be connected to the primary PCI bus. here,
What is aware of where the accessing target is connected is a host bridge, an actual PCI bridge, or software.

Here, the configuration space is
A space for holding data of the device, for example, a device ID, a vendor ID, a subsystem ID, and the like, and is specifically realized by a register, an EEPROM, or the like. In addition, the initiator device is also called a master device, and is a device that can be an access subject to another device, and the target device is a device that is an access object by the master device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of an add-in card equipped with a PCI bridge device according to the present invention. The add-in card includes a PCI bridge device 3, eight target devices 12,
Add-in card 2 containing 14-16 is the primary PC
1 shows a state in which it is connected to the I bus 1. The bridge device 3, the target devices 12, and 14 to 16
Hereinafter, these are referred to as device 3, device 12, and 14 to 16.

In the device 3, devices 12, 14 connected to the device 3 via the secondary side pseudo PCI bus 7 are provided.
~ 16 each configuration space 13,15 ~ 17
Corresponding to the pseudo configuration space 4,5
To 6 virtually exist.

That is, when viewed from the primary side PCI bus 1, the device 1 connected to the secondary side pseudo PCI bus 7
2, 14 to 16 appear as one of the functions (functions) of the device 3. In short, from the primary PCI bus 1, the device 3 appears as a single device having eight functions. Thus, the primary PC
It is possible to relatively easily provide an environment for mounting a plurality of devices on the add-in board 2 with a reduced electric load on the I bus 1.

From the primary side PCI bus 1 to the 0th
When a configuration cycle (initialization cycle) is accessed for a function, the device 3 relays the cycle as a configuration cycle for the device 12 connected to the secondary pseudo PCI bus 7. Thus, the configuration space 13 of the device 12 can be read as the configuration space 4 of the device 3. At this time, as will be described later, some bit data of the read-only bits are replaced. Similarly, the configuration space of the device 14 can be read as a first function 5, and the configuration space 15 of the device 17 can be read as a seventh function.

In a cycle other than the configuration from the primary side, the device 3 relays to the secondary side as it is.

In addition, instead of the add-in card 2 shown in FIG. 1, as shown in FIG.
The bus 7 and the devices 12, 14 to 16 may be accommodated on a motherboard, that is, the same board as the primary PCI bus 1.

FIG. 3 is a block diagram showing details of the device 3. As shown in FIG. The device 3 is a primary PCI interface unit 18 that simply relays the configuration cycle on the primary PCI bus 1 to the secondary pseudo PCI bus.
And a secondary side pseudo PCI interface unit 19.
When a configuration cycle occurs for each function of the device 3, the secondary side pseudo PC for the device corresponding to each function is used.
It also has a decoding unit 20 for activating S_IDSEL [0-7] of the I bus 7. When relaying the configuration cycle, the device 3 also has a function of converting the function number bit existing in the configuration cycle so as to match each device connected to the secondary side pseudo PCI bus 7. The device 3 sends a configuration cycle for each function of the device 3 by returning data of a device connected to the secondary side pseudo PCI bus 7 or to a device connected to the secondary side pseudo PCI bus 7. By writing, from the primary side PCI bus 1, the device 3
Show that each function exists in. However, if all the data in the configuration space of each device connected to the secondary side pseudo PCI bus 7 is returned to the primary side PCI bus 1 as it is, a contradiction arises. Has the function of replacing and returning the bits. Here, a part of the bits is a Heade denoting a multi-function.
bit 7 of the rType register, an InterruptPin register indicating the interrupt used by the device,
If necessary, DEVSEL T in the Status register
Indicates an iming bit or the like.

Since the signals on the PCI bus and the bits of the configuration register in FIG. 3 are well known to those skilled in the art, their details are omitted.

Next, the operation of this embodiment will be described.

FIG. 4 is an example of a flow of one operation of the device 3 performed immediately after the reset. If the reset signal is not active (34), information of each device connected on the secondary side pseudo PCI bus 7 is acquired (2).
5). Here, the device information is the device 12, 1
Function numbers and devices 12 and 14 to 16 performed by 4 to 16
Means information such as resources required by At 26, the functions of the devices 12, 14 to 16 on the secondary pseudo PCI bus 7 are assigned to the apparent functions in the device 3 based on the information obtained at 25. This allows the device 3 to be seen from the primary PCI1 bus.
And S_ID on the secondary side pseudo PCI bus 7
SEL [0: 7] can be assigned.

FIG. 5 is a flowchart showing an operation example of the device 3.

First, if the reset signal is not active (34), it is determined whether or not a cycle for the device 3 has occurred on the primary PCI bus (35). Next, the DEVSEL signal is asserted to the primary PCI bus 1 to indicate that the device 3 is the target (3).
6), it is determined whether the flow of FIG. 4 has been completed (37).
If this is NO, the cycle that has occurred on the primary PCI bus 1 ends with a retry (39). If YES, it is determined whether the cycle is a configuration cycle (38). If NO at 38, device 3
Simply relays the cycle to the ordinary secondary side pseudo PCI bus 7 (46).

On the other hand, if YES at 38, it is determined whether the configuration cycle is a read or write cycle (40), and if it is a read cycle, it is determined whether it is an access to a configuration register that requires data replacement (41). ). If the answer is YES at 41, the cycle is relayed as usual and the primary PCI bus 1
Only the bits that need to be replaced are replaced (43). At this time, since there is a possibility that the parity signals on the primary PCI bus 1 may be inconsistent, the parity signal is generated in the parity generation unit 33 in FIG.

At 40, in the case of a write cycle, it is determined whether or not it is a write cycle to the Base Address register in the configuration space (42). 42
Is YES, the cycle is relayed as usual (46), and the write data to the Base Address register is also held in the device 3. This data is 3
5 is used to determine whether the resource matches the resource of the device on the secondary side pseudo PCI bus 7. The configuration register, the retry, and the like are well known to those skilled in the art, and thus the details thereof are omitted.

FIG. 6 is an example of a timing chart of the bus operation showing the relay of the actual cycle. The basic operation of the relay is performed by latching the signal received on each bus with the PCI clock CLK and outputting the latched signal to the opposite bus. However, in the next clock after the data transfer, TRDY on the primary PCI bus 1 and the secondary pseudo PC
S_IDRY on the I bus 7 is deasserted. Also,
The output DEVSEL signal to the primary side PCI bus 1 is based on the device information on the secondary side pseudo PCI bus 7 held in the device 3 and if necessary, the secondary side pseudo PCI bus 7
Before S_DEVSEL is asserted above, the primary P
Assert on CI bus 1. This operation enables basic relay of the cycle.

While the above has described an example of a configuration in which eight devices are connected to the secondary-side pseudo PCI bus 7, the present invention is not limited to this. You may.

Next, FIG. 8 shows an embodiment in which a device having a plurality of functions is connected to the secondary side pseudo PCI bus 7. In this example, the device 50 is a device having two functions.
Are assigned to the second function (configuration 47) and the third function (configuration 48) of the device 3 one by one.

FIG. 9 shows an embodiment in which the device 3 has a function corresponding to the device 12 shown in FIG. 7 as a substance. According to the present embodiment, when the device 14 already exists and a device having a function equivalent to the device 12 is to be newly designed, the device 3 having the bridge function of the present invention and the function of the device 12 is designed. This has the advantage that the chip of the device 14 can be used as it is.

FIG. 10 shows an embodiment in which the present invention is applied to a card bus, which is a bus similar to a PCI bus. One device that can be connected to the card bus is determined by the standard. Therefore, if it is desired to design a card having a plurality of functions, it is necessary to use a card bus-to-card bus bridge or design a new device having a plurality of functions. However, it is also possible to satisfy such a requirement by using the present invention. However, IDSE of PCI bus is used for the card bus.
Since there is no signal corresponding to L and the configuration cycle is identified by AD1 and AD0, it is necessary to prepare AD1 and AD0 on the secondary side pseudo card bus 54 for each device.

[0033]

According to the present invention, since the above configuration is adopted, the electric load on the primary PCI bus can be reduced.
Mounting of a plurality of devices on an add-in board can be provided by a relatively simple circuit.

Instead of designing a device having a plurality of functions of an existing device, an existing device chip can be used as it is. That is,
Since detailed design data of an existing device is not required, a device having a plurality of functions can be created by using a device manufactured by another manufacturer, which is usually difficult.

The present invention can be applied to a card bus which is a bus similar to a PCI bus. The card bus, which is often used for notebook computers, does not allow multiple devices to be mounted on a card. According to the present invention, a plurality of existing devices can be mounted.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of an add-in card using a PCI bridge device of the present invention.

FIG. 2 is a diagram showing a first embodiment of a motherboard using the PCI bridge device of the present invention.

FIG. 3 is a diagram showing one embodiment of a PCI bridge device of the present invention.

FIG. 4 is a flowchart showing an operation immediately after reset of the embodiment shown in FIG. 3;

FIG. 5 is a flowchart showing the operation of the embodiment shown in FIG. 3;

FIG. 6 is a timing chart of the embodiment shown in FIG. 3;

FIG. 7 is a diagram showing a second embodiment of a motherboard using the PCI bridge device of the present invention.

FIG. 8 is a diagram showing a third embodiment of the motherboard using the PCI bridge device of the present invention.

FIG. 9 is a diagram showing a fourth embodiment of a motherboard using the PCI bridge device of the present invention.

FIG. 10 is a diagram showing an embodiment in which the present invention is applied to a card bus.

[Explanation of symbols]

1 Primary side PCI bus 2 Add-in card 3, 12, 14, 16, 32, 50, 55, 57 Device 4, 5, 6, 13, 15, 17, 47, 48, 51, 5
2, 56, 58 Configuration space 7 Secondary side pseudo PCI bus 18 Primary side PCI interface section 19 Secondary side pseudo PCI interface section 20 Decoding section 33 Parity generation section

Claims (8)

[Claims] A configuration space of a target device interposed between a primary PCI bus and a secondary PCI bus, which is connected to the secondary PCI bus, is realized in a pseudo manner within itself. A PCI bridge device configured such that the target device appears to the primary PCI bus to have a function of one of the devices connected to the primary PCI bus. 2. Immediately after resetting, information of the target device (information such as a function number of the target device and resources required by the target device, etc.) is acquired from a configuration space of the target device, and 2. A decoding unit for associating with an IDSEL signal on a PCI bus and replacing a part of bits of information of the device at the time of reading a configuration cycle.
A PCI bridge device as described. 3. The PCI bridge device according to claim 1, wherein the PCI bridge device is a PCI bridge device for the target device having a plurality of functions, and the pseudo configuration space is realized for each of the functions. 4. The PCI bridge device according to claim 1, wherein some of the target devices are substantially provided in the device itself. 5. The PCI bridge device according to claim 1, wherein the configuration space of the target device is constituted by a register. 6. The PCI bridge device according to claim 1, wherein the configuration space of the target device is constituted by an EEPROM. 7. An add-in card accommodating the PCI bridge device according to claim 1, the secondary PCI bus, and the target device, and connected to the primary PCI bus. 8. A motherboard accommodating at least the PCI bridge device according to claim 1, the secondary PCI bus, the target device, and the primary PC bus.