JPH11274980A - Matched filter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the total scale of a matched filter circuit and also to suppress the power consumption of the circuit by preparing plural circuits which integrate the signals that are cleared, after they have been outputted once in a cycle and should secure correlation with the input signals to change their phases and hold the integrated value and sum of value to be held by themselves as the next timing and then selecting and outputting those held value in the order of phases with which the circuits secure their correlation. SOLUTION: The contents of SH(sample hold) circuits 11(1) to 11(n) of each stage are cleared once, in a cycle by a decoder 16. The signals which are inputted in each timing that is set on the basis of the clear time are defined as d1, d2,..., dn, and the signal counts which secure the correlation are defined as h1, h2,..., hn respectively. A single SH circuit has its output value S=h1d1+ fh2d2+,..., hndn after it has been cleared. Plural SH circuits where the clear timing is shifted by one to each other are prepared, and an SH circuit output value S are selectively outputted,when a cycle passed after the clearing of each SH circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a correlator used for CDMA communication and the like, and more particularly to a matched filter applicable to spread spectrum communication.

[0002]

2. Description of the Related Art Matched Filter
Is a filter used for spread spectrum communication,
A sharp peak-like output is generated for a specific signal waveform. Circuits used in this method usually require an element for delaying a signal, and when a delay element is realized by an analog element, a surface acoustic wave (SAW) element or a charge-coupled (CCD) element is used. It has been. The delay by the digital circuit is realized by using a flip-flop circuit or the like. If a delay element using an analog circuit is used, it cannot be realized by one IC.
Further, when a digital circuit is used, there is a problem that the adder becomes particularly large.

[0003]

FIG. 6 shows an example of a conventional matched filter. In the figure, 11 (1) to 11 (1) to 11
(N) is a sample-and-hold circuit (hereinafter referred to as an SH circuit), 12 (1) to 12 (n) are multipliers, 13 is an adder, and 15 is a count generator for generating a coefficient group of a signal to be correlated. Circuit. The SH circuit is based on, for example, a switched capacitor circuit, Koishi, Fujita, Masu, Tsubouchi, "Si
High Speed, Low Power Consumption Matched Filter Using Process "
Current delay flip flop described in IEICE Technical Report, SST97-50, pp.51-56, 1997.
An element such as a flip-flop circuit in a digital circuit that can hold a certain amount of state for at least one timing. In the conventional matched filter circuit, the SH circuit 11
(1) to 11 (n) are connected in cascade, and the SH
By passing the input signal from the circuit to the next stage of the SH circuit, a plurality of signals obtained by delaying the timing of the input signal from 1 to _{n {d 1, d 2,} d 3, ..., d n-1, d n ｝ (1) was obtained. .., H _n−1 , h _n } (2) The coefficient groups {h ₁ , h ₂ , h ₃ ,... And the sum is added by the adder 13 to obtain a correlation value C represented by the following equation. _{C = h 1 d 1 + h} 2 d 2 + ... + h n-1 d n-1 + h n d n (3)

However, in the conventional method, (1) there is a loss in transmission from the SH circuit to the next-stage SH circuit, so that an error occurs when a signal is transferred between the SH circuits. Since the errors accumulate everywhere when the number of stages of the SH circuit increases, there is a problem that a large error appears in the output as the entire matched filter device. Further, when the conventional matched filter circuit is entirely realized by a digital circuit, there is a problem that the circuit 13 for calculating the sum used in the matched filter circuit becomes complicated. An object of the invention according to claim 1 is to calculate the sum separately in each SH circuit, thereby eliminating the transfer of values between the SH circuits, reducing the error of the correlation value, and reducing the output of each SH circuit. Is to eliminate the necessity of a circuit for calculating the sum of the above, and to reduce the scale of the entire matched filter circuit.

The output of the matched filter circuit usually outputs a correlation peak once per cycle, and only this correlation is required for communication. Therefore, each SH circuit outputs a value at each phase of one cycle of the correlation characteristic. Therefore, the output of the correlation peak portion is substantially the same SH circuit. Accordingly, an object of the invention according to claim 2 is to estimate an SH circuit that outputs a correlation peak value, and once an SH circuit that outputs a correlation peak is estimated, an SH circuit and a peripheral circuit that are not related to the correlation peak are estimated. By stopping the power, the power consumption can be suppressed.

As described above, after detecting a correlation peak, the correlation peak itself can be output even if the number of required SH circuits is reduced. Therefore, an object of the invention according to claim 3 is to reduce the number of SH circuits used in a matched filter circuit, to further reduce power consumption, and to reduce the circuit scale.

[0007] When CDMA communication is performed in mobile communication, a fading phenomenon due to multipath may occur. This is because a direct wave that reaches the receiving station directly from the transmitting station and an indirect wave that reaches the receiving station after being reflected on a building or the like cause wave interference and weaken a received radio wave. Such fading phenomenon due to multipath can be corrected by the RAKE method in spread spectrum communication. In a matched filter, when a signal affected by multipath is received, a correlation peak for an indirect wave as well as a correlation peak for a direct wave are temporally separated and output. Therefore, an object of the invention according to claim 4 is to easily realize the RAKE method using a matched filter and to manufacture a receiver having a high demodulation capability at a low cost.

There is another method of using the plurality of matched filters used in the present invention. In the CDMA communication standard IS-95 in the United States, one code (a signal to be correlated) is used as a pilot channel, and information is transmitted in another code. An object of claim 5 is to detect a correlation peak of a pilot channel in such CDMA communication, detect a correlation peak of the pilot channel with a plurality of matched filters, and after detecting the correlation peak, A circuit is simplified by outputting a correlation peak with one matched filter and demodulating an information signal with another matched filter so that only one correlation peak detection circuit and one information demodulation circuit are required. It is.

[0009]

According to a first aspect of the present invention, an output signal is cleared after output once in one cycle, and at other timings, an input signal and a signal to be correlated with a phase change at the timing are integrated. A plurality of sample-and-hold circuits for self-holding the sum of the integrated value and the value for self-holding as a value at the next timing are provided so as to operate sequentially at the timing, and the outputs of the plurality of sample-and-hold circuits are correlated with each other. In the order of the signal phase to be taken,
This is a matched filter circuit for outputting.

According to a second aspect of the present invention, in the matched filter circuit of the first aspect, a sample-and-hold circuit that outputs a correlation peak is searched, and a sample-and-hold circuit other than the sample-and-hold circuit and an additional circuit thereof are added. This is a matched filter circuit having a function of stopping.

According to a third aspect of the present invention, in the matched filter circuit of the first aspect, the number of the sample-and-hold circuits is less than the number of phases for one cycle of the signal to be correlated, and the correlation peak A matched filter circuit that controls the phase of the signal to be correlated so as to detect

According to a fourth aspect of the present invention, there is provided a plurality of the matched filter circuits according to the third aspect, and when detecting a correlation peak, each of the plurality of matched filters has a signal of the correlation to be obtained. By obtaining correlation values at different phases of one cycle, a matched filter circuit that outputs a correlation peak is searched, and after the detection of a correlation peak, the matched filter circuit continues to detect the correlation peak and outputs another matched peak. The filter circuit is a matched filter circuit that detects a signal corresponding to a correlation peak.

According to a fifth aspect of the present invention, in the matched filter circuit according to the fourth aspect, when demodulating a code division multiplexed signal, when detecting a correlation peak, all signals which should take one correlation are detected. After the correlation peak is detected, one matched filter circuit continues to detect the correlation peak of the signal to be correlated, and the other matched filter detects another signal to be correlated. It is a matched filter circuit.

[0014]

FIG. 1 is a block diagram showing an embodiment of a matched filter circuit according to the present invention. In FIG. 1, 11 (1) to 11 (1) to 11
(N) is an SH circuit, 12 (1) to 12 (n) are multipliers,
13 (1) to 13 (n) are adders, 14 is a controller for controlling the timing of the entire matched filter circuit, 1
Reference numeral 5 denotes a coefficient generation circuit for a signal to be correlated. Also,
Reference numeral 16 denotes SH in response to a control signal from the controller 14.
A decoder for generating a timing for clearing the circuit is provided. Reference numeral 17 denotes a multiplexer for selecting one of the n inputs. Next, the operation will be described. The SH circuits 11 (1) to 11 (n) of each stage are respectively
The contents held are cleared once in one cycle. The cleared SH circuits 11 (1) to 11 (n) correlate with the input signal with respect to its own value at each timing of the phase change of the signal to be correlated until the next clearing. The signal multiplied by the coefficient of the power signal is added. In FIG. 2, reference numerals 12 (1) to 12 (n) denote multipliers which take the product of the input signal and the signal to be correlated, and 13 (1) to 13 (n)
(N) is an adder for adding a multiplier output to the contents of the SH circuit.

With respect to a certain SH circuit, an input signal at each timing with respect to a point of time when the signal is cleared is represented by Δd ₁ ,
d ₂ ,..., d _n }, and the coefficients of the signals to be correlated are {h ₁ ,
If h ₂ ,..., h _n }, the value held by the SH circuit at the first timing after clearing is h ₁ d ₁ , at the next timing h ₁ d ₁ + h ₂ d ₂ , and further at the next timing And h ₁ d ₁ +
the _{h 2 d 2 + h 3 d} 3. As described above, the input signal and the signal to be correlated are added at each timing, and after n timings, which is one cycle, the value S held by the SH circuit is: S = h ₁ d ₁ + h _{2 d 2 + ... h n-1} d n-1 + h n d n (4) next, the formula represents the same thing as the formula (3). That is, one SH circuit has a value S to be output by the matched filter circuit only once after one cycle after being cleared. Therefore, as shown in FIG. 1, a plurality of sample-and-hold circuits are provided so as to operate sequentially at the timing, and the outputs of the plurality of sample-and-hold circuits are arranged in the order of the phase that changes at the timing of the signal to be correlated. If the SH circuit is selected and output, that is, a plurality of SH circuits whose clear timing is shifted by one timing are prepared, and the SH circuit selected by the multiplexer 17 is cleared after the SH circuit is cleared. In order to select the output of the SH circuit one cycle later, the output signal of the SH circuit given by the equation (4) always appears at the output.

FIG. 2 is a schematic diagram of an output signal of a matched filter circuit. As shown in FIG. 2, normally, the output from the matched filter outputs a correlation peak once per cycle. In the example of FIG. 2, the timing T _i
, A correlation peak appears. Normally, only this correlation peak is involved in communication. On the other hand, in the case of the present invention, each of the SH circuits 11 (1) to 11 (n) calculates a correlation value at a certain phase with a signal to be correlated with the input signal. Therefore, the output signal of each SH circuit in each cycle is almost constant, and the SH circuit that outputs a correlation peak at a specific phase (here, T _i )
After the correlation for one cycle is calculated and searched, the SH circuit can be estimated as an SH circuit that outputs a correlation peak, and other output signals not related to the correlation peak become unnecessary. Therefore, the correlation portion indicated by the dotted line in FIG. 2 can be set as a pause section, and the SH circuit that is in charge of this correlation portion can be stopped.

(Section 3) If the correlation peak can be detected, the portion of the SH circuit corresponding to the idle section in the embodiment of the embodiment 2 can be reduced. . In this case, in FIG. 1, the number of SH circuits to be prepared may be smaller than the number n of timings of one cycle of correlation. When no correlation peak is detected in this matched filter circuit, the phase of the signal generated by the signal generation circuit 15 for correlating the signal is shifted, and S
Make the correlation peak appear in the H circuit. Specifically, for example, the generation timing of a signal to be correlated is set to 1
A method of shifting by two timings only once in a cycle can be considered. In addition, by controlling the signal generation circuit 15 for correlating the input signal with the input signal, the SH circuit may always follow the correlation signal so as to output the correlation peak.

(Invention of claim 4) In addition, the SH in the idle section
A circuit can be used as each branch in the RAKE scheme. FIG. 3 shows an embodiment at this time. In FIG. 3, reference numerals 31 (1) to 31 (k) denote the matched filter circuits shown in the embodiment of the third aspect of the present invention, each having the configuration shown in FIG. In the figure, 14
Denotes a controller, and 32 denotes a circuit for detecting a correlation peak (peak detection circuit). Next, the operation will be described. When detecting a correlation peak, the matched filter circuits 31 to 31
(K) is responsible for each phase of the signal to be correlated. For example, as shown in FIG. 5, the matched filter circuit 31 (1) has a section {T ₁ , T ₂ ,..., T _j1 }, and the matched filter circuit 31 (2) has a section {T _{j1 + 1} ,
One of the matched filter circuits works to calculate the correlation value at each phase to be correlated, such as up to T _{j1 + 2} ,..., T _j2 }. Thus, by searching the SH circuit of each matched filter circuit, it is possible to obtain an SH circuit that takes a correlation peak due to a direct wave.

After detecting the correlation peak due to the direct wave,
The matched filter having the SH circuit that outputs the correlation peak keeps the phase so as to output the correlation peak as it is. Other matched filters, for example, based on the matched filter that outputs the correlation peak due to this direct wave, search for the output corresponding to each correlation peak, and if such an output is found, output the value if,
A correlation peak due to an indirect wave can be output.

When detecting a correlation peak, all the matched filter circuits need to calculate a correlation using one signal to be correlated. It is not always necessary to use the signal that should take the same correlation after detecting. This is, for example, I
It can be used, for example, when communication is performed by code-dividing a plurality of channel signals, such as CDMA communication such as S-95. In the case of IS-95, the received signal is composed of one pilot channel and a plurality of information transmission channels (paging channel and traffic channel), and each channel is spread and superimposed using a signal to be correlated differently. I have. In such a case, when detecting the correlation peak, all the matched filters search the pilot channel, and after detecting the correlation peak, one matched filter continues to follow the pilot channel and the remaining matched filters are searched. The filter changes the signal to be correlated and can be used to demodulate channels in the signaling channels. In the above, the description has been made particularly with respect to circuits to be correlated. However, the matched filter of the present invention is generally applicable to other filters such as an FIR filter.

[0021]

According to the first aspect of the present invention, each S
By separately calculating the sum in the H circuit, the transfer of values between the SH circuits is eliminated, the error in the correlation value is reduced, and a circuit for summing the outputs of the SH circuits is not required. Can be reduced in size.

According to the second aspect of the invention, once the SH circuit that outputs the correlation peak is once estimated, power consumption can be suppressed by stopping the SH circuit and its peripheral circuits that are not related to the correlation peak. .

According to the third aspect of the invention, the correlation peak is detected by controlling the phase of the signal to be correlated, thereby reducing the number of required SH circuits, thereby suppressing power consumption. The circuit scale can be reduced.

According to a fourth aspect of the present invention, a plurality of matched filter circuits calculate the correlation for one round of a signal to be correlated, and after detecting a correlation peak due to a direct wave, one matched filter is used. Since the filter outputs the correlation peak due to the direct wave and the other matched filters detect the correlation peak due to the indirect wave, RAK
The E system can be easily realized, and a receiver having high demodulation capability can be manufactured at low cost.

According to a fifth aspect of the present invention, when detecting the correlation peak of the pilot channel, the correlation peak of the pilot channel is detected by a plurality of matched filters, and after detecting the correlation peak, one matched filter is detected. Since the correlation peak is output by the filter and the other matched filters demodulate the information signal, only one correlation peak detection circuit and one information demodulation circuit are required, so that the circuit can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a matched filter circuit.

FIG. 2 is a schematic diagram of an output signal in the matched filter circuit shown in FIG.

FIG. 3 is a diagram illustrating RAKE of the matched filter circuit shown in FIG. 1;
FIG. 4 is a block diagram of a circuit showing an example of use in a system.

FIG. 4 is a block diagram illustrating a configuration of a matched filter circuit illustrated in FIG. 3;

FIG. 5 is a schematic diagram of an output signal in the circuit shown in FIG.

FIG. 6 is a block diagram of a conventional matched filter circuit.

[Explanation of symbols]

11 ... SH (sample hold circuit), 12 ... multiplier,
13 adder, 14 controller, 15 controller generation circuit, 16 decoder, 17 multiplexer, 31 matched filter circuit, 32 peak detection circuit.

Claims (5)

[Claims] 1. An output signal is cleared once in one cycle and then cleared. At other timings, an input signal and a signal to be correlated, the phase of which changes at the timing, are integrated, and the sum of the integrated value and a self-held value is added. A plurality of sample and hold circuits that self-hold as a value at the next timing are provided in such a manner as to sequentially operate at the timing, and the outputs of the plurality of sample and hold circuits are selected in the order of the phase of the signal to be correlated, A matched filter circuit characterized by outputting. 2. The matched filter circuit according to claim 1, further comprising a function of searching a sample / hold circuit for an output of a correlation peak, and stopping a sample / hold circuit other than the sample / hold circuit and ancillary circuits thereof. A matched filter circuit. 3. The matched filter circuit according to claim 1, wherein the number of sample-and-hold circuits is smaller than the number of phases for one cycle of a signal to be correlated to detect a correlation peak. A matched filter circuit for controlling a phase of a signal to be correlated. 4. A plurality of the matched filter circuits according to claim 3, wherein when detecting a correlation peak, each of the plurality of matched filters has a different phase in one cycle of a signal to be correlated. By searching for a matched filter circuit that outputs a correlation peak by obtaining the correlation value in the above, after detecting the correlation peak, the matched filter circuit continues to detect the correlation peak, and the other matched filter circuits output the correlation peak. A matched filter circuit for detecting a signal according to the following. 5. The matched filter circuit according to claim 4, wherein when demodulating a code division multiplexed signal, a signal to be correlated is detected by all matched filters when a correlation peak is detected. Search and 1 after detecting the correlation peak
A matched filter circuit wherein one matched filter circuit continues to detect a correlation peak of the signal to be correlated, and the other matched filter detects another signal to be correlated.