JPH11273376A - Control circuit of voltage booster circuit and semiconductor memory device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control circuit of voltage booster circuit which enables reduction of current dissipation and improvement of data write operation rate in a semiconductor memory device. SOLUTION: The voltage booster circuits 1, 2 are connected in parallel to a load and operations of respective voltage booster circuits are controlled depending on outputs of corresponding comparing circuits 3, 4. Since different reference voltages Vref 1, 2 are applied respectively to these comparing circuits 3, 4, voltage boosting level and number of voltage booster circuits can be controlled automatically with a load condition of the voltage booster circuit. Therefore, the voltage can be impressed step by step in such a manner that a low voltage can be impressed in the former condition of write operation and a high voltage can be impressed in the latter condition thereof.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit for a booster circuit and a semiconductor memory device using the same, and more particularly to a control circuit for a booster circuit using a nonvolatile semiconductor memory such as a flash memory as a load and a semiconductor memory using the same. It concerns the device.

[0002]

2. Description of the Related Art In a nonvolatile semiconductor memory such as a flash memory, writing is performed by applying a high voltage to a memory cell. When a high voltage is applied to the memory cell at the beginning of writing, a high electric field is applied to the insulating film of the memory cell, so that the memory cell is deteriorated and the life of the semiconductor memory is shortened. Therefore, in order to avoid this, if the level of the high voltage for writing is reduced, there arises a problem that the writing speed is reduced. In order to solve these problems, it is necessary to apply a low voltage to the memory cell at the early stage of writing and a high voltage at the latter stage of writing.

In order to solve such a problem, there is a technique as disclosed in JP-A-1-89100. A conventional technique will be described with reference to FIG. In FIG. 5, the output of the booster circuit 50 is clamped by the clamp circuit 51. Here, the clamp level can be changed by turning on and off the transistor 53 by the timing control circuit 52. Therefore, by turning on the transistor 53 at the beginning of writing and turning off the transistor 53 at the latter stage of writing, A low voltage can be applied to the memory cell at the beginning of writing and a high voltage can be applied to the memory cell at the end of writing.

[0004]

However, in this circuit, since the change in the clamp level is controlled by timing, the time for changing the voltage is fixed,
When the writing speed of the memory cell varies, there is a problem that a desired effect is hardly exhibited. In addition, since all the boosting circuits are always operating, there is a problem that current consumption increases.

An object of the present invention is to provide a control circuit of a booster circuit capable of reducing current consumption and improving a writing speed, and a semiconductor memory device using the same.

[0006]

According to the present invention, there is provided a control circuit for a booster circuit in which outputs of a plurality of booster circuits are commonly connected to each other to drive a common load. An operation control of the plurality of boosting circuits is performed according to a state, thereby obtaining a control circuit.

A plurality of comparing means provided for each of the boosting circuits for comparing a supply voltage to the common load with a corresponding reference voltage; and a plurality of comparing means provided for these comparing means, And a plurality of control means for controlling the operation of the booster circuit corresponding to the result of the comparison.

Further, each of the control means controls the corresponding booster circuit to an active state when the corresponding comparison result is smaller than the reference voltage, and controls the corresponding booster circuit to an inactive state when the corresponding comparison result is larger than the reference voltage. The reference voltage is set to a plurality of different voltage values, and the supply voltage value is controlled such that the plurality of voltage values are switched stepwise according to a load state. I do.

The semiconductor memory device is characterized in that the common load is a nonvolatile semiconductor memory and the control circuit is configured as a one-chip IC together with the nonvolatile semiconductor memory and the booster circuit. can get.

The operation of the present invention will be described. A plurality of booster circuits are connected in parallel to the load, and the operation of each booster circuit is controlled according to the outputs of the plurality of comparison circuits. By supplying reference voltages of different values to these comparison circuits, the boosting level and the number of operating boosting circuits can be automatically controlled according to the load state of the boosting circuit. High high voltage can be applied stepwise.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The output CONT1 of the comparison circuit 3 is connected to the booster circuit 1 having the current capability Icp1, and the comparison circuit 3 is supplied with the reference voltage Vref1. The comparison circuit 3
The output voltage Vpump to a common load (not shown) is supplied as a comparison input of the. In the same configuration, the output of the comparison circuit 4 is connected to the booster circuit 2 having the current capability Icp2 by CONT2.
f2 is supplied. An output Vpump is supplied as a comparison input of the comparison circuit 4.

The booster circuits 1 and 2 are driven by two-phase clocks CLK1 and 2 (denoted as CLKi) which are complementary to each other. Both outputs Vpump are short-circuited and a selected memory cell in a flash memory cell array as a common load is used. Supplied to

The booster circuits 1 and 2 have a configuration as shown in FIG. That is, the transistors 11 to 15 whose gates and sources are commonly connected are connected to a power supply and a common load (Vpu
mp), and one end of each of the capacitance elements 16 to 19 is connected to the series connection point of these transistors, and the other end of each of these capacitance elements is connected to the above-described two-phase clock CLK1. , 2 to drive alternately. Since the booster circuit having such a configuration is well known, its operation is not particularly described.

Three-input NAND gates 20, 21 are provided as a control circuit for controlling the supply of these two-phase clocks CLK1, 2 to control the operation of the booster circuit.
The NAND gate 20 outputs the clock CLK1, the enable signal CPEN, and the comparison output CONTi of the comparison circuit 3 or 4.
Is supplied. In this case, the CONi “i”
Denotes the output of the comparison circuit corresponding to the booster circuit, and in the case of the booster circuit 1, the output CONT1 of the comparison circuit 3.

The NAND gate 21 is supplied with the clock CLK2, the enable signal CPEN, and the comparison output CONTi of the comparison circuit 3 or 4. In this case, CON
Ti is also the output CO of the comparison circuit 3 in the case of the booster circuit 1.
NT1.

The comparison circuits 3 and 4 have a configuration as shown in FIG. The reference voltage Vre input to the comparison circuits 3 and 4
f1 and Vref2 take different values from each other. Thus, for example, Vref1 <Vref2, and the signal CONT1 output from the comparison circuit 3 is configured to output a high level when Vpump is smaller than 5V and to output a low level when Vpump is 5V or more. The signal CONT2 output from the comparison circuit 4 is configured to output a high level when Vpump is smaller than 7V, and to output a low level when Vpump is 7V or more.

Referring to FIG. 3, voltage dividing resistors 30 and 31 are provided to divide Vpump. The divided voltage output becomes one gate input of the differential pair transistors 34 and 35 and is connected to the other gate input. A reference voltage Vrefi is supplied. “I” in this case indicates a reference voltage corresponding to the comparison circuit. In the case of the comparison circuit 3, it is Vref1.

The transistors 32 and 33 form a current mirror load circuit of the differential pair transistors 34 and 35, and a signal CONTi is derived from the drain output of the transistor 33 via an inverter 38. Note that the transistor 36 operates as a current source, and the transistor 37 is a switch element for performing on / off control of the voltage dividing operation of the voltage dividing resistor. These transistors 36 and 37 can be controlled by the enable signal CPEN.

Next, the operation of the embodiment of the present invention will be described with reference to the waveform diagram of FIG. When the enable signal CPEN, which is a high-voltage generation circuit drive signal, goes high, the two boosting circuits 1 and 2 start operating, and the boosting level Vpump increases. When Vpump is less than 5V, CONT1,
Since both CONT2 are at the high level, the two booster circuits 1 and 2 operate together. When Vpump becomes 5V, a boosted level is output to the nonvolatile memory cell.

The non-volatile memory requires a large load current at the beginning of writing as indicated by Iout, and the load current decreases as writing proceeds. When Iout is greater than Icp2, the output level of 5 V cannot be maintained unless the two booster circuits operate. At this time, by controlling only the operation of the booster circuit 1 by the signal CONT1, the output level of 5V is maintained, and the CONT2 is fixed at the high level.
When Iout becomes smaller than Icp2, the output can be maintained only by the booster circuit 2, so that CONT1 is fixed at the low level, the operation of the booster circuit 1 is stopped, and the booster circuit 2 is operated while the CONT2 remains at the high level. To 7V. Thereafter, the comparison circuit 4 and C
The operation of the booster circuit 2 is controlled by the ONT2 to maintain the output level of 7V.

The clocks CLK1 and CLK2 for driving the booster circuits 1 and 2 have a high frequency (for example, on the order of ns) and are activated to maintain the frequency (5V or 7V) at which the control signals CONT1 and 2 are turned on and off. , Repetition frequency in an inactive state; see FIG. 4). The above numerical examples are merely examples, and the number of boosting circuits is not limited to two but may be three or more.

[0023]

According to the present invention, the number of operating booster circuits can be automatically controlled according to the load condition, that is, a change in load current, so that the current consumption of all booster circuits can be reduced. There is. In addition, since the output voltage can be switched stepwise according to a change in load current and output, the high voltage applied to the memory cell at the beginning of writing can be reduced, and the high voltage applied to the memory cell in the latter half of writing can be increased. Therefore, there is also an effect that deterioration of the memory cell can be prevented, and the writing speed can be further increased.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a booster circuit.

FIG. 3 is a diagram illustrating an example of a comparison circuit.

FIG. 4 is a waveform example of each part signal showing the operation of the present invention.

FIG. 5 is a diagram showing a conventional example.

[Explanation of symbols]

 1, 2 booster circuit 3, 4 comparator circuit 11 to 15 booster transistor 16 to 19 booster capacitor element 20, 21 control NAND gate

Claims (6)

[Claims] 1. A control circuit for a booster circuit, wherein outputs of a plurality of booster circuits are commonly connected to each other to drive a common load, wherein the control circuit controls the plurality of booster circuits in accordance with a load state of the common load. A control circuit characterized by performing operation control. 2. A plurality of comparing means provided corresponding to each of the boosting circuits, for comparing a supply voltage to the common load and a corresponding reference voltage, respectively, and provided corresponding to these comparing means, 2. The control circuit according to claim 1, further comprising a plurality of control means for controlling the operation of the booster circuit corresponding to the result of the comparison. 3. The control means controls the corresponding booster circuit to an active state when the corresponding comparison result is smaller than the reference voltage, and controls the corresponding booster circuit to an inactive state when the corresponding comparison result is larger than the reference voltage. 3. The control circuit according to claim 2, wherein: 4. The method according to claim 1, wherein the reference voltage is set to a plurality of different voltage values, and the supply voltage value is controlled such that the plurality of voltage values are switched stepwise according to a load state. The control circuit according to claim 1. 5. The control circuit according to claim 1, wherein said common load is a nonvolatile semiconductor memory. 6. The semiconductor memory device according to claim 5, wherein the control circuit is configured as a one-chip IC together with the nonvolatile semiconductor memory and the booster circuit.