JPH11273342A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the time period required for lock-on by adjusting a delay amount of a variable delay circuit or the like immediately after power-on or return from a standby mode in a semiconductor storage device comprising a clock phase adjusting circuit for adjusting a phase of an external clock signal to output an internal clock signal delayed by a predetermined phase. SOLUTION: A clock phase adjusting circuit has: a delay circuit section 2 for delaying an external clock signal by a selected delay amount; a phase comparison circuit section 3 for comparing a phase of the external clock signal with a phase of a signal responding to an internal clock signal; a delay control circuit section 4 for selecting the delay amount of the delay circuit section 2 based on the phase comparison result; and a clock period measurement section 5 for measuring the delay amount for predetermined periods of the external clock signal and supplying the measured value to the delay control circuit section. During a period when the supply of the external clock signal to the phase comparison circuit section 3 is stopped, the above-mentioned delay amount is set in the delay circuit section 2 by the phase comparison circuit section 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DLL (Delay Lock) for adjusting the phase of an external clock signal supplied from the outside and outputting an internal clock signal delayed by a predetermined phase.
The present invention relates to a semiconductor device having a clock phase adjusting circuit such as an ed Loop circuit. More specifically, the present invention generates an internal clock signal delayed from the external clock signal by a predetermined period, for example, one period, and
By synchronizing the phase of data input to a random access memory (hereinafter abbreviated as DRAM) or the like with the phase of the internal clock signal, external data can be obtained regardless of variations in characteristics, ambient temperature, power supply voltage, and the like. The present invention relates to a semiconductor device having a function of always taking in and outputting data at a predetermined accurate phase with respect to a clock signal.

[0002]

2. Description of the Related Art Usually, in a semiconductor integrated circuit (LSI),
Data is input as an external input signal, a processing operation is performed in accordance with the input data, and desired data is output. Generally speaking, in general-purpose LSIs, in order to stably output desired data irrespective of variations in characteristics, fluctuations in ambient temperature, power supply voltage, and the like, it is necessary to determine which data is input externally. It is important that the same data is output at such a timing. For this reason, it is necessary to specify the timing in advance according to specifications. For example, in a DRAM, a timing at which data is output from a changing edge of an address signal, a data setup time for writing data, and the like are defined in advance together with a maximum frequency of the address signal.

In recent years, C in computer systems
With an increase in the speed of a clock signal of a PU (Central Processing Unit) or an increase in the processing speed of various other electronic circuits, it is also necessary to increase the speed of a main storage device and an interface in the CPU. Currently, the clock signal is 10
Although CPUs of 0 MHz or higher have appeared, general-purpose DRAMs widely used as main storage devices need to be operated at an access speed and a data transfer speed one digit faster than the current CPU clock signal. . So, 100
Various new DRAMs have been proposed, such as a synchronous DRAM (usually abbreviated as SDRAM), which enables a data transfer rate of MHz or higher.

In a new DRAM such as an SDRAM operating at such a high speed, it is necessary to always input and output data at a predetermined accurate phase with respect to a high-speed external clock signal input from the outside. . For this reason, usually, a clock phase adjustment circuit such as a DLL circuit having a function of accurately adjusting the phase of an external clock signal and generating an internal clock signal is provided in a DRAM, and an internal clock generated by the clock phase adjustment circuit is provided. The phase of the clock signal and DR
The phase of the data input to the AM is synchronized.

FIG. 21 is a circuit block diagram showing a configuration of a semiconductor device having a conventional clock phase adjusting circuit having the above functions. The conventional clock phase adjustment circuit as shown in FIG. 21 generates an internal clock signal delayed by a predetermined phase by changing the delay amount of an external clock signal CLK input from the outside via an input buffer 800. Variable delay circuit 21 for
0 and the second variable delay circuit 220, the phase of the external clock signal CLK,
A phase comparison circuit 300 for comparing the phase of a signal inputted from the dummy data output buffer 290 and the dummy input buffer 280 via the dummy data output buffer 290 and the dummy input buffer 280;
And a delay control circuit 400 for selecting the amount of delay of the first and second variable delay circuits 210 and 220 based on the result of the phase comparison by 00.

More specifically, after the external clock signal CLK is amplified to a predetermined level by the input buffer 800, the first variable delay circuit 21
The signal is supplied to the zero and second variable delay circuit 220 and is also supplied to the phase comparison circuit 300 as a first input signal. In this case, a dummy input buffer 280 is provided on the input side of the phase comparison circuit 300 in order to cancel the phase delay of the external clock signal CLK caused by the input buffer 800. Further, the first variable delay circuit 21
0, a data output buffer 90 for taking in and outputting data DATA in synchronization with the internal clock signal generated by
A dummy data output buffer 290 is provided to cancel the phase delay of the internal clock signal due to 0. Therefore, the external clock signal CLK input to the second variable delay circuit 220 is supplied as a second input signal to the phase comparison circuit 300 via the dummy data output buffer 290 and the dummy input buffer 280.

The phase comparison circuit 300 compares the phase of the first input signal with the phase of the second input signal, and inputs the result of the comparison between the phases of the two input signals to the delay control circuit 400. The delay control circuit 400 controls the first and second variable delay circuits 210 and 220 so that the phase difference between the external clock signal CLK and the internal clock signal is equal to a predetermined period, for example, one period (360 degrees).
Select and adjust the delay amount. As a result, the external clock signal CLK input to the first variable delay circuit 210
Is supplied to the data output buffer 900 after being given the delay amount adjusted by the delay control circuit 400. The data output buffer 900 takes in the data DATA in synchronization with the internal clock signal supplied from the first variable delay circuit 210, and outputs it as an output signal OUT to the outside.

[0008]

In a conventional semiconductor device having a clock phase adjusting circuit, the phase difference between the external clock signal and the internal clock signal becomes a predetermined period, for example, 360 degrees (that is, lock-on). 1) and the second variable delay circuit 21
By changing the delay amount of 0, 220 step by step,
The delay amount of the external clock signal was adjusted. When the DRAM or the like is in the normal operation mode, that is, when it is in the active state, the variation in the cycle of the external clock signal due to variations in characteristics and changes in the power supply voltage and the ambient temperature is small. There is no problem even if the phase of the external clock signal is adjusted by the method of changing one step at a time. However, in the following cases (1) and (2), a lot of time is required to set the delay amount necessary for lock-on, and until the actual operation such as data writing / reading is started. This leads to an increase in the time of the operation. (1) At power-on At power-on, the delay amount of the variable delay circuit is reset to an initial state, and then the phase of the external clock signal is adjusted. For this reason, it takes a lot of time for the variable delay circuit to enter the lock-on state. (2) When switching the operation mode, for example, when returning from the standby mode When the DRAM or the like is in the standby mode, the clock frequency of the external clock signal is reduced or the power supply voltage is reduced in order to reduce power consumption. Therefore, the delay amount of the variable delay circuit greatly deviates from the delay amount set in the normal active state. For this reason, when returning from the above-mentioned standby mode, it takes much time for the variable delay circuit to enter the lock-on state.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and can be applied to a variable delay circuit or the like even when a DRAM or the like is not in a normal operation mode, such as when power is turned on or when returning from a standby mode. It is an object of the present invention to provide a semiconductor device capable of shortening the time required for adjusting the delay amount and bringing it into the lock-on state as compared with the related art.

[0010]

FIG. 1 is a block diagram showing the principle configuration of the present invention. Here, the configuration of a semiconductor device having a phase adjustment circuit is simplified.
In order to solve the above problems, the semiconductor device of the present invention
As shown in FIG. 1, there is provided a clock phase adjusting circuit 1 for adjusting the phase of an external clock signal CLK supplied from the outside and outputting an internal clock signal.

The clock phase adjusting circuit 1 can select a delay amount of the external clock signal CLK (or the first clock input signal CLK1), and delays the external clock signal CLK by the selected delay amount. A delay circuit section 2 for outputting the internal clock signal, a phase comparison circuit section 3 for comparing the phase of the external clock signal CLK with a signal responsive to the internal clock signal, and a phase comparison by the phase comparison circuit section 3. Based on the result, a delay control circuit unit 4 for selecting the delay amount of the delay circuit unit 2 and a delay amount corresponding to a predetermined period of the external clock signal CLK are measured. And a clock cycle measuring unit 5 to be supplied to the delay control circuit unit 4.

Here, the delay control circuit section 4 controls the delay corresponding to a predetermined period of the external clock signal CLK during the period when the supply of the external clock signal CLK to the phase comparison circuit section 3 is stopped. The amount of the delay circuit part 2
Is set to. Preferably, in the semiconductor device of the present invention, the external clock signal C is supplied to the phase comparison circuit unit 3 only for a predetermined period from when the power of the semiconductor device is turned on.
A clock phase adjusting circuit control unit for stopping supply of LK and supplying a delay amount measurement result corresponding to a predetermined period of the external clock signal to the delay control circuit unit; I have.

Still preferably, in a semiconductor device according to the present invention, supply of the external clock signal CLK to the phase comparison circuit section 3 is stopped for a predetermined period from a time when the operation mode of the semiconductor device is switched, and Clock signal C
A clock phase adjustment circuit control unit 6 is provided that enables the measurement result of the delay amount corresponding to a predetermined period of LK to be supplied to the delay control circuit unit 4.

More specifically, in FIG. 1, a clock input circuit 8 having substantially the same function as the conventional input buffer 800 (FIG. 21) is provided on the input side of the clock phase adjustment circuit 1. On the other hand, on the input side of the clock phase adjusting circuit 1, a data output circuit 9 having substantially the same function as the conventional data output buffer 900 (FIG. 21) is provided. While the external clock signal CLK is being supplied to the phase comparison circuit unit 3, the external clock signal CLK is amplified by the clock input circuit 8 until it reaches a predetermined level, and the first clock input signal CL
Output as K1. This first clock input signal C
LK1 is supplied to the delay circuit unit 2 in the clock phase adjustment circuit 1 and the clock phase adjustment circuit control unit 6
Is supplied to the phase comparison circuit section 3 as one input signal (for example, the second clock input signal CLK2).

Here, the external clock signal CLK from the clock input circuit 8 is provided on the input side of the phase comparison circuit section 3.
A dummy input circuit section 18 is provided to cancel the phase delay of. Further, a dummy output circuit section 19 is provided to cancel the phase delay of the internal clock signal by the data output circuit 9. Therefore, the first clock input signal CLK1 input to the delay circuit unit 2
Are the dummy output circuit section 19 and the dummy input circuit section 18
Is supplied to the phase comparison circuit section 3 as the other input signal. The phase comparison circuit 3 compares the phases of the two input signals, and inputs the result of the phase comparison between the two input signals to the delay control circuit unit 4.

More preferably, the semiconductor device of the present invention adjusts the phase of the external clock signal CLK based on the measurement result of the delay amount by the clock cycle measuring unit 5 immediately after the power supply of the semiconductor device is turned on. Then, the phase of the external clock signal CLK is adjusted based on the result of the phase comparison by the phase comparison circuit section 3.

Still preferably, in a semiconductor device according to the present invention, immediately after the semiconductor device returns from the standby mode, the phase of the external clock signal CLK is determined based on the measurement result of the delay amount by the clock cycle measuring circuit 5. After the adjustment, the phase of the external clock signal CLK is adjusted based on the result of the phase comparison by the phase comparison circuit unit 3.

In other words, in the semiconductor device of the present invention, a clock phase adjusting circuit control unit 6 and a clock cycle measuring unit 5 are newly provided. The clock phase adjustment circuit control unit 6 controls the semiconductor device for a certain period of time after power-on, or for a certain period of time after switching the operation mode of the semiconductor device, such as immediately after returning from the standby mode.
The supply of the external clock signal CLK to the delay circuit unit 2 and the phase comparison circuit unit 3 is stopped, and the external clock signal CL is stopped.
The clock cycle measuring control signal Ss synchronized with K is supplied to the clock cycle measuring unit 5. The clock cycle measurement control signal Ss indicates a start signal START indicating the start of measurement of a delay amount corresponding to a predetermined period of the external clock signal as shown in FIG. A stop signal STOP, a gate signal GATE for transmitting the measurement result of the delay amount to the delay control circuit unit 4, and the like are included. The power-on timing of the semiconductor device or the switching timing of the operation mode of the semiconductor device is notified to the clock phase adjustment circuit control unit 6 such as a DLL control circuit by a control signal Sc.

In addition, the clock cycle measuring unit 5 responds to the above-described clock cycle measuring control signal Ss for a certain period of time after power-on of the semiconductor device or for a certain period of time after switching the operation mode of the semiconductor device. The delay amount corresponding to a predetermined period, for example, one period, is measured, and the measurement result of the delay amount is transmitted to the delay control circuit unit 4.
To supply. Further, the delay control circuit unit 4 sets a delay amount corresponding to one cycle of the external clock signal in the delay circuit unit 2. Clock period measurement unit 5 and clock phase adjustment circuit control unit 6 as described above
By the operation described above, the delay amount of the delay circuit unit can be set near the delay amount required for lock-on of the variable delay circuit or the like of the delay circuit unit immediately after power-on or immediately after switching the operation mode of the semiconductor device. .

Thus, according to the present invention, even when the DRAM or the like is not in the normal operation mode, such as when the power is turned on or when the DRAM is returned from the standby mode, the variable delay circuit and the like are required to be locked on. The required time can be greatly reduced as compared with the conventional case.

[0021]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
A preferred embodiment of the present invention (hereinafter, referred to as an example) will be described with reference to FIG. However, here, the configuration and operation of the SDRAM to which the embodiment of the present invention is applied will be described first so that the configuration and features of the preferred embodiment of the present invention can be easily understood.

FIG. 2 is a block diagram showing a schematic configuration of a synchronous DRAM to which the semiconductor device of the present invention is applied. FIG. 3 is a timing chart for explaining the operation of the synchronous DRAM of FIG. is there. The semiconductor chip composed of a synchronous DRAM (SDRAM) shown in FIG. 2 has a plurality of banks (for example, banks No. 0 and No. 1) for forming a memory area in the chip.
048 bits × 2048 bits DRAM core 108
a, 108b and these DRAM cores 108a, 10b
Control signal latch 105 holding various control signals (row address control signal RAS, column address signal CAS, and write enable signal WE) to be supplied to 8b.
a and 105b, a mode register 106 for specifying an operation mode of the SDRAM, and column address counters 107a and 107b for counting column addresses and accessing data.

Further, the semiconductor chip shown in FIG. 2 uses the synchronous DR based on the clock enable signal CKE.
A clock buffer 101 for holding a clock signal (ie, an external clock signal) CLK serving as a reference for operating the AM and supplying the clock signal to another circuit unit, and various command signals (a chip select signal / CS, a row address) Select signal / RAS, column address select signal /
CAS and write enable signal / WE) and supply them to control signal latches 105a, 105b and mode register 106.
Memory address signals A0 to A10 including a row address and a column address, and a bank address signal A
11, the mode register 106, the column address counters 107a and 107b, and the DRAM core 108
a, 108b, and various data DQ (DQ0).
To DQ7 and DQM) and the I /
I / O data buffer / register 104 to be supplied to O section
And

Further, in FIG. 2, various commands are inputted by command signals such as a chip select signal / CS, a row address select signal / RAS, a column address select signal / CAS, and a write enable signal / WE in combination. Thus, the operation mode is determined. These various commands are
It is decoded by the command decoder 102 and controls each circuit according to the operation mode. On the other hand, the above-mentioned chip select signal / CS, row address select signal / RAS, column address select signal / CAS, and write enable signal / WE are controlled by control signal latch 1
05a and 105b are also input, and the state of the current command signal is latched until the next command is input.

Further, in FIG. 2, memory address signals A0 to A10 and bank address signal A11
Are amplified by the address buffer 103 and used as load addresses of the respective banks, and also used as initial values of the column address counters 107a and 107b. The signals read from the DRAM cores 108a and 108b are amplified by the I / O data buffer / register 104, and externally input from an external clock signal CL
It is output in synchronization with the rise of K. A similar operation is performed for data input, and data input to I / O data buffer / register 104 is stored in DRAM core 108.
a, 108b.

In the timing chart shown in FIG. 3, various control signals are input to the DRAM core in synchronization with the rise of the external clock signal CLK in the part (a) (shown in the part (b)). Is read out. In this case, first, a row address (Row Address) of a memory matrix in the DRAM core is selected, and after a predetermined delay time (corresponding to a later-described row address access time tRCD) elapses, a column address (Column Address) is obtained. Is selected to start the data read operation.

More specifically, when data is read from the SDRAM, an active (ACT) command is input to a command terminal from a combination of the various command signals described above, and a row address signal is input to an address terminal. When such a command and a row address are input, the SDRAM is activated, selects a word line corresponding to the row address, outputs cell information on the selected word line to the bit line, and then outputs a signal to the sense amplifier. Amplify at On the other hand, after the operation time (row address access time tRCD) of the portion related to the access of the row address has elapsed, the read command (REA)
D) and the column address. According to the column address, the data of the selected sense amplifier is output to the data bus line, then amplified by the data bus amplifier, and further amplified by the output buffer to output data DQ to the output terminal ((c)). Section).

These series of operations are exactly the same as those of a general-purpose DRAM. However, in the case of an SDRAM, a circuit related to a column address performs a pipeline operation. It is output continuously for the cycle. Thereby, the data transfer cycle becomes equal to the cycle of external clock signal CLK. SDR
There are three types of access times in AM, all of which are defined with reference to the rising point of the external clock signal CLK. In FIG. 3, tRAC is a row address access time indicating an operation time of a portion related to a row address access, tCAC is a column address access time indicating an operation time of a portion related to a column address access, t
AC indicates a clock access time indicating a time delay from the external clock signal CLK to data output. When using the above SDRAM in a high-speed memory system,
Although tRAC and tCAC indicating the time from when a command is input to when data is first obtained are also important, the clock access time tA is required to increase the data transfer speed.
C is also important.

Further, in FIG. 3, tOH indicates the output data holding time for the previous cycle or the next cycle. In consideration of the variation in the characteristics of the SDRAM, the temperature dependency, and the power supply voltage dependency, tAC and tOH do not coincide with each other, and thus have a certain time width. In the time corresponding to this time width, the data to be output from the output terminal is indeterminate. As described above, the time when the data is indeterminate, that is, the data indefinite time means a time when it is not known what data is output, and is a time that cannot be used in the memory system. .

The above data indefinite time tends to fluctuate due to variations in the characteristics of the SDRAM and changes in temperature, power supply voltage and the like. Even in such a case, in order to output data at an accurate timing without error, data is always output at a predetermined phase with respect to the external clock signal CLK, that is, the clock access time tAC
Is required to be always constant. For example, when it is desired that the output of data is performed in synchronization with the rise of the internal clock signal, the phase difference between the external clock signal CLK and the internal clock signal is always equal to a predetermined period, for example, three.
The clock phase adjustment circuit (FIG. 1) is held at 60 degrees.
It is necessary to set the delay amount of the delay circuit section (see FIG. 1).

FIG. 4 is a block diagram showing the configuration of one embodiment of the present invention. Hereinafter, the same components as those described above will be denoted by the same reference numerals. In the embodiment shown in FIG. 4, as the clock phase adjusting circuit 1 (see FIG. 1) of the present invention, the delay amount (phase) of the external clock signal CLK supplied from the outside is adjusted and the phase for a predetermined period is always adjusted. A DLL circuit 10 that outputs an internal clock signal delayed only by a predetermined time is provided.

The DLL circuit 10 serves as the above-described delay circuit section 2 (see FIG. 1).
Variable delay circuit for generating an internal clock signal delayed by a predetermined phase by changing the amount of delay of an external clock signal CLK (ie, first input clock signal CLK1) input through 21 and a second variable delay circuit 22 are provided. Further, the DLL circuit 10 includes the above-described phase comparison circuit unit 3 (FIG. 1).
And the phase of the external clock signal CLK,
A phase comparison circuit 30 for comparing the phase of a signal input from the second variable delay circuit 22 via the dummy data output buffer 29 and the dummy input buffer 28 is provided.

Further, the DLL circuit 10 serves as the above-described delay control circuit section 4 (see FIG. 1) based on the result of the phase comparison by the phase
The delay control circuit 40 for selecting the delay amount of the variable delay circuits 21 and 22 is provided. Further, the DLL circuit 10 serves as the above-described clock cycle measuring unit 5 (see FIG. 1) to supply the external clock signal CLK to the phase comparator 30.
While the supply of the (second clock input signal CLK2) is stopped, a delay amount corresponding to a predetermined period of the external clock signal CLK is measured, and the measurement result of the delay amount is sent to the delay control circuit 40. A clock cycle measuring circuit 50 to be supplied is provided.

Further, in the embodiment shown in FIG. 4, the clock adjustment circuit control unit 6 (see FIG. 1) is
The supply of the second clock input signal CLK2 to the phase comparison circuit 30 is stopped for a predetermined period from when the power of the semiconductor device such as the RAM is turned on or when the operation mode is switched, and the clock cycle measurement circuit 50 sends the delay control circuit 40 A DLL control circuit 60 is provided to enable the supply of the measurement result of the delay amount to the above. The DLL control circuit 60 generates a second clock input signal CLK2 based on the first clock input signal CLK1 supplied from the input buffer 80, and supplies the second clock input signal CLK2 to the phase comparison circuit 30 as one input signal. On the other hand, when the power-up signal Spo indicating that the semiconductor device is turned on or the power-down return signal Spr indicating that the semiconductor device has returned from the standby mode is input to the DLL control circuit 60, the second clock input signal C
The supply of the LK2 to the phase comparison circuit 30 is stopped, and the start signal START indicating the start of the measurement of the delay amount, the stop signal STOP indicating the end of the measurement of the delay amount, and the measurement result of the delay amount are transmitted to the delay control circuit 40. Is supplied to the clock cycle measuring circuit 50.

Further, in the embodiment shown in FIG. 4, the input buffer 80 having almost the same function as the conventional input buffer 800 (see FIG. 21) and the same as the conventional data output buffer 900 (see FIG. 21). A data output buffer 90 having a function is provided. In this case, the input buffer 8 is provided on the input side of the phase comparison circuit 30.
A dummy input buffer 28 is provided on the output side of the second variable delay circuit 22 in order to cancel the phase delay of the external clock signal CLK due to 0. On the other hand, a dummy data output buffer 29 is provided on the output side of the second variable delay circuit 22 in order to cancel the phase delay of the internal clock signal by the data output buffer 90.

Dummy input buffer 28 and dummy data output buffer 29 have substantially the same functions as conventional dummy input buffer 280 and dummy data output buffer 290, respectively. Therefore, the external clock signal C input to the second variable delay circuit 220
LK is supplied to the phase comparison circuit 30 via the dummy data output buffer 29 and the dummy input buffer 28 as the other input signal. This phase comparison circuit 3
“0” compares the phases of the two input signals, and inputs the phase comparison result of these input signals to the delay control circuit 40.

In FIG. 4, when a semiconductor device such as a DRAM is in a normal operation mode, the DLL circuit 10 according to the embodiment of the present invention performs the same operation as the conventional phase adjustment circuit shown in FIG. Do. In such a normal operation mode, the external clock signal CLK is amplified by the input buffer 80 and supplied to the first variable delay circuit 21 and the delay control circuit 40 as the first clock input signal CLK1.

The first control signal supplied to the DLL control circuit 40 is
Is supplied to the second variable delay circuit 22 and, at the same time, is supplied to the in-phase comparison circuit 30 as one input signal of the phase comparison circuit 30 (the second clock input signal CLK2). On the other hand, the first clock input signal CLK1 supplied to the first variable delay circuit 21 has the same phase as the other input signal of the phase comparison circuit 30 via the dummy data output buffer 29 and the dummy input buffer 28. It is supplied to a comparison circuit. Here, the phase comparison circuit 30 compares the phases of the two input signals, and outputs the result of the phase comparison to the delay control circuit 40.

The delay control circuit 40 controls the delay amounts of the first variable delay circuit 21 and the second variable delay circuit 22 according to the phase comparison result supplied from the phase comparison circuit 30. As a result, the first delay circuit 21
Is supplied to the data output buffer 90 after the delay amount adjusted by the delay control circuit 40 is given to the first clock input signal CLK1. The data output buffer 90 receives the first clock input signal CL to which the delay amount adjusted by the delay control circuit 40 has been added.
K1, that is, the data DATA is fetched in synchronization with the internal clock input signal and output to the outside as an output signal OUT.

Next, referring to FIG. 4, the operation immediately after turning on the power of the semiconductor device such as the DRAM or the operation immediately after returning from the standby mode will be described. When the power of the semiconductor device is turned on, the power supply start-up signal Spo goes to a high voltage level (“H (High)” level). When the semiconductor device returns from the standby mode, the power-down return signal Spr goes to the “H” level. . At this time, as will be described later, the second clock input signal CLK2 is at a low voltage level (“L (Low)” level) for a certain period, and the external clock signal is applied to the second variable delay circuit 22 and the phase comparison circuit. No longer supplied to 40.

While the supply of the external clock signal to the second variable delay circuit 22 and the phase comparison circuit 40 is stopped, the start signal START, the stop signal STOP, and the start signal SYNC synchronized with the first clock input signal CLK1. The gate signal GATE is supplied to the clock cycle measuring circuit 50.
Supplied to The clock cycle measuring circuit 50 uses the start signal START, the stop signal STOP, and the gate signal GATE to generate one of the external clock signals.
The delay amount for the cycle is measured, and the measurement result thus obtained is output to the delay control circuit 40. The delay control circuit 40 selects the delay amounts of the first variable delay circuit 21 and the second variable delay circuit 22 in accordance with the measurement result, and adjusts the delay amount in the vicinity of the delay amount required to lock on the variable delay circuits. Is set to the delay amount. afterwards,
The supply of the external clock signal CLK to the second variable delay circuit 22 and the phase comparison circuit 30 starts. The subsequent operations of the DLL circuit and the like are the same as the operations in the above-described normal operation mode.

In summary, in an embodiment of the present invention, DRA
When the semiconductor device such as the DRAM is not in the normal operation mode, such as immediately after turning on the power of the semiconductor device such as the M or immediately after returning from the standby mode,
In the first first cycle, the external clock signal 1
There is provided a means (for example, a clock cycle measuring circuit 50) for measuring the length of the clock cycle at a stretch by measuring the length of the cycle. By using such means, the delay circuits of the first and second variable delay circuits 21 and 22 are not changed step by step, and the delay circuit section is placed near the delay amount required for lock-on of the variable delay circuit. The delay amount can be set quickly. After the next cycle, by supplying an external clock signal to the phase comparison circuit 30, the delay amount of the delay circuit section is changed one step at a time to adjust the phase of the internal clock signal more accurately, and the variable delay circuit is locked on. State.

Therefore, according to an embodiment of the present invention, D
Even when a semiconductor device such as a RAM is not in a normal operation mode, it is possible to significantly reduce the time required for setting the delay amount of the variable delay circuit to the lock-on state. FIG. 5 is a circuit diagram showing one configuration example of the DLL control circuit of FIG. 4. FIGS. 6 and 7 are timing charts (parts 1 and 2) for explaining the operation of the DLL control circuit of FIG. It is.

As shown in FIG. 5, the main part of the DLL control circuit 60 (FIG. 4) according to the embodiment of the present invention includes a power-on signal Spo indicating that the power is turned on, or a return from the standby mode. D flip-flops 7 # 1- # 6 for generating a start signal START, a stop signal STOP, and a gate signal GATE in response to a change in the voltage level of the power-down return signal Spr (For example, six D flip-flops) and a second clock input signal CLK2 according to a change in the voltage level of the power-on signal Spo or the power-down return signal Spr.
And a seventh D flip-flop 7 # 7 for deciding whether or not to supply to the phase comparison circuit 30.

In the timing chart of FIG. 6, when the power is turned on, an "H" level power supply rising signal Spo (node N11) is supplied to the node N8 via the NOR gate 61. Alternatively, when returning from the standby mode, the power-down return signal Spr (node N
12) is supplied to the node N8 via the NOR gate 61. At this time, the two NAND elements 6
The output side (node N1) of the RS flip-flop composed of 1 and 62 becomes "H" level and is supplied to the first D flip-flop 7 # 1. At the time of power-on, the power-on signal Spo (node N1
Until 1) is supplied, the state of the output side (node N1) of the RS flip-flop may not be determined.

In this embodiment, by grounding the node N1 via the capacitor 63c, the node N1 is kept at "L" level until the power supply start signal Spo (node N11) is supplied. In the first D flip-flop 7-1, as shown in FIG. 4, a first clock input signal CL corresponding to the external clock signal CLK is provided.
An "H" level signal is output to the second D flip-flop 7-2 in synchronization with K1 (node N2). In addition, the second to the second D flip-flops
Similarly, the sixth D flip-flops 7-2 to 7-6 output an "H" level signal to the subsequent stage in synchronization with the first clock input signal CLK1 (nodes N3 to N6).
At this time, the second to fourth D flip-flops 7-2 to 7-
Signal output from 7-4 (nodes N3 to N5)
7, a start signal START, a stop signal STOP, and a gate signal G having signal waveforms as shown in FIG.
ATE is generated, respectively, and the clock cycle measuring circuit 50
Supplied to In this case, the start signal START is
The stop signal STOP output through the NAND gate 70 and the inverter 71 is output from the NAND gate 72
And output via an inverter 73. further,
The gate signal GATE is supplied to three inverters 75 and 76.
And 77, and output via a NAND gate 78 and an inverter 79.

The "H" level signal output from the sixth flip-flop 7-6 becomes the "L" level signal via the inverter 64 (node N7), and is applied to the reset input side of the RS flip-flop circuit. Supplied. As a result, the output side (node N1) of the RS flip-flop circuit goes to "L" level. The signals at the nodes N1 and N7 are supplied to the seventh D flip-flop 7- via the NAND gate 66 and the inverter 67.
7 (node N9). The seventh D flip-flop 7-7 synchronizes with the inverted signal (/ CLK1) of the first clock input signal CLK1 generated by the inverter 65 and outputs the inverted output terminal (/ CLK1).
Q) to output an “L” level signal (node N1).
0). This "L" level output signal (node N10) and first clock input signal (CLK1)
The signal is supplied to the second variable delay circuit 22 and the phase comparison circuit 30 via the gate 68 and the inverter 69 as the second clock input signal CLK2 (FIG. 7). When the signals at the nodes N1 and N7 are at the "H" level, the output signal (node N10) of the seventh D flip-flop 7-7 goes to the "L" level, and the second clock input signal CLK2 (FIG. 7) Is output (the signal pulse of the first clock input signal CLK1 in FIG. 6). That is, the external clock signal is not supplied to the second variable delay circuit 22 and the phase comparison circuit 30 for a certain period immediately after turning on the power or immediately after returning from the standby mode.

FIG. 8 is a circuit diagram showing an example of the configuration of the clock cycle measuring circuit of FIG. 4. FIGS.
5 is a timing chart (No. 1 and No. 2) for explaining the operation of the clock cycle measuring circuit of FIG. As shown in FIG. 8, the main part of the clock cycle measuring circuit 50 (FIG. 4) according to the embodiment of the present invention has a basic structure having a delay amount corresponding to the sum of the delay amounts of the dummy input buffer and the dummy data output buffer. A delay circuit 25, a multi-stage delay circuit for counting a delay amount corresponding to one cycle of an external clock signal based on a start signal START and a stop signal STOP supplied from a DLL control circuit 60, and a plurality of transfer gates And the gate signal GATE
And a latch circuit including a transfer gate for holding the counted amount of delay.

In FIG. 9, as described above, the DRA
For a certain period from power-on of the semiconductor device such as M or return from the standby mode, the start signal START, the stop signal STOP, and the gate signal GATE generated by the DLL control circuit 60 are applied to the first clock input signal. It is supplied to the clock cycle measuring circuit 50 in synchronization.

Here, the start signal START propagates through the basic delay circuit 25 to a delay circuit group of a plurality of stages (n stages, where n is an arbitrary positive integer) each including a NAND gate and an inverter. (Node N1
0, node N20, node N40, node Nn
0). The delay amount of the basic delay circuit 25 corresponds to the sum of the delay amounts of the dummy input buffer 28 and the dummy data output buffer 29 in FIG. More specifically, the first-stage delay circuit group includes two NAND gates 50-1, in addition to the delay amount of the basic delay circuit 25.
50-3 and two inverters 50-2, 50-
4 has a delay amount. Further, the second-stage delay circuit group includes the delay amount due to the NAND gate 50-5 and the inverter 50-6, and the third-stage delay circuit group includes the NAND gate 50-7 and the inverter 50-8.
And the delay circuit group of the fourth stage is NAN
Includes delay due to D-gate 50-9 and inverter 50-10. Similarly, the delay circuit group at the n-th stage includes the NAND gate 50-n-4 and the inverter 5
Includes the delay amount due to 0-n-3.

The amount of delay per stage of the digital circuit group of a plurality of stages is equal to the amount of delay of one stage of the first variable delay circuit 21 and the second variable delay circuit 22 in FIG. The details of the circuit configuration of these variable delay circuits will be described later with reference to FIG. Signals that have passed through the nodes N10, N20,..., Nn0) shown in FIG. 10 are transferred to a plurality of transfer gates 5-1 to 5-n- connected respectively to these nodes N10 to Nn0.
5 and held by a plurality of latch circuits (node N
11, node N21, node N41, node Nn
1).

The first-stage latch circuit of the plurality of latch circuits has a pair of inverters 50-14, 50-15 connected in parallel so as to have opposite polarities, and outputs from the pair of inverters. Inverter 50 # 16 for inverting a signal and transfer gate 5-6 connected to inverter 50 # 16 (node N
11). Further, a second-stage latch circuit of the plurality of latch circuits includes a pair of inverters 50-17 and 50-18 connected in parallel so as to have opposite polarities, and a signal output from the pair of inverters. , And a transfer gate 5-7 connected to the inverter 50 # 19 (node N21).

Further, a third-stage latch circuit of the plurality of latch circuits includes a pair of inverters 50-20 and 50-21 connected in parallel so as to have opposite polarities.
An inverter 50 # 22 for inverting a signal output from the pair of inverters;
# 22 and a transfer gate 5-8 (node N31). Furthermore, a fourth-stage latch circuit of the plurality of latch circuits includes a pair of inverters 50-23 and 50 connected in parallel so as to have opposite polarities.
-24, an inverter 50 # 25 for inverting a signal output from the pair of inverters, and a transfer gate 5-8 connected to the inverter 50 # 25 (node N41). Similarly, the n-th latch circuit of the plurality of latch circuits is connected to the inverter 50
-N-2, 50-n-1 and 50 @ n-1 and a transfer gate 5 connected to the inverter 50 # 25
−n (node N41).

Further, in FIG. 8, the n-th transfer gate 5-n-5 of the plurality of transfer gates is connected to the first-stage transfer gate 5-1 via the inverter 50-13. ing. Further, the n-th transfer gate 5-n in the plurality of latch circuits is connected to the first-stage transfer gate 5-6 via the inverter 50-26.

In FIG. 9, the stop signal STOP is
From the start signal START to the first clock input signal C
Transfer gate 5-1 supplied with a delay of one cycle of LK1 and connected to each of nodes N10 to Nn0
Close ~ 5-n-5. In this embodiment, FIG. 9 and FIG.
As shown at 0, since the start signal START has propagated to the node N30 when the stop signal STOP is supplied, the delay amount corresponding to one cycle of the external clock signal is regarded as four stages of the delay circuit group. It is. After closing the transfer gates 5-1 to 5-n-5, the nodes N11 to N31 are held at the "H" level by the corresponding latch circuits, respectively. It is kept at L "level.

On the other hand, the gate signal GATE is
As shown in FIG. 10 and FIG. 10, the signal is supplied two cycles of the first clock input signal CLK1 from the start signal START and one cycle after the stop signal STOP.
The transfer gates 5-6 to 5-n connected to the respective nodes 11 to Nn1 are temporarily set in a passing state. The signal passing through each of these transfer gates 5-6 to 5-n is supplied to delay control circuit 40 (node N1).
ノ ー ド node Nn1).

Next, in the semiconductor device according to the embodiment of the present invention, specific circuit configurations and operations of components other than the DLL control circuit and the clock cycle measuring circuit will be described. Here, a specific circuit configuration and operation waveforms of the first and second variable delay circuits, the delay control circuit, and the phase comparison circuit in the DLL circuit 10 will be described.

FIG. 11 is a diagram showing a circuit configuration and operation waveforms of the variable delay circuit of FIG. More specifically,
FIG. 11A shows a 1-bit delay circuit in each of the first variable delay circuit 21 and the second variable delay circuit 22 shown in FIG. 4 (hereinafter, simply referred to as a variable delay circuit). (2) of FIG. 11 shows a timing chart for explaining the operation of the delay circuit for one bit, and (3) of FIG.
This shows a circuit configuration when a plurality of delay circuits of one bit are connected.

As shown in FIG. 11A, the one-bit delay circuit includes two NAND circuits 201 and 202,
And an inverter 203. The operation of the one-bit delay circuit will be described with reference to (2) of FIG. 11. One input signal .phi.E is an activation signal, and the delay circuit operates when it is at "H" level (the level of the power supply voltage Vcc). . FIG. 11 (2) shows a state in which the input signal φE goes to the “H” level and the signal can be accepted. Signal IN
Indicates another input signal to the 1-bit delay circuit,
φN indicates a signal from the adjacent right side connected in a plurality of stages, OUT indicates an output signal of a 1-bit delay circuit, and 2a-1 and 2a-2 correspond to the delay circuit in FIG. 11A. 5 shows operation waveforms of internal terminals (2a-1 and 2a-2). Therefore, OUT becomes the signal φN to the left.

When signal φN is at "L" level, output signal OUT is always at "L" level. When signal φN is at “H” level and input signal φE is at “L” level, output signal OUT is at “H” level. When signal φN is at “H” level and input signal φE is at “H” level,
When the input signal IN is at "L" level, the output signal OUT is at "H" level, and when the input signal IN is at "H" level, it is at "L" level. FIG. 11 (2) shows that φE =
In the state of “H”, φN = “H”, the input signal IN is “L”
When the signal rises from the "H" level to the "H" level, the input signal IN is transmitted to the output side as the output signal OUT while being inverted by the NAND gates 201 and 202 and the inverter 203.

FIG. 11 (3) shows an example in which the delay circuits for one bit in FIG. 11 (1) are cascaded (cascaded) in a plurality of stages, and corresponds to an actual delay circuit. Although only three stages are shown in the figure, they are actually connected in multiple stages. The signal lines of the other input signals (ie, the activation signals) φE are provided for each circuit element by φE-1, φE-2 and φE-
3, and these activation signals are controlled by the delay control circuit 40.

In the figure, the middle one-bit delay circuit is activated, and the activation signal φE-2 is at "H" level. In this case, when the input signal IN changes from the "L" level to the "H" level, the activation signals .phi.E-1 and .phi.E-3 of the leftmost one-bit delay circuit and the rightmost one-bit delay circuit are both activated. Since it is at “L” level, the input signal IN is
It is stopped at the ND circuits 201-1 and 201-3. On the other hand, since the activation signal φE-2 of the activated delay circuit for the middle one bit is at the “H” level, the input signal IN passes through the NAND circuit 201-2. Output signal O of 1-bit delay circuit on the right
Since the UT is at “H” level, the input signal IN is NAN.
The signal also passes through the D circuit 202-2, and is transmitted to the output side as an output signal OUT of "L" level. As described above, when the activation signal φN is at the “L” level, the left output signal OUT is always at the “L” level. Therefore, this “L” level signal is the NAND of the left one bit delay circuit. Sequentially transmitted to the circuit and inverter,
It is taken out as the final output signal OUT.

As described above, the input signal IN is transmitted so as to be folded back through the activated 1-bit delay circuit, and finally becomes the output signal OUT. That is,
The delay amount can be controlled depending on which part of the activation signal φE is set to the “H” level. The delay amount for one bit is determined by the total signal propagation time of the NAND circuit and the inverter, and this time becomes the unit time of the delay amount of the DLL circuit. The delay time corresponding to the entire delay amount is the amount obtained by multiplying the delay amount for one bit by the number of stages to be passed.

FIG. 12 is a diagram showing an example of the configuration of the delay control circuit of FIG. 4, and FIG. 13 is a timing chart for explaining the operation of the delay control circuit of FIG. As shown in FIG. 12, the delay control circuit 1
In this configuration, the delay control circuits 400-2 for the bits are connected by the number of stages of the delay circuit, and the output of each stage becomes the activation signal φE of each stage of the delay circuit.

One bit delay control circuit 400-2
Is a NAND gate 402-2 and an inverter 403
-40-2, 408-2,
And 407-2, 409-2, and a NOR gate circuit 401-2. The gate terminal of the transistor 408-2 is connected to the terminal 4a-2 at the preceding stage, and the gate terminal of the transistor 409-2 is connected to the terminal 4a- at the subsequent stage.
5 for receiving signals at the preceding and subsequent stages. On the other hand, the other transistor connected in series has a set signal φ for counting up.
SE and φSO, and reset signals φRE and φRO for counting down are connected every other circuit. As shown in the figure, a delay control circuit 400 for one bit at the center.
-2, the transistor 405-2 outputs the set signal φSO
And the transistor 407-2 is connected to the reset signal φRO, and the delay control circuit 40
0-2, the other set signal φSE
And the reset signal φRE. NOR circuit 401
-2 is the terminal 4a of the left NAND gate 402 # 1
-1 and the signal of the terminal 4a-2 of the same circuit is inputted. Note that the reset signal φR is a signal for resetting the delay control circuit, and temporarily becomes “L” after power-on.
Level, and thereafter fixed at the “H” level.

Further, in FIG. 12, a plurality of nodes N1 to N1 of the clock cycle measuring circuit 50 (see FIG. 8) are described.
N3 signals (only three signals are shown here for convenience of explanation) are supplied to the output sides of the inverters 403-1 to 403-3, respectively. In this embodiment, the nodes N1 to N1
Since N3 is at "H" level and the node N4 and thereafter are at "L" level, the activation signal φE-4 on the output side of the NOR circuit 401-4 is at "H" level (not shown in FIG. 12). ). Thereby, four stages of the delay circuit are set in the variable delay circuit 21 as a delay amount corresponding to one cycle of the external clock signal.

In the timing chart of FIG. 13, first, the reset signal φR temporarily goes to the "L" level, the terminals 4a-1, 4a-3 and 4a-5 are reset to the "H" level, and the terminal 4a −2, 4a-4 and 4
a-6 is reset to the “L” level. When counting up, the reset signal φSE and the set signal φSO, which are count-up signals, alternately repeat “H” level and “L” level. When the set signal φSE changes from “L” level to “H” level, the terminal 4a-1 is grounded and changes to “L” level, and the terminal 4a-2 changes to “H” level. In response to the change of terminal 4a-2 to "H" level, activation signal .phi.E-1 changes from "H" level to "L" level. Since this state is latched by the flip-flop, even if set signal φSE returns to “L” level, activation signal φE-1 remains at “L” level.

Then, in response to the change of terminal 4a-1 to the "L" level, activation signal φE-2 changes from the "L" level to the "H" level. Terminal 4a-2 is "H"
When the set signal φSO changes from “L” level to “H” level, the terminal 4a-3 is grounded and changes to “L” level. , Terminal 4a-4 changes to "H" level. In response to terminal 4a-4 changing to "H" level, activation signal .phi.E-2 changes from "H" level to "L" level. Since this state is latched by the flip-flop, the activation signal φE-2 remains at the “L” level even if the set signal φSO returns to the “L” level.

Then, in response to the change of terminal 4a-3 to "L" level, activation signal φE-3 changes from "L" level to "H" level. In FIG. 13, although only one set signal φSE and one pulse of φSO are output, the delay control circuit is connected to any number of stages, and the set signals φSE and φSO alternately become “H” level and “L”. When the level is repeated, the activation signal φE becomes “H”.
The position of the stage that becomes the level is sequentially shifted to the right. Therefore, when it is necessary to increase the delay amount according to the phase comparison result of phase comparison circuit 30 (FIG. 4), pulses of set signals φSE and φSO may be input alternately.

If the set signals .phi.SE and .phi.SO for counting up and the reset signals .phi.RE and .phi.RO for counting down are not output, that is, the state of "L" level is maintained, the output is activated. The position of the stage at which the activation signal φE becomes “H” level is fixed. Therefore, when it is necessary to maintain the delay amount according to the phase comparison result of phase comparison circuit 30, set signals φSE and φSO and reset signals φRE and φR
Do not input O pulse.

When the reset signal φRE and the pulse of φRO are input alternately when counting down, the position of the stage where the activation signal φE becomes the "H" level is sequentially shifted to the left, as opposed to when counting up. As described above, in the delay control circuit shown in FIG. 12, by inputting a pulse, the position of the stage where the output activation signal φE becomes the “H” level can be moved one by one. By controlling the variable delay circuit shown in (3) of FIG. 11 by these activation signals φE, it is possible to control the delay amount to increase or decrease by one unit.

Here, the delay circuit and the delay control circuit will be described in more detail. In the above-described embodiment, a circuit as shown in FIG. 11 (3) is used as a delay circuit, and is controlled by a delay control circuit as shown in FIG. In order to realize a circuit in which the delay amount can be changed stepwise by a unit amount, a plurality of signal paths connected in series are provided, and a signal is selectively output from a part of the plurality of signal paths. In general, a delay line whose delay amount can be selected is used. In such a delay line, it is necessary to avoid a state in which any signal path is not selected even in a transient state in which a signal is output from an adjacent signal path in order to change the delay amount. Therefore, the delay control circuit for controlling the delay line as described above needs to always output a signal for selecting one of the signal paths even in a transitional state.

In the delay control circuit shown in FIG. 12, each stage outputs two complementary signals. That is, NAND
The output of the gate and the output of the inverter are complementary signals.
Up to a certain stage, a complementary signal in one state is output,
Subsequent stages output inverted complementary signals, and the stage that outputs the inverted complementary signal first shifts. In other words, the delay control circuit of FIG. 12 performs the same operation as the shift register. In the delay control circuit of FIG. 12, the NOR gate calculates the NOR of two different complementary signals adjacent to each other among the complementary signals of the shift register for each stage, and outputs the output of FIG. It is connected to the selection signal line of each stage of 3). In the MOS transistor used in the embodiment of the present invention, generally, the falling from the logical value of the "H" level to the logical value of the "L" level takes the logical value of the "L" level to the logical value of the "H" level. The change speed is faster than the rise to the logical value. In the delay control circuit of FIG. 12, both inputs are NOR of a logical value of "L" level.
The output of the gate indicates the selection position of the delay line, and one of the inputs of this NOR gate slowly changes to the logical value of "H" level, and the output of the NOR gate indicating the selection position of the delay line is next. “H” level input changes to “L” level at a faster rate. Therefore, before the output of the NOR gate, which previously indicated the selected position, stops indicating the selected position, NO
Since the output of the R gate will indicate the selected position,
A state where none of the NOR gates indicates the selected position can be avoided.

Next, referring to FIGS. 14 to 20,
The specific configuration and operation of the phase comparison circuit 30 in FIG. 4 will be described. The phase comparison circuit 30 includes two circuit parts, a phase comparison unit and an amplification circuit unit. More specifically, FIG. 14 is a circuit diagram illustrating a configuration example of the phase comparison unit of the phase comparison circuit in FIG. 4, and FIG. 15 is a diagram illustrating the operation of the phase comparison unit in the phase comparison circuit in FIG. FIG. 16 is a circuit diagram showing one configuration example of the amplifier circuit section of the phase comparison circuit of FIG. 4, and FIG. 17 illustrates the operation of the amplifier circuit section of the phase comparison circuit of FIG. FIG. Further, FIG.
6 is a timing chart for explaining the count-up operation of the amplifier of the phase comparison circuit of FIG. 6, FIG. 19 is a timing chart for explaining the count maintaining operation of the amplifier, and FIG. 5 is a timing chart for explaining the countdown operation of FIG.

FIG. 14 shows a phase comparison circuit 30 for describing the structure and operation of a general phase comparison circuit.
The two signals to be compared in FIG. 4 are output signal φout
(Corresponding to the aforementioned internal clock signal) and an external clock signal φext (the aforementioned second clock input signal CLK2
). Here, the phase of the output signal φout is determined with reference to the external clock signal φext, and φa to φe indicate output signals connected to the amplifier circuit unit. As shown in FIG. 14, the phase comparison unit in the phase comparison circuit includes flip-flop circuits 301 and 303 each including two NAND gates 3a-2 and 3a-3, and a latch circuit for latching the state. 305, 306, a circuit 304 for generating an activation signal for these latch circuits, and a delay circuit 302 for one delay for obtaining an allowable phase value of the external clock signal φext.

In FIG. 15, (1) shows that the output signal φout, which is the signal to be compared, has a phase advanced from the external clock signal φext, which is the comparison reference, and the output signal φout
The case where t changes from “L” level to “H” level before the external clock signal φext is shown. Output signal φ
When both out and external clock signal φext are at “L” level, flip-flop circuits 301 and 303
Terminals 3a-2, 3a-3, 3a-4 and 3a-5 are all at "H" level. When the output signal φout changes from “L” level to “H” level, the terminal 3a
Both -2 and 3a-4 change from "H" level to "L" level. After that, the external clock signal φext becomes “L”
The terminal 3a-1 changes from the "L" level to the "H" level after a delay of one unit from the "H" level, but the potential at both ends of the flip-flop has already been determined. No change occurs.

After all, the terminal 3a-2 maintains the "L" level, the 3a-3 maintains the "H" level, the terminal 3a-4 maintains the "L" level, and the terminal 3a-5 maintains the "H" level. On the other hand, in response to the external clock signal φext changing from “L” level to “H” level, the output signal φa of the circuit 304 changes from “L” level to “H” level, and the terminals 3a-6 Is temporarily applied with a pulse which goes high. The signal at the terminal 3a-6 is supplied to the latch circuit 30
5 and 306, the NAND gate circuits are temporarily activated, and the potential states at both ends of the flip-flop circuits 301 and 303 are taken into the latch circuits 305 and 306. Eventually, output signal φb is at “H” level, output signal φc is at “L” level, output signal φd is at “H” level, and output signal φe is at “L” level.

Next, FIG. 15 (2) shows that the output signal φout, which is the comparison target signal, and the external clock signal φext, which is the comparison reference, have almost the same phase, and the output signal φout
A case where t changes from “L” level to “H” level almost simultaneously with the external clock signal φext is shown. That is, when the output signal φout rises and the terminal 3a-1
In this case, the output signal φout changes from the “L” level to the “H” level within the time difference from the rising point in FIG.
In this case, first, when the external clock signal φext changes from “L” level to “H” level, the terminal 3a-3 of the flip-flop circuit 301 changes from “L” level to “H” level. 30
In terminal 3, since the terminal 3a-1 remains at the "L" level, the terminal 3a-4 changes from the "H" level to the "L" level. Thereafter, the terminal 3a-1 changes from the "H" level to the "L" level, but no change occurs because the state of the flip-flop circuit 303 has already been determined. After that, the terminal 3a-6 temporarily becomes "H" level,
This state is stored in the latch circuit. As a result, the output signal φb becomes “L” level, the output signal φc becomes “H” level, the output signal φd becomes “H” level, and the output signal φe becomes “L” level.

Further, (3) of FIG. 15 shows that the output signal φout, which is the signal to be compared, is delayed in phase from the external clock signal φext, which is the comparison reference, and the output signal φo
ut changes from “L” level to “H” level after the external clock signal φext. In this case, the external clock signal φext causes a change in the two flip-flop circuits 301 and 303, and the terminal 3a
-3 and 3a-5 change from "H" level to "L" level. And finally, the output signal φb becomes “L”.
Level, the output signal φc becomes “H” level, the output signal φd becomes “L” level, and the output signal φe becomes “H” level.

As described above, the rising time of the output signal φout has reached the “H” level before, substantially at the same time, or has reached the “H” level with a delay with reference to the rising time of the external clock signal φext. Can be detected. These detection results are latched as the values of the output signals φb, φc, φd, and φe, and whether to count up or down the delay control circuit is determined based on the values.

FIG. 16 shows a circuit configuration of the amplifier circuit section of the phase comparison circuit 30 (FIG. 4). Here, the amplifier circuit section
It comprises two parts, a K flip-flop 307 and an amplifier 308 composed of a NAND gate and an inverter. Output signal φa is input to JK flip-flop 307 from the phase comparison unit in FIG. 14, and terminals 5a-9 and 5a- are output in accordance with whether output signal φa is at “L” level or “H” level. The eleventh potential alternates between "L" level and "H" level alternately. The amplification unit 308 receives and amplifies the output signal of the JK flip-flop 307 and the output signals φb to φd from the phase comparison unit, and outputs the amplified signal.

First, the operation of JK flip-flop 307 will be described with reference to the timing chart of FIG.
When output signal φa changes from “H” level to “L” level at time T1, terminals 5a-1 and 5a-10 change from “L” level to “H” level. On the other hand, according to the change of the terminal 5a-1, the terminals 5a-5, 5a
Although the state changes at -6 and 5a-7, no change occurs at the terminal 5a-8 because the output signal φa is at the “L” level. After all, the output level of the terminal 5a-9 does not change, and only the terminal 5a-11 changes from the "L" level to the "H" level.

Next, at time T2, the output signal φa
Changes from the “L” level to the “H” level, the time T
1, the terminal 5a-8 changes from the "H" level to the "L" level, but since the terminal 5a-7 does not change, the terminal 5a-10 does not change and the output 5a-9 changes to the "L" level. "
The level changes from "H" level to "H" level, and the terminals 5a-11 remain unchanged. Thus, even after time T2,
The JK flip-flop circuit 307 causes the terminals 5a-9 and 5a-11 to alternately repeat the "H" level and the "L" level in response to the movement of the output signal φa.

Next, the operation of the amplifying unit 308 will be described with reference to FIGS.
This will be described with reference to FIG. FIG. 18 shows a case where the output signal φout, which is the comparison target signal, first goes from the “L” level to the “H” level in response to the rise of the external clock signal φext serving as the comparison reference. In this case, the output signal φb supplied from the phase comparator is at “H” level,
Output signal φc is at “L” level, output signal φd is at “H” level, and output signal φe is at “L” level.

After all, terminal 5a-12 is fixed at "H" level, terminal 5a-13 is fixed at "L" level, and set signals φSO and φSE change according to the state of JK flip-flop. Signals φRO and φ
RE does not change because the terminal 5a-13 is at the "L" level. FIG. 19 shows an output signal φout which is a signal to be compared.
Shows a case where the level changes from "L" level to "H" level almost simultaneously with the external clock signal φext serving as a comparison reference. In this case, the output signal φ supplied from the phase comparison unit
b is an “L” level, an output signal φc is an “H” level, an output signal φd is an “H” level, and an output signal φe is an “L” level. After all, the terminals 5a-12 and 5a-1
3 is fixed at the “L” level, and the set signals φSO and φSE do not affect the amplifying section which is the output of the JK flip-flop, and the set signals φSO and φSE
And reset signals φRO and φRE remain fixed at “L” level.

FIG. 20 shows an output signal φ which is a signal to be compared.
Out shows a case where the level changes from the “L” level to the “H” level with a delay with respect to the rise of the external clock signal φext serving as a comparison reference. In this case, the output signal φb supplied from the phase comparator is at “L” level, and the output signal φc
Are at "H" level, output signal φd is at "L" level, and output signal φe is at "H" level. After all, terminal 5a
-12 is fixed at "L" level, the terminals 5a-13 are fixed at "H" level, and the reset signals φRO and φRE are set to JK.
Although it changes according to the state of the flip-flop, the set signals φSO and φSE do not change because the terminals 5a-13 are at the "L" level.

The case where the clock phase adjusting circuit of the present invention is constituted by a DLL circuit applied to a high-speed memory system such as an SDRAM has been described. However, it is needless to say that the present invention is not limited to such a specific circuit configuration and can be applied to a general semiconductor device.

[0088]

As described above, according to the semiconductor device of the present invention, first, even when the semiconductor device is not in the normal operation mode, the clock cycle measuring unit determines the predetermined period of the external clock signal. Since the delay amount equivalent to a minute is measured and the above-mentioned delay amount is set in the vicinity of the delay amount necessary for lock-on of a variable delay circuit or the like, the time required for the lock-on state is greatly reduced. Can be shortened.

Further, according to the semiconductor device of the present invention, secondly, the supply of the external clock signal to the delay circuit portion and the phase comparison circuit portion is stopped for a certain period from the time when the power of the semiconductor device is turned on. Since the delay amount corresponding to a predetermined period of the signal is measured and the delay amount is set near the delay amount necessary for lock-on of the variable delay circuit or the like, D
The time required until the variable delay circuit or the like is brought into the lock-on state without causing malfunction of the LL circuit or the like can be greatly reduced.

Further, according to the semiconductor device of the present invention, thirdly, the supply of the external clock signal to the delay circuit unit and the phase comparison circuit unit is stopped for a certain period after the operation mode of the semiconductor device is switched, Since the delay amount corresponding to a predetermined period of the external clock signal is measured and the delay amount is set near the delay amount required for lock-on of the variable delay circuit or the like, the operation mode of the semiconductor device is The time required for setting the variable delay circuit or the like to the lock-on state without adversely affecting the DLL circuit or the like by the switching can be greatly reduced.

Further, according to the semiconductor device of the present invention, fourthly, the above-mentioned delay amount is adjusted at once in the vicinity of the delay amount necessary for lock-on of the variable delay circuit or the like only immediately after the power supply of the semiconductor device is turned on. In addition, since the delay amount is accurately adjusted using a variable delay circuit or the like, the phase of the internal clock signal can be accurately and promptly adjusted without causing a malfunction of the DLL circuit or the like due to the rise of the power supply of the semiconductor device. It becomes possible to adjust.

Further, according to the semiconductor device of the present invention, fifthly, only immediately after the semiconductor device has returned from the standby mode, the above-mentioned delay amount is adjusted at once in the vicinity of the delay amount necessary for lock-on of the variable delay circuit or the like. Then, since the delay amount is accurately adjusted using a variable delay circuit or the like, the phase of the internal clock signal can be adjusted without causing a malfunction of the DLL circuit or the like immediately after returning from the standby mode of the semiconductor device. The adjustment can be performed quickly with high accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle configuration of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a synchronous DRAM to which the semiconductor device of the present invention is applied;

FIG. 3 is a timing chart for explaining the operation of the synchronous DRAM of FIG. 2;

FIG. 4 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration example of a DLL control circuit of FIG. 4;

FIG. 6 is a timing chart (part 1) for explaining the operation of the DLL control circuit of FIG. 5;

FIG. 7 is a timing chart (2) for explaining the operation of the DLL control circuit of FIG. 5;

FIG. 8 is a circuit diagram showing a configuration example of a clock cycle measuring circuit of FIG. 4;

FIG. 9 is a timing chart (part 1) for explaining the operation of the clock cycle measurement circuit of FIG. 8;

FIG. 10 is a timing chart (2) for explaining the operation of the clock cycle measurement circuit of FIG. 8;

11 is a diagram showing a circuit configuration and operation waveforms of the variable delay circuit of FIG.

FIG. 12 is a circuit diagram showing a configuration example of a delay control circuit of FIG. 4;

FIG. 13 is a timing chart for explaining the operation of the delay control circuit of FIG. 12;

FIG. 14 is a circuit diagram illustrating a configuration example of a phase comparison circuit (phase comparison section) in FIG. 4;

FIG. 15 is a timing chart for explaining the operation of the phase comparison circuit (phase comparison unit) in FIG. 14;

FIG. 16 is a circuit diagram showing a configuration example of a phase comparison circuit (amplifier circuit section) in FIG. 4;

FIG. 17 is a timing chart for explaining the operation of the phase comparison circuit (JK flip-flop) in FIG. 16;

FIG. 18 is a timing chart illustrating a count-up operation of the phase comparison circuit (amplifying unit) in FIG. 16;

FIG. 19 is a timing chart illustrating a count maintaining operation of the phase comparison circuit (amplifying unit) in FIG. 16;

20 is a timing chart illustrating a countdown operation of the phase comparison circuit (amplifying unit) in FIG. 16;

FIG. 21 is a circuit block diagram showing a configuration of a semiconductor device having a conventional clock phase adjustment circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 clock phase adjustment circuit 2 delay circuit section 3 phase comparison circuit section 4 delay control circuit section 5 clock cycle measurement section 6 clock phase adjustment circuit control section 7 # 1 to 7 # 7 D flip-flop 8 Clock input circuit 9 Data output circuit 10 DLL circuit 18 Dummy input circuit section 19 Dummy output circuit section 21 First variable delay circuit 22 Second variable delay circuit 25 Basic delay circuit 28 Dummy input buffer 29 ... Dummy data output buffer 30 ... Phase comparison circuit 40 ... Delay control circuit 50 ... Clock cycle measurement circuit 60 ... DLL control circuit

Claims (5)

[Claims] 1. A semiconductor device comprising a clock phase adjusting circuit for adjusting the phase of an external clock signal supplied from the outside and outputting an internal clock signal, wherein the clock phase adjusting circuit comprises a delay amount of the external clock signal. A delay circuit unit that delays the external clock signal by a selected delay amount and outputs the delayed clock as the internal clock signal; and a phase of the external clock signal and a phase of a signal responsive to the internal clock signal. A delay control circuit for selecting a delay amount of the delay circuit based on a result of the phase comparison performed by the phase comparator, and a delay period corresponding to a predetermined period of the external clock signal. A clock cycle measuring unit that measures a delay amount and supplies a measurement result of the delay amount to the delay control circuit unit. The delay control circuit unit sets a delay amount corresponding to a predetermined period of the external clock signal to the delay circuit unit during a period in which the supply of the external clock signal to the phase comparison circuit unit is stopped. A semiconductor device characterized by the above-mentioned. 2. The method according to claim 1, wherein the supply of the external clock signal to the phase comparison circuit unit is stopped for a predetermined period after power-on of the semiconductor device, and a delay amount corresponding to a predetermined period of the external clock signal is measured. 2. The semiconductor device according to claim 1, further comprising a clock phase adjustment circuit control unit that enables a result to be supplied to the delay control circuit unit. 3. A delay amount corresponding to a predetermined period of the external clock signal, wherein the supply of the external clock signal to the phase comparison circuit unit is stopped for a predetermined period from a time when the operation mode of the semiconductor device is switched. 2. The semiconductor device according to claim 1, further comprising a clock phase adjustment circuit control unit configured to supply the measurement result of (b) to the delay control circuit unit. 3. 4. Immediately after turning on the power of the semiconductor device, the phase of the external clock signal is adjusted based on the measurement result of the delay amount by the clock cycle measurement circuit. 3. The semiconductor device according to claim 2, wherein a phase of the external clock signal is adjusted based on a result of the phase comparison. 5. Immediately after the semiconductor device returns from a standby mode, a phase adjustment of the external clock signal is performed based on a result of the measurement of the delay amount by the clock cycle measurement circuit. 4. The semiconductor device according to claim 3, wherein a phase of the external clock signal is adjusted based on a result of the phase comparison.