JPH11272499A - Parallel processor system equipped with performance measuring circuit and method for measuring performance of program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To measure an access time or the number of times of access for each processing or each processor. SOLUTION: The values of measuring counters 51 and 52 are initialized, and a measuring ID value corresponding to a processing content is set in measuring ID registers 71-73 of each processor 61-63. When a processor performs access to a synchronizing register 2, the measuring ID value is transmitted to a measuring counter control circuit 3, and when any processor succeeds in access a shared resource a count-up circuit 4 outputs a prescribed count-up instruction signals to the measuring counter 51 or 52 corresponding to the inputted measuring ID value. The measuring counter measures a clock signal in a prescribed procedure, and when all the prescribed processing are ended, the measured values of the measuring counters 51 and 52 are read, and transmitted to a prescribed processor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to improving the performance of a program in a parallel processor system, and more particularly to a circuit for measuring the performance of a program.

[0002]

2. Description of the Related Art Tuning a program for improving the program so as to improve the performance of the program in order to bring out the performance of the system is a very important task even in increasing the speed of a parallel program. In order to perform this tuning work, it is important to measure the performance of the program in advance and to specify the parts that require the most tuning.

Generally, a multiprocessor system has shared resources such as a shared register and a shared memory that can be accessed from all processors in order to realize communication between processes and control between tasks. The number of accesses to these shared resources and the access time greatly affect the overall parallel processing performance.

As an example in which the access time of the common resource affects the overall performance, there is a case where exclusive control between processors is realized using a synchronization register. While one processor acquires the lock to execute the exclusive processing unit, the other processor cannot execute the exclusive processing unit. Therefore, if the synchronization register is locked for a long time, the performance of the system deteriorates. . Therefore, it is important to measure the time during which the synchronization register is locked and tune the program so as to shorten the time during which the synchronization register is locked, in order to improve the performance of the entire program.

For this reason, many conventional large-sized information processing apparatuses are provided with a performance measurement counter for counting the operation processing time, the number of operations, and the like in order to measure the performance of a program.

[0006]

However, when a single performance measurement counter is provided for a shared resource accessed by a plurality of processors as in the conventional system, the performance measurement counter includes: Since the total time of shared resources accessed by each processor is recorded, it is not possible to measure the access time and the number of accesses for each processor, so identify programs that are causing system performance degradation There was a problem that it was not possible.

An object of the present invention is to provide a parallel system provided with a performance measuring circuit capable of measuring an access time of each process or each processor, an access frequency, and the like, and a method of measuring the performance of a program.

[0008]

A parallel processor system having a performance measuring circuit according to the present invention has a plurality of processors having a measurement ID register capable of setting a measurement ID value by software, and can be accessed from all processors. Resource, a shared resource control circuit for controlling access to the shared resource, and a measuring I
A performance measurement circuit is provided for measuring the access time from the processor to the shared resource for each measurement ID value set in the D register. This performance measurement circuit processes a plurality of measurement counters and an access request from a processor to a shared resource, stores a measurement ID register value, instructs the measurement counter to write, reads a measurement counter counter value, and reads the measurement counter value. And a count-up control circuit that controls the measurement counter and records the state of access to the shared resource of the processor corresponding to the measurement ID value to the corresponding measurement counter.

The state of access to the shared resource recorded in the measurement counter may be an access time or the number of accesses.

The measurement ID value set in the measurement ID register of the processor is a value corresponding to the type of processing of the program, and the measured value corresponding to the type of processing may be recorded in the measurement counter. And a measurement value corresponding to each processor may be recorded in the measurement counter.

[0011] The shared resource may be a synchronous register or a shared memory, a network between processors, the measured value may be the use time of the network, a peripheral device, or a peripheral device. The value may be the usage time of the peripheral device.

A method for measuring the performance of a program according to the present invention is a method for measuring the performance of a parallel processor system provided with a performance measuring circuit. Measurement ID corresponding to the processing content of each processor in the register
When the processor sets the value and accesses the shared resource, the processor sends the measurement ID value set in the internal measurement ID register to the measurement counter control circuit of the performance measurement circuit. If the access to the shared resource succeeds, the measurement ID value sent from the processor is stored in the measurement register of the measurement counter control circuit and transmitted to the count-up control circuit. A predetermined count-up instruction signal is output to the measurement counter corresponding to the ID value, and the measurement counter that inputs the count-up instruction signal measures the clock signal in a predetermined procedure, and when the access of the shared resource is released. The count-up control circuit stops outputting the count-up signal. It reads the total side value of the printer to be sent to a predetermined processor.

The measurement circuit of the present invention can set an individual measurement ID value for each processor and measure the access time of the shared resource for each ID value. It is possible to know not only the total time of the processors within, but also the processing contents and each processor, and it is possible to measure the performance of each program.

[0014] Uneven access time between processors, etc.
Since it is possible to obtain more detailed performance information than the conventional measurement method, it is easy to specify a portion where the parallel program should be tuned.

[0015]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a parallel processor system including a performance measuring circuit according to the first embodiment of the present invention.

(Configuration) In a parallel processor system having a performance measuring circuit according to the first embodiment of the present invention, a synchronous processor is provided in a parallel processor system having three processors and two measurement counters. A case in which exclusive control is performed using the above will be described as an example.

A parallel processor system provided with the performance measuring circuit of the present invention shown in FIG. 1 comprises a first processor 61 having a measurement ID register 71, and a measurement ID register 72.
Processor 62 having ID and measurement ID register 7
3, a third processor 63 having three, a synchronization register 2, a synchronization register control circuit 1, and a performance measurement circuit 9.

The performance measurement circuit 9 includes a measurement counter control circuit 3 having a measurement ID holding register 31, a count-up control circuit 4, a first measurement counter 51, and a second measurement counter 52. And

The synchronous register control circuit 1 and the first to third processors 61 to 63 are provided with synchronous register access request paths A1 to A3 and synchronous register reply paths B1 to B3.
Connected by The synchronous register control circuit 1 and the synchronous register 2 are connected by a synchronous register write path C, a synchronous register read path D, and a synchronous register control signal E.

The synchronous register control signal E is a read signal for controlling the reading and writing of the synchronous register 2 and a write signal. Synchronous register control circuit 1
Performs an access to the synchronization register 2 in accordance with an access request to the synchronization register 2 from the first to third processors 61 to 63, and sends the result to the processor.

The measurement counter control circuit 3 has a measurement ID holding register 31 therein. The measurement counter control circuit 3 and the first to third processors 61 to 63 are connected by measurement counter access request paths L1 to L3 and measurement counter reply paths M1 to M3.

The measurement counter control circuit 3, the first measurement counter 51, and the second measurement counter 52 are connected by a measurement counter write path J and a measurement counter read path K. The measurement counter control circuit 3 controls reading and writing of the first measurement counter 51 and the second measurement counter 52 in accordance with the access requests of the measurement counters from the first to third processors 61 to 63.

When one of the first to third processors 61 to 63 accesses the synchronization register 2, the measurement counter control circuit 3 sends out the measurement ID of the measurement ID register 71 to 73 of that processor. Value for measurement I
Write to the D holding register 31.

The count-up control circuit 4 has a measurement ID
The output F of the holding register 31 and the output G of the synchronization register 2
And connected to. The output G of the synchronization register 2 is a signal indicating the time when the synchronization register 2 is locked for access by any processor and the first measurement counter 51 or the second measurement counter 52 is counted up. The count-up control circuit 4 controls the synchronization register 2
Of the measurement ID held by the measurement ID holding register 31 only while the synchronization register 2 is locked.
The count-up instruction signal H1 or H2 is exclusively output to the first measurement counter 51 or the second measurement counter 52 corresponding to the D value.

The first measurement counter 51 and the second measurement counter 52 count clocks only while being selected by the output H1 or H2 of the count-up control circuit 4, respectively.

(Explanation of Operation) An example of the configuration of the present invention shown in FIG.
The operation of the parallel processor system of the present invention will be described with reference to the simple parallel program example shown in FIG.

FIG. 2 is a flowchart of an example of a parallel program of the parallel processor system of FIG. In the figure, symbols P, Q1 to Q3, R1 to R3, and S indicate a program routine.

The parallel program shown in FIG.
The processing X is performed in parallel by two processors, a first processor 61 and a second processor 62. Each of the processing X and the processing Y needs to be processed exclusively, and by the lock control method using the synchronization register 2,
Implement exclusive control. In the description of the performance measurement circuit of the present embodiment, the time during which a lock is acquired for exclusive control is measured for each of the processing X and the processing Y.

First, prior to performance measurement, the first processor 61 executes a measurement counter initialization routine P.
The first processor 61 sends a request to initialize the first measurement counter 51 and the second measurement counter 52 to the measurement counter control circuit 3 through the measurement counter access request path L1.
Send to

The measurement counter control circuit 3 writes an appropriate initial value into the first measurement counter 51 and the second measurement counter 52 through the measurement counter write path J, thereby obtaining the first measurement counter 51 and the second measurement counter 52. Measurement counter 5
2 is initialized.

Next, prior to execution of the parallel routines R1 to R3, the first to third processors 61 to 63 store the measurement IDs in the measurement ID registers 71 to 73 inside the processors.
Set the value.

The first processor 61 executes the routine Q1 and outputs the measurement ID value “1” indicating the processing X to the measurement I
Set in the D register 71. Similarly, the second processor 62 also converts the measurement ID value “1” indicating the process X into the measurement ID value “1”.
Set to D register 72. The third processor 63 includes:
The routine Q3 is executed, and the measurement ID value “2” indicating the process Y is set in the measurement ID register 73. The processing time for setting the measurement ID value in the register inside the processor is so short that the influence on the performance of the program can be ignored.

After setting the measurement ID value, the first processor 61 executes the parallel routine R1. Before executing the exclusive processing X, the first processor 61
Make a lock request to. The first processor 61 includes:
The lock request is sent to the synchronous register control circuit 1 through the synchronous register access request path A1. At the same time, the first
The processor 61 transmits the measurement ID value “1” held in the internal measurement ID register 71 to the measurement counter control circuit 3 through the measurement counter access request path L1.

The synchronous register control circuit 1 arbitrates access requests for the synchronous register asynchronously sent from the first to third processors 61 to 63, and processes the access request for the synchronous register 2.

When the synchronous register control circuit 1 processes a lock request from the first processor 61, the synchronous register control circuit 1 reads the value of the synchronous register 2 using the synchronous register read path D. The value read from the synchronization register 2 is sent to the first processor 61 via the synchronization register reply path B1. Further, the synchronization register control circuit 1 writes “1” indicating that locking is being performed to the synchronization register 2 through the synchronization register writing path C.

If the value read from the synchronization register 2 in response to the lock request from the first processor 61 is "1", the acquisition of the lock has failed.
No. 1 cannot execute the process X. Until the lock is successfully acquired, the first processor 61 repeats the lock request to the synchronization register control circuit 1.

If the value read from the synchronization register 2 is "0" in response to the lock request from the first processor 61, the lock is successfully acquired, and the first processor 61 can execute the exclusive processing X.

When the first processor 61 succeeds in acquiring the lock, the measurement counter control circuit 3 stores the measurement ID value “1” sent from the first processor 61 in the measurement ID holding register 31. I do. The measurement ID holding register 31 outputs the held value “1” to the count-up control circuit 4.

The count-up control circuit 4 has a measurement ID
The output F of the holding register 31 and the output G of the synchronization register 2
The count-up instruction signal H1 corresponding to the value “1” held in the measurement ID holding register 31 is output to the first measurement counter 51 using The first measurement counter 51 that has received the count-up instruction signal H1 counts the clock signal while the count-up instruction signal H1 is being supplied.

When the first processor 61 terminates the execution of the exclusive processing X and issues an unlock request to the synchronous register control circuit 1, the synchronous register control circuit 1 sends the unlock request to the synchronous register 2 through the synchronous register write path C. Write “0”. When "0" is written to the synchronization register 2 and the lock is released, the count-up control circuit 4 stops outputting the count-up instruction signal H1.

By the above operation, the first processor 61
The time during which the lock is acquired is determined by the first measurement counter 5
1 can be measured.

When the second processor 62 starts the exclusive processing X of the routine R2, the second processor 62
The lock request is sent to the synchronous register control circuit 1 through the synchronous register access request path A2. At the same time, the measurement ID value “1” held by the measurement ID register 72 is
It is sent to the measurement counter control circuit 3 through the measurement counter access request path L2.

The synchronous register control circuit 1 reads the value of the synchronous register 2 in response to a lock request from the second processor 62, and stores the value in the measurement counter access request path L
2 to the second processor 62. At the same time, the synchronization register control circuit 1 writes “1” indicating that locking is being performed to the synchronization register 2 through the synchronization register write path C.

The value read from the synchronization register 2 is "0"
Then, when the second processor 62 succeeds in acquiring the lock, the measurement counter control circuit 3 sets the second processor 62
Is stored in the measurement ID holding register 31. Measurement ID holding register 3
1 is a counter for counting up the measurement ID value “1”.
Output to

The count-up control circuit 4 has a measurement ID
Using the output F of the holding register 31 and the output G of the synchronization register 2 indicating that locking is being performed, the count-up instruction signal H1 corresponding to “1” held in the measurement ID holding register 31 is subjected to the first measurement. Output to the counter 51. The first measurement counter 51 that has received the count-up instruction signal H1 counts the clock signal while the count-up instruction signal H1 is being supplied.

When the second processor 62 terminates the execution of the process X and issues an unlock request to the synchronous register control circuit 1, the synchronous register control circuit 1 sends the unlock request to the synchronous register 2 through the synchronous register write path C. Write "0". When "0" is written to the synchronization register 2, the count-up control circuit 4 stops outputting the count-up instruction signal H1.

By the above operation, the second processor 62
The time during which the lock is acquired is determined by the first measurement counter 5
1 can be measured.

Similarly, when the third processor 63 starts the exclusion process Y of the routine R3, in order to acquire the lock, the third processor 63 transmits the synchronous register control circuit 1 through the synchronous register access request path A3. Sends a lock request. At the same time, the third processor 63
The measurement ID value “2” is transmitted to the measurement counter control circuit 3 through the measurement counter access request path L3.

The synchronous register control circuit 1 reads the value of the synchronous register 2 in response to a lock request from the third processor 63, and sends the value to the third processor 63 via the synchronous register reply path B3. At the same time, the synchronization register control circuit 1
Is written to the synchronization register 2 through the process, indicating that locking is being performed.

The value read from the synchronization register 2 is "0"
When the third processor 63 succeeds in acquiring the lock, the measurement counter control circuit 3
Is stored in the measurement ID holding register 31. Measurement ID holding register 3
1 is a count-up control circuit 4 for counting the measurement ID value “2”.
Output to

The count-up control circuit 4 has a measurement ID
The output F of the holding register 31 and the output G of the synchronization register 2
The third ID held by the measurement ID holding register 31 using
The count-up instruction signal H2 corresponding to the measurement ID value “2” of the processor 63 is output to the second measurement counter 52. The second measurement counter 52 that has received the count-up instruction signal H2 counts the clock signal while the count-up instruction signal H2 is being supplied.

By the above operation, the third processor 63
The second measurement counter 52 can measure only the time during which the lock is acquired.

After the first to third processors 61 to 63 complete execution of the parallel routines R1 to R3, the first processor 61 executes the first measurement counter 51 and the second The value of the measurement counter 52 is read. The first processor 61 sends a request to read the value of the first measurement counter 51 to the measurement counter control circuit 3 through the measurement counter access request path L1. The measurement counter control circuit 3 reads the value of the first measurement counter 51 through the measurement counter read path K. The measurement counter control circuit 3 sends the value read from the first measurement counter 51 to the first processor 61 via the measurement counter reply path M1.
Next, similarly, the value of the second measurement counter 52 is read and transmitted.

The first processor 61 reads out the values of all the first measurement counters 51 and the second measurement counters 52 to determine the access time to the synchronization register 2 for each measurement ID value, that is, the processing X , For each process Y.

In the description of the first embodiment, the number of processors is 3 and the number of measurement counters is 2. However, the number of processors and the number of measurement counters can be arbitrarily designed.

As described above, the measurement circuit of the present invention can set an individual measurement ID value for each processor and measure the access time of the shared resource for each ID value. Access time can be known for each processor, not the total time of the processors in the system, and the performance of the program can be measured.

For example, access time deviation between processors
Since it is possible to obtain more detailed performance information than the conventional measurement method, it is easy to specify a portion where the parallel program should be tuned. For example, in the first embodiment,
When the value of the second measurement counter 52 is equal to the value of the first measurement counter 51,
If the value is larger than the value, the lock time of the third processor 63 is long, and it can be seen that the entire processing time can be reduced by tuning the processing Y.

The control program is read from the recording medium 62 into a data processing device (not shown) of the control unit 61 and controls the operation of the data processing device. The control unit 61 executes the following processing under the control of the control program.

That is, the first measurement counter 51 and the second measurement counter 51 are instructed by the processor via the measurement counter control circuit 3.
For initializing the value of the measurement counter 52 of each of the above,
1 to 73 to set a measurement ID value corresponding to the processing content of each processor; and, when each processor accesses the shared resource 2, the measurement ID value set in the measurement ID register 71 to 73 from each processor. When the ID value is sent to the measurement counter control circuit 4, and when one of the processors successfully locks the access of the synchronization register 2 for exclusive processing, the measurement ID value sent from the processor is sent to the measurement counter control circuit 4. 3 is sent to the count-up control circuit 4 and sent to the count-up control circuit 4.
A count-up instruction signal is output to any of the measurement counters 51 to 52 corresponding to the value while the synchronization register 2 is locked, and a clock signal is sent to any of the measurement counters 51 to 52 to which the count-up instruction signal is input. , The process of stopping the output of the count-up signal to the count-up control circuit 4 when the synchronization register 2 is unlocked, and the instruction of the processor via the measurement counter control circuit 3.
1 to 52 are read, and the measurement counter control circuit 3
And sending it to the processor via

Next, a second embodiment will be described.
In the first embodiment, the number of processors is 3 and the number of measurement counters is 2. However, in the second embodiment, the same number of measurement counters as the number of processors are prepared, and the number of processors is determined by the routine of Q1 to Q3 in FIG. By giving a processor-specific value, such as a processor physical number or a logical number, as a measurement ID value, a measurement counter is made to count the access time of each processor, and the access time of each processor is measured. In the first embodiment, the access time for each type of processing is measured. In the second embodiment, the access time for each processor is measured.

Next, a third embodiment will be described.
In the first embodiment, the case where the time during which the synchronization register 2 is locked is described as an example, but in the third embodiment, the number of accesses to the synchronization register is measured. In the first embodiment, the count-up control circuit 4
Uses the output F of the measurement ID holding register 31 and the output G of the synchronization register 2 to calculate the measurement ID holding register 31
And outputs a count-up instruction signal H1 or H2 corresponding to the measurement ID value of the processor held by the processor to the first measurement counter 51 or the second measurement counter 52, and the measurement counter receiving the count-up instruction signal counts up. While the clock signal was counted while the instruction signal was supplied, in the third embodiment, the count-up control circuit 4 changes the condition for generating the count-up instruction signal H1 or H2, and Is used as a count-up instruction signal to the measurement counter, the number of accesses to the synchronization register 2 can be easily measured for each measurement ID value. Next, a fourth embodiment will be described. Although the performance measurement circuit of the first embodiment measures the access time for the synchronization register, the fourth embodiment measures the access time and the number of accesses of the shared resources other than the synchronization register. FIG.
When the synchronous register 2 and the synchronous register control circuit 1 are replaced with a shared memory, a network between processes, peripheral devices and the like and their control circuits, the access time of the shared memory, the usage time of the network between processors, and the usage time of the peripheral device And other measurements.

Next, a fifth embodiment will be described.
FIG. 3 is a flowchart of an example of a parallel program of the parallel processor system according to the fifth embodiment. In the figure, reference numerals P, Q1, Q2, R1, R2, and S denote program routines. In the present embodiment, the access time for each routine is measured.

Since the measurement ID value inside the processor can be easily set by software, the setting of the measurement ID value is switched for each routine. First, prior to performance measurement, an initialization routine P of a measurement counter is executed. Next, in the routine Q1, the ID value X1 of the routine to be executed is set in the measurement ID register of the processor to be measured. Thereafter, the routine R1 is executed. Next, the routine Q2
The routine sets the ID value X2 of the routine to be executed in the measurement ID register of the processor to be measured, executes the routine R2, and reads the counter value of the measurement counter after the desired routine is completed. The access time for each can be measured.

[0064]

As described above, the performance measuring circuit for a parallel system according to the present invention can measure the access time and the number of accesses for each processor and each process in a parallel processor system, so that the tuning of the program can be performed. In this case, it is possible to easily specify the part that requires the most tuning, and to improve the program efficiently and improve the performance of the program.

Conventionally, even if a performance measurement counter is provided, only the total time during which each processor accesses the shared resource can be obtained. On the other hand, the measurement circuit of the present invention can set an individual measurement ID value for each processor and measure the access time of the shared resource for each ID value. Not only the total time of the processors within, but per processor. Since it is possible to obtain more detailed performance information than the conventional measurement method, such as a bias in the access time between processors, it is easy to specify a part where the parallel program should be tuned.

[Brief description of the drawings]

FIG. 1 is a block diagram of a parallel processor system including a performance measuring circuit according to a first embodiment of the present invention.

FIG. 2 is a flowchart of an example of a parallel program of the parallel processor system of FIG. 1;

FIG. 3 is a flowchart illustrating an example of a parallel program of a parallel processor system according to a fifth embodiment;

[Explanation of symbols]

Reference Signs List 1 synchronization register control circuit 2 synchronization register 3 measurement counter control circuit 31 measurement ID holding register 4 count-up control circuit 51 first measurement counter 52 second measurement counter 61 first processor 62 second processor 63 third Processor 71 to 73 Measurement ID register 9 Performance measurement circuit A1 to A3 Synchronous register access request path B1 to B3 Synchronous register reply path C Synchronous register write path D Synchronous register read path E Synchronous register control signal F Measurement ID holding register output G Synchronous register output H1 to H2 Count up instruction signal J Measurement counter write path K Measurement counter read path L1 to L3 Measurement counter access request path M1 to Mn Measurement counter reply path P, Q1 to Q3, R1 to R3, S Program routine

Claims (11)

[Claims] 1. A parallel processor system having a program performance measurement circuit, comprising: a plurality of processors having a measurement ID register capable of setting a measurement ID value by software; and a shared processor accessible from all the processors. A resource, a shared resource control circuit that controls access to the shared resource, and an access time from the processor to the shared resource for each measurement ID value set in the measurement ID register inside the processor. The performance measurement circuit has a plurality of measurement counters, processes an access request from the processor to the shared resource, stores a measurement ID register value, and writes the measurement counter. Instructs and reads the counter value of the measurement counter and sends it to the processor A measurement counter control circuit, and a count-up control circuit that controls the measurement counter to cause the corresponding measurement counter to record an access state of the processor to the shared resource corresponding to the measurement ID value. A parallel processor system equipped with a characteristic performance measurement circuit. 2. The access state to the shared resource recorded in the measurement counter is an access time.
A parallel processor system comprising the performance measurement circuit according to item 1. 3. The access status of the shared resource recorded in the measurement counter is an access count.
A parallel processor system comprising the performance measurement circuit according to item 1. 4. A measurement ID value set in the measurement ID register of the processor is a value corresponding to a type of processing of a program, and a measurement value corresponding to the type of processing is recorded in the measurement counter. A parallel processor system comprising the performance measuring circuit according to claim 1. 5. The measurement ID value set in the measurement ID register of the processor is a value for identifying the processor, and a measurement value corresponding to each processor is recorded in the measurement counter. A parallel processor system comprising the performance measurement circuit according to item 1. 6. The parallel processor system according to claim 1, wherein said shared resource is a synchronization register. 7. The parallel processor system according to claim 1, wherein the shared resource is a shared memory. 8. The parallel processor system according to claim 1, wherein the shared resource is an inter-processor network, and the measured value is a use time of the network. 9. The parallel processor system according to claim 1, wherein the shared resource is a peripheral device, and the measured value is a usage time of the peripheral device. 10. A method for measuring the performance of a program of a parallel processor system provided with a performance measuring circuit, wherein a value of a measurement counter of the performance measuring circuit is initialized, and each processor is stored in a measurement ID register of each processor. When the processor accesses a shared resource, the processor sets the measurement ID value set in the internal measurement ID register to the measurement ID value of the performance measurement circuit. Sends to the counter control circuit, and if any of the processors succeeds in accessing the shared resource, stores the measurement ID value sent from the processor in the measurement register of the measurement counter control circuit and counts up. Circuit, and the count-up control circuit outputs the measurement ID value corresponding to the input measurement ID value. The measurement counter outputs a predetermined count-up instruction signal to the measurement counter, and the measurement counter that has received the count-up instruction signal measures the clock signal in a predetermined procedure, and counts up when the access to the shared resource is released. A method for measuring the performance of a program of a parallel processor system, wherein the circuit stops outputting the count-up signal, and upon completion of a predetermined process, reads the measured value of the measurement counter and sends it to a predetermined processor. 11. A recording medium recording a control program for measuring the performance of a program of a parallel processor system, comprising: a procedure for initializing the value of each measurement counter according to an instruction of a processor via a measurement counter control circuit. A procedure for causing each processor to set a measurement ID value corresponding to the processing content of each processor in each measurement ID register; and when the processor accesses a shared resource, the processor sends the measurement ID register to the measurement ID register. A procedure for sending the set measurement ID value to the measurement counter control circuit; and when any of the processors succeeds in accessing the shared resource, the measurement ID value sent from the processor is used for measurement by the measurement counter control circuit. It is stored in a register and sent to the count-up control circuit. The setup control circuit, to one of said measurement counter corresponding to the measurement ID value received, to output a count-up instruction signal while said shared resource is accessed,
A step of causing the measurement counter to input the count-up instruction signal to measure a clock signal in a predetermined procedure, a step of stopping the count-up control circuit from outputting the count-up signal when the lock of the shared resource is released, According to the instruction of the processor via a measurement counter control circuit, read the measurement side value of each measurement counter,
A recording medium for recording a program for executing a procedure of sending the measurement counter control circuit to the processor via the measurement counter control circuit.