JPH11261498A - Device and method for digital audio signal processing and provision medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable interpolation processing of an error sample by making a circuit scale smaller. SOLUTION: First, audio data of nine samples are successively read from a frame memory and an error pattern is detected by an error data detection decoder 40. Then, after an interpolation coefficient corresponding to that is prepared by an interpolation coefficient table 42, product-sum operation of the interpolation coefficient and the data is performed by a multiplier 44 and an adder 45 while reading the data of nine samples again, and the interpolation processing is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital audio signal processing apparatus and method, and a providing medium, and more particularly, to a digital audio signal processing apparatus and method suitable for interpolating error data, and a providing medium.

[0002]

2. Description of the Related Art As a device for recording / reproducing a digital audio signal, a CD (compact disc), MD
In addition to audio-only devices such as (mini-disc) and DAT (digital audio tape recorder), devices for recording and reproducing digital audio signals related to image data such as digital VCRs (video cassette tape recorders) are also known. . In these digital audio signal recording / reproducing devices, it is unavoidable that an error occurs in the process of recording / reproducing. Therefore, it is common to use an error correction code and take measures against the error. However,
If an error occurs that exceeds the correction capability of the error correction code, correction is impossible. In this case, an error sample (a sample having an error) is interpolated by using a correct sample near in time to reduce the influence of the error.

For example, as disclosed in Japanese Patent Application Laid-Open No. 9-161417, in a digital VCR (NTSC system) in which shuffling (rearrangement of data arrangement) processing is performed at a period of five samples, the reproduction time is reduced. By interpolating the error samples with a higher-order polynomial, the quality of the sound can be improved.

FIG. 9 shows the configuration of an example of a digital audio signal reproducing apparatus (helical scan type).
The mechanical deck 70 includes a pair of magnetic heads (not shown) attached to the rotating drum at an angular interval of 180 °, a magnetic tape (not shown) drawn from a tape cassette and wound around the rotating drum, and a magnetic tape. , And a tape traveling mechanism (not shown) for traveling along a predetermined path. A reproduction signal from the mechanical deck 70 is supplied to an equalizer 72 via a reproduction amplifier 71. The output of the equalizer 72 is the demodulator 73 for channel coding and the PL
It is supplied to L75. Channel encoding is performed, for example, by using 24
One that converts a bit information word into a 25-bit code word is used. The output of the demodulator 73 is supplied to a sync / ID detection circuit 74. The recording data has a sync block configuration. The sync block has a sync at the beginning, an ID is added after the sync, data (video data, audio data, or subcode) is located after the ID, and an inner code of an inner code added in sync block units thereafter. It has a data structure where the parity is located. PL
The L75 reproduces a clock synchronized with the reproduction signal, and supplies this clock to the demodulator 73 and the sync / ID detection circuit 74.

The output signal of the sync / ID detection circuit 74 is EC
It is supplied to the C decoder 76. The ECC decoder 76
The error correction code is decoded, and the error sample is corrected.
For example, a product code is used as the error correction code.
The product code encodes an inner code in the recording / reproducing direction and encodes an outer code in a direction orthogonal to the inner code.
Therefore, the decoding process of the inner code is performed first, and the decoding process of the outer code is performed after the array is rearranged. Each of the audio data, the video data, and the subcode is independently encoded with a product code. In FIG.
After the C decoder 76, only the configuration of audio data processing is shown.

The data decoded by the ECC decoder 76 and an error flag indicating whether or not each sample has an error are stored in the memory 77. A deshuffling circuit 78 is connected to the memory 77, and a deshuffling process reverse to the shuffling performed during recording is performed. A concealing circuit 79 is connected to the deshuffling circuit 78. The concealing flag (error flag) is also supplied to the concealing circuit 79, and the concealing is performed so that the error sample is not conspicuous in the reproduced sound. The output of concealing circuit 79 is D / A converter 80
Supplied to A reproduced audio signal is obtained from the D / A converter 80.

FIG. 10 shows an example of the configuration of the concealing circuit 79. The upper input terminal supplies 16-bit audio data per sample, and the lower input terminal supplies a conceal flag indicating whether or not each sample has an error. The audio data is supplied to the product-sum operation circuit 92 and the conceal flag is set to the error pattern detection circuit 9.
0 is supplied. The error pattern detection circuit 90 detects an error pattern from temporally continuous concealing flags. The information of the detected error pattern is stored in the coefficient memory 9.
1 is supplied.

An interpolation coefficient is stored in advance in the coefficient memory 91 in correspondence with the error pattern. When information on the detected error pattern is supplied, the corresponding interpolation coefficient is read and read. The interpolation coefficient thus obtained is supplied to the product-sum operation circuit 92. The product-sum operation circuit 92 performs an operation of a linear combination expression of an interpolation coefficient and data, similarly to the operation of the digital filter. At the output terminal, concealed reproduced audio data is obtained.

FIG. 11 shows an example of the product-sum operation circuit 92. As shown in FIG. 11, each sample of audio data is sequentially supplied from an input terminal to a series circuit of delay elements Z 素 子 (−1). The delay element Z ＾ (− 1) is 1
Eight delay elements have a sample period delay time and are connected in series. Therefore, at each tap derived from the series circuit of the delay elements, nine temporally continuous audio samples a-4 to a4 are taken out. These tap outputs are supplied to multipliers, and each multiplier multiplies the interpolation output by the interpolation coefficients k-4 to k4 from the coefficient memory 91. The multiplied outputs are added by an adder, and an audio signal is extracted from the adder to an output terminal.

Note that a0 represents the sample data of interest to be interpolated, and the data temporally preceding this data is
a-1, a-2,..., and the subsequent data are a1, a2,. The error pattern (concealed flag) indicates the presence or absence of an error in these samples.
“1” indicates that there is an error. The simplest interpolation formula is linear, which is mean value interpolation. The highest interpolation formula is 7
Next. In the case of average value interpolation, the value of a point passing through two points a-1 and a1 is obtained. In the seventh-order interpolation, a polynomial passing through eight points a-4 to a4 is obtained by the Lagrangian method, and the equation is obtained. Simplified, we have the formula to find the interpolated value of a0.

[0011]

However, in the above-described method, when an error sample is to be interpolated by, for example, a 7th-order polynomial, data obtained by multiplying data of four samples before and after the error sample by the number of channels is held. For this purpose, a circuit such as a shift register is required, and if this is to be realized by a logic LSI, there is a problem that the circuit scale becomes large.

The present invention has been made in view of such a situation, and an error sample interpolation process is performed by a logic LS.
If it is to be realized with I, the circuit size can be reduced. Also, as a result, logic
The price of LSI can be reduced.

[0013]

According to a first aspect of the present invention, there is provided a digital audio signal processing apparatus for interpolating error samples of digital audio data, wherein the digital audio signal processing apparatus performs a deshuffling process on the digital audio data. Shuffling means, error pattern detecting means for detecting an error pattern of a plurality of samples including an error sample, interpolation coefficient selecting means for selecting an interpolation coefficient corresponding to the error pattern detected by the error pattern detecting means, and interpolation coefficient selecting means. Interpolating means for interpolating an error sample using the selected interpolation coefficient.

According to a third aspect of the present invention, in the digital audio signal processing method for interpolating error samples of digital audio data, a deshuffling step of performing a deshuffling process on the digital audio data; An error pattern detection step of detecting an error pattern of a plurality of samples including the interpolation pattern, an interpolation coefficient selection step of selecting an interpolation coefficient corresponding to the error pattern detected in the error pattern detection step, and an interpolation coefficient selected in the interpolation coefficient selection step And an interpolation step of interpolating the error sample using

According to a fourth aspect of the present invention, there is provided a digital audio signal processing apparatus for interpolating an error sample of digital audio data, a deshuffling step of performing a deshuffling process on the digital audio data, and a plurality of media including error samples. An error pattern detection step of detecting an error pattern of a sample, an interpolation coefficient selection step of selecting an interpolation coefficient corresponding to the error pattern detected in the error pattern detection step, and an interpolation coefficient selected in the interpolation coefficient selection step A program for executing a process including an interpolation step of interpolating an error sample is provided.

In the digital audio signal processing apparatus according to the first aspect, the deshuffling means performs a deshuffling process on the digital audio data, and the error pattern detecting means detects an error pattern of a plurality of samples including an error sample. Detected, the interpolation coefficient selection means selects an interpolation coefficient corresponding to the error pattern detected by the error pattern detection means, and the interpolation means interpolates the error sample using the interpolation coefficient selected by the interpolation coefficient selection means.

In the digital audio signal processing method according to the third aspect and the providing medium according to the fourth aspect,
In the deshuffling step, digital audio data is subjected to a deshuffling process, an error pattern detection step detects error patterns of a plurality of samples including an error sample, and an interpolation coefficient selection step detects the error pattern in the error pattern detection step. Select the interpolation coefficient corresponding to the error pattern, and in the interpolation step,
The error sample is interpolated using the interpolation coefficient selected in the interpolation coefficient selection step.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. In order to clarify the correspondence between each means of the invention described in the claims and the following embodiments, When the features of the present invention are described by adding the corresponding embodiments (however, examples) in parentheses after the means, the following is obtained.
However, of course, this description does not mean that each means is limited to those described.

The digital audio signal processing device according to the first aspect of the present invention is a digital audio signal processing device for interpolating error samples of digital audio data, wherein the deshuffling means (for example, FIG. 6) and error pattern detecting means for detecting an error pattern of a plurality of samples including an error sample (for example, the error data detection decoder 40 and the error pattern holding register 4 shown in FIG. 6).
1), an interpolation coefficient selection means for selecting an interpolation coefficient corresponding to the error pattern detected by the error pattern detection means (for example, the interpolation coefficient table 42 shown in FIG. 6), and an interpolation coefficient selected by the interpolation coefficient selection means. Interpolation means (for example, a multiplier 44 shown in FIG. 6)
And an adder 45).

FIG. 1 is a block diagram showing a configuration of an embodiment of a digital audio signal processing apparatus according to the present invention. The mechanical deck 1 includes a pair of magnetic heads (not shown) attached to the rotating drum at an angular interval of 180 °, a magnetic tape (not shown) drawn from a tape cassette and wound around the rotating drum, and a magnetic tape. , And a tape traveling mechanism (not shown) for traveling along a predetermined path. A reproduction signal from the mechanical deck 1 is supplied to an equalizer 3 via a reproduction amplifier 2. The output of the equalizer 3 is supplied to a demodulator 4 for channel coding and a PLL 6. For channel coding, for example, a method of converting a 24-bit information word into a 25-bit code word is used. The output of the demodulator 4 is supplied to the sync / ID detection circuit 5. The recording data has a sync block configuration. The sync block has a sync at the beginning, an ID is added after the sync, data (video data, audio data, or subcode) is positioned after the ID, and an inner code of an inner code added in sync block units thereafter. It has a data structure where the parity is located. The PLL 6 reproduces a clock synchronized with the reproduced signal, and outputs this clock to the demodulator 4.
And to the sync / ID detection circuit 5.

The output signal of the sync / ID detection circuit 5 is ECC
The data is supplied to the decoder 7. The ECC decoder 7 decodes the error correction code and corrects an error sample. For example, a product code is used as the error correction code. The product code encodes an inner code in the recording / reproducing direction and encodes an outer code in a direction orthogonal to the inner code. Therefore, the decoding process of the inner code is performed first, and the decoding process of the outer code is performed after the array is rearranged. Each of the audio data, the video data, and the subcode is independently encoded with a product code. In FIG. 1, after the ECC decoder 7, only the configuration of processing of audio data is shown.

The data decoded by the ECC decoder 7 is supplied to an error data interpolation processing circuit 8. The error data interpolation processing circuit 8 performs deshuffling processing and interpolation processing and supplies the result to the D / A converter 9. The D / A converter 9 converts a digital signal into an analog signal and outputs a reproduced audio signal.

FIG. 2 is a diagram for explaining processing of audio data when a digital VCR is reproduced.
As shown in FIG. 2A, signals are alternately recorded on a magnetic tape by a pair of magnetic heads, and diagonal tracks are sequentially formed. In the case of a video signal of a 525 (line) / 60 (field) system, a video signal and an audio signal for one frame are recorded as ten tracks. For these tracks,
Track numbers 0 to 9 are assigned. Each track has a video sector in which video data is recorded and an audio sector in which audio data is recorded. The audio signal is digitized at a sampling frequency of 48 kHz, 44.1 kHz, or 32 kHz, with one sample being 16 bits.
In the first five tracks of the ten tracks, a signal of one channel (CH1) of digital audio signals of two channels (for example, left and right channels) is recorded, and in the latter five tracks, the other channel (CH1) is recorded. C
H2) signal is recorded.

All data, including audio data,
It is recorded for each video frame with reference to the video system clock (FIG. 2B). Next, only audio data is extracted from all data on the basis of the video system clock (FIG. 2C). In this state, since the audio data has lost temporal continuity, the data transfer clock is switched to the audio system clock. Further, at this time, a deshuffling process reverse to the shuffling process performed at the time of recording is also performed (FIG. 2).
(D)).

FIG. 3 shows an example of a shuffling pattern of audio data. In this shuffling pattern, one frame has 10 tracks (track 0).
525/60 system recorded on tracks 9). In FIG. 3, D0 to D1
Reference numeral 619 denotes the number of an audio sample included in one frame. The audio sample of each channel is, for example, 16 bits. i indicates the sync block number in the track, and j indicates the byte position number in the sync block. FIG. 3 shows a two-channel mode in which audio data of one channel is recorded in the first five tracks and audio data of the other channel is recorded in the second five tracks.

Five consecutive samples of each channel, for example, D0 to D4 are Track 0 (or Track 5), Track 2 (or Track 7), Track 4 (or Track 9), Track 1 (or Track 6), and Track 3. (Or track 8). At the same time, the position of the sync block recorded in each track is sequentially shifted. Such shuffling reduces erroneous consecutive audio samples.

A circuit for realizing the above-described deshuffling processing using a frame memory will be described. FIG.
3 shows a configuration example of a frame memory (for one channel). Since the shuffling process specified in the DV format is performed for each frame, when performing the deshuffling process, it is necessary to hold at least one frame of audio data at a time. Furthermore, since the audio data must be output to the baseband system at the same time as the audio data is supplied (because the output to the baseband side is continuous and continuous in time), two frame memories are required. I'm using

The data supplied from the tape reproducing system includes a mixture of video data and audio data, and is synchronized with the video system clock. The switch 26 switches at a frame period, and supplies data to the frame memories 20 and 21 alternately. The frame memory on which the switch 26 is ON has a frame memory control circuit 1
The write address generation circuit 22 and the write permission timing generation circuit 24 in 0 supply a write address synchronized with the video system clock and a write permission timing pulse for notifying the timing at which audio data exists in the input data. . A video clock is also supplied. Based on these,
The frame memory control circuit 10 writes one frame of audio data into the frame memory.

A read address synchronized with the audio system clock is supplied from the read address generation circuit 23 in the frame memory control circuit 10 to the frame memory on the opposite side to the above-mentioned frame memory. An audio system clock is also supplied. Based on these, the frame memory control circuit 10 reads audio data for one frame from the frame memory and supplies it to the baseband system circuit.

The switches 26 to 32 are switched at a frame cycle, and the frame memory control circuit 10 always
Writing is performed in one frame memory, and reading is performed in the other frame memory.

The write address generation circuit 22 generates a write address simply by incrementing it from the start address, and supplies it to the frame memory. The read address generation circuit 23 generates an address in an order reverse to the shuffling order specified in the DV format, and supplies the generated address to the frame memory. As a result, deshuffling is realized.

The flip-flop 25 switches the audio data after the deshuffling supplied via the switch 32 to an audio sampling period and outputs the audio data to the baseband system.

FIG. 5 is a timing chart for explaining the operation of the frame memory shown in FIG. This timing chart shows a case where audio data of the first five tracks (CH1) is reproduced. In the frame memory 20, when the switch 26 is ON, only the audio data of the data supplied from the tape reproduction system is written in synchronization with the video system clock. When the switch 26 is OFF, audio data written when the switch 26 is ON is read out in synchronization with the audio system clock (FIG. 5C). At this time, a deshuffling process is also performed at the same time.

In the frame memory 21, writing and reading of audio data are performed by the frame memory 20 described above.
(D in FIG. 5D).

LRCK (FIG. 5E) is, for example, 48 kHz.
3 shows an audio sampling clock of z. AD
S (FIG. 5 (F)) indicates a read address,
Address 217,649,1405,541,973
109, 865, 1297, and 433 are in an order in which deshuffling is considered. DATA (Fig. 5 (G))
The figure shows output data of the flip-flop 25, and outputs the audio data read out in the order of the addresses in synchronization with the audio sampling clock.

FIG. 6 is a block diagram showing an example of the error data interpolation processing circuit 8 of FIG. The configurations of the frame memory control circuit 10 and the frame memories 20 and 21 are the same as those of FIG. The error data detection decoder 40 is supplied with audio sample data (16 bits) after deshuffling from the frame memory. Error data detection decoder 4
If the supplied audio sample data is determined to be an error, “0” is output, and if it is determined that the supplied audio sample data is not an error, “0” is output.

The error pattern holding register 41 is composed of nine flip-flops (FF50 to FF58). One-bit error information supplied from the error data detection decoder 40 is first latched by the FF 50. Next, the supplied error information is latched by the FF 51. Similarly, error information for nine samples is sequentially taken into FF50 to FF58.

The interpolation coefficient conversion table 42 outputs nine interpolation coefficients corresponding to the error pattern composed of nine samples supplied from the error pattern holding register 41.

The selector switch 43 selects the nine interpolation coefficients supplied from the interpolation coefficient conversion table 42 in order and supplies them to the multiplier 44.

To the multiplier 44, nine interpolation coefficients and audio data corresponding thereto are supplied at the same timing. The multiplier 44 multiplies the interpolation coefficient by the audio data corresponding to the interpolation coefficient and supplies the result to the adder 45.

The data supplied from the multiplier 44 is added by a loop adder composed of the adder 45 and the FF 59 to obtain, for example, audio data interpolated by an interpolation formula as shown in FIG. Can be. The switch 46 is for clearing the accumulated value of the loop adder to zero.

FIG. 8 shows the operation timing of the error data interpolation circuit 8. FIG.
The case where the error data of 73 is interpolated and output to the baseband side is shown. The error data interpolation processing circuit 8 first reads audio data of 9 samples in order from the frame memory, detects an error pattern, prepares an interpolation coefficient corresponding to the error pattern, and then reads data of 9 samples again. While performing the product-sum operation, the interpolation process is performed.

LRCK indicates an audio sampling clock, and ADS indicates a read address. In the conventional reproduction, the address 97 in this one sampling period is used.
In this embodiment, it is sufficient to read the data No. 3 once. However, in the present embodiment, the read cycle is accelerated to read the address 973 and the data of four samples before and after the address 973.
A total of 18 times, two times within the sampling period.
The 18 readings need only be within one sampling period, and the addressing period does not necessarily have to be as shown in FIG.

The reading from the first address 217 to 433 is for detecting an error pattern of four samples before and after the data at the address 973. The reading from the next address 217 to 433 is performed by using the prepared interpolation coefficient. Is read in order to perform a product-sum operation with.

In this embodiment, for example, 7
In the case of the next interpolation, when interpolating the data from the beginning of the frame to the fourth and the data from the end of the frame to the fourth,
In some cases, data necessary for the interpolation calculation is stored in the opposite frame memory. Therefore, in the actual processing, the time for supplying the audio system clock and the read address needs to be slightly longer before and after the frame period. Further, the switch of the frame period needs to be shifted to the left from the frame change point so that the write timing and the read timing do not batter.

As described above, in the present embodiment, the case where the present invention is applied to a digital VCR has been described.
The present invention is also applicable to interpolation of error data in T, CD, DVD, and the like.

As for shuffling of data,
The present invention can be applied to cases other than those described above.

In the present specification, a providing medium for providing a user with a computer program for executing the above processing includes an information recording medium such as a magnetic disk and a CD-ROM, and a network such as the Internet and a digital satellite. Transmission media is also included.

[0049]

As described above, according to the digital audio signal processing apparatus according to the first aspect, the digital audio signal processing method according to the third aspect, and the providing medium according to the fourth aspect, interpolation of error samples is performed. Since the processing is performed using the frame memory, the circuit scale can be reduced. As a result, the price of the device can be set low.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a digital audio signal processing device of the present invention.

FIG. 2 is a conceptual diagram of deshuffling when reproducing audio data.

FIG. 3 is a diagram illustrating an example of a shuffling pattern of audio data.

FIG. 4 is a block diagram illustrating a configuration of a frame memory.

FIG. 5 is a timing chart for explaining the operation of the frame memory.

FIG. 6 is a diagram for explaining the error data interpolation processing circuit 8 of FIG. 1;

FIG. 7 is a diagram illustrating an example of a correspondence relationship between an error pattern and an interpolation formula;

FIG. 8 is a timing chart for explaining an operation of the error data interpolation processing circuit 8 of FIG. 6;

FIG. 9 is a block diagram showing an example of a configuration of a conventional digital audio signal processing device.

FIG. 10 is a diagram for explaining the concealing circuit 79 of FIG. 9;

11 is a diagram for explaining the product-sum operation circuit 92 in FIG.

[Explanation of symbols]

1,70 mechanical deck, 2,71 playback amplifier,
3,72 equalizer, 4,73 24-25 demodulator,
5,74 SINK / ID detection circuit, 6,75 PLL,
7, 76 ECC decoder, 8 error data interpolation processing circuit, 9, 80 D / A converter, 10 frame memory control circuit, 20, 21 frame memory, 2
2 write address generation circuit, 23 read address generation circuit, 24 write permission timing generation circuit, 25 flip-flops, 26 to 32 switches, 40 error data detection decoder, 41 error pattern holding register, 42 interpolation coefficient table,
43 selector switch, 44 multiplier, 45
Adder, 46 switches, 50 to 60 flip-flops, 77 memory, 78 deshuffle circuit, 79 concealment circuit, 90 error pattern detection circuit, 91 coefficient memory, 92 product-sum operation circuit

Claims (4)

[Claims] 1. A digital audio signal processing device for interpolating error samples of digital audio data, a deshuffling means for performing a deshuffling process on the digital audio data, and detecting an error pattern of a plurality of samples including the error samples. Error pattern detecting means, an interpolation coefficient selecting means for selecting an interpolation coefficient corresponding to the error pattern detected by the error pattern detecting means, and interpolating the error sample using the interpolation coefficient selected by the interpolation coefficient selecting means. A digital audio signal processing device comprising: an interpolation unit. 2. The digital audio signal processing device according to claim 1, wherein said deshuffling means is a frame memory. 3. A digital audio signal processing method for interpolating error samples of digital audio data, wherein: a deshuffling step of performing a deshuffling process on the digital audio data; and detecting an error pattern of a plurality of samples including the error samples. An error pattern detecting step, an interpolation coefficient selecting step of selecting an interpolation coefficient corresponding to the error pattern detected in the error pattern detecting step, and the error sample using the interpolation coefficient selected in the interpolation coefficient selecting step. An interpolating step of interpolating. 4. A digital audio signal processing device for interpolating error samples of digital audio data, a deshuffling step of performing a deshuffling process on the digital audio data, and detecting an error pattern of a plurality of samples including the error samples. An error pattern detecting step, an interpolation coefficient selecting step of selecting an interpolation coefficient corresponding to the error pattern detected in the error pattern detecting step, and the error sample using the interpolation coefficient selected in the interpolation coefficient selecting step. A providing medium for providing a program for executing a process including an interpolation step of interpolating.