JPH11249887A - Program correcting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To configure this device without increasing a circuit scale and to almost limitlessly correct the number of program correctable address places without being affected by the limitation of the hardware of a built-in microcomputer. SOLUTION: In a program stored in a ROM 3, a program correction processing specification instruction is arranged in every head of a subroutine program whose correction is preliminarily estimated. A ROM correction functioning part 5 decides the existence of program correction processing from program counter(PC) value when the correction processing is called and correction program data stored in an EEPROM 7, reads the correction program data of the EEPROM 7 in the case of needing correction processing and stores the read correction program data in a RAM 4 at a correcting ROM address 1 corresponding to the leading address of a correcting ROM 3 program and a CPU 2 executes what is after the leading address of the program based on the correction program data stored in the RAM 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program correction method for an embedded microcomputer, and more particularly to a program correction method suitable for performing a program correction process without limiting the number of ROM addresses at which the program can be corrected to the hardware of the embedded microcomputer. It relates to a correction device.

[0002]

2. Description of the Related Art In general, as a method of correcting a program in an embedded microcomputer, a necessary program is stored in a read-only memory (hereinafter referred to as a ROM).
When the system is started, execution of the program is started from a specific address in the ROM content. However, in such a program correction method, the embedded program is
If an attempt is made to change a program stored in the OM but in the ROM to correct an error, R
All programs in the OM must be rewritten.

In view of the above problem, even if there is an error in the embedded program in the ROM, the embedded program is executed without rewriting, and a method of using the program correction function is disclosed in Japanese Patent Application No. Hei 4-137713.
No. 6 proposes a proposal.

In the program storage method according to this proposal,
In a program storage method of an embedded program, a central processing unit (hereinafter, referred to as a CPU) and a random access memory (hereinafter, a RAM) accessible from the CPU are used.
), A first ROM storing change information of the embedded program, a rewritable second ROM storing change information of the embedded program, and the first ROM.
A base address generation unit that stores a base address when writing OM data to the RAM;
An address generator for adding an address of the base address generator and a relative address stored in a second ROM to generate an address for writing data to the RAM; A RAM writing unit that writes stored information to an address generated by the address generation unit, and an instruction from the CPU,
A rewritable ROM writer for rewriting information stored in the second ROM.

In the above configuration, an electrically erasable programmable ROM (hereinafter referred to as EEP) is used as the second ROM.
And an address for writing data to the RAM by adding the relative address stored in the first ROM and the EEPROM and the address of the base address generation unit by an address generation unit. The first RO is generated by the RAM writing unit.
The information stored in the M and the EEPROM is written to the address generated by the address generator. The rewritable ROM writing unit, that is, the EEPROM writing unit, issues an instruction from the CPU to
Rewrites information stored in the EPROM. Thus, the data stored in the EEPROM can be freely changed by the program of the CPU.

Therefore, according to this proposal, instead of storing the embedded program in the ROM and directly mapping it in the address space of the CPU, the main body of the embedded program is stored in the ROM, and its change (correction) information is stored in the EEPROM.
And transfer it to a RAM accessible from the CPU when the system is started, so that if there is an error in the embedded program, a copy of the embedded program on the RAM can be corrected using the information in the EEPROM without rewriting it. You can modify and run the program.

However, in such a conventional program correction method, if the number of correction ROM address setting functions provided as hardware of the embedded microcomputer is N, correction beyond N is impossible. Also,
If an attempt is made to increase the number of modifiable parts, the circuit scale of the hardware becomes large, and it is also difficult to execute such a part at low cost, especially with a low-cost microcomputer.

For this reason, in the prior art, there is a problem that the number of ROM addresses where the program can be corrected is limited by the hardware of the microcomputer.

[0009]

As described above, in the conventional program correction method, if the correction ROM address setting function prepared as hardware of the embedded microcomputer has N locations, correction beyond the N locations is impossible. Yes,
In addition, if the number of possible locations is increased, the circuit scale of the hardware becomes large. In particular, it is difficult to execute the hardware at a low cost with a low cost microcomputer. There was a problem that it was limited by hardware.

Therefore, the present invention has been made in view of the above problems, and can be configured without increasing the circuit scale. The number of address locations that can be programmed is almost infinite without being limited by the hardware of the embedded microcomputer. It is an object of the present invention to provide a program correction device which can be performed in a computer.

[0011]

A program correction apparatus according to the present invention stores a CPU and a program for executing the CPU and in which a program correction processing instruction is arranged at each head of a subroutine program which is expected to be corrected in advance. A non-rewritable first ROM, a rewritable RAM accessible from the CPU for storing and loading correction program data for correcting the program, and storing the correction program data. A rewritable second ROM, capable of controlling a program correction process required to correct a program in the first ROM, a program counter value when the program correction process is instructed, and the correction program It is determined from the data whether or not the program has been modified, and If it is necessary, the in the second modification program data ROM read, said modifying the read patch data first address corresponding to the start address of the program ROM RA
M for controlling the CPU to execute the program based on the correction program data stored in the RAM after the start address of the program in the first ROM.
And a correction function unit.

In the present invention, the second ROM includes:
An electrically erasable programmable read only memory (EEPROM) storing correction program data. When a program correction occurs, the correction program data is read by the ROM correction function unit and transferred to the RAM. Stored. The first RO
In the program stored in M, a program correction processing instruction is arranged for each head of a subroutine program that is expected to be corrected in advance. For this reason, the ROM correction function unit determines the presence or absence of the correction processing of the program from the program counter value at the time of instructing the program correction processing and the correction program data, and when the correction processing is necessary, Reading the correction program data from the second ROM, storing the read correction program data in the RAM at an address corresponding to the start address of the program in the first ROM, and starting the start address of the program in the first ROM Thereafter, the CPU is controlled so as to be executed by the CPU based on the correction program data stored in the RAM. Therefore, such a program correction process can be executed many times before each subroutine process in the program. As a result, the embedded microcomputer can be configured without increasing the circuit scale, and the number of addresses at which the program can be corrected can be almost infinite without being limited by the hardware of the embedded microcomputer.

[0013]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a program correction device according to the present invention, and showing the entire configuration of a built-in microcomputer constituting the device and its peripheral circuit section.

As shown in FIG. 1, the program correction device according to the present invention is built in a built-in microcomputer 1 and has a program correction function.

Specifically, the built-in microcomputer 1 includes a CPU 2, a non-rewritable ROM 3 storing a built-in program, a rewritable RAM 4 for loading and storing correction program data,
A ROM correction function unit 5 capable of performing a processing function for correcting the embedded program stored in the ROM 3 and an I / O interface 6 for transmitting data to an externally connected EEPROM 7. Have been.

The EEPROM 7 is connected to the outside of the built-in microcomputer 1 having the above-described configuration via the I / O interface 6. The EEPROM 7 stores correction program information (change of the built-in program) as described in the prior art. Information), and the stored correction program information can be rewritten. EEP
By controlling the I / O interface 6 by the ROM correction function unit 5, the ROM 7 can read stored correction program information and rewrite the correction change information. That is, when the program correction function is executed, the transfer, writing, and reading of the correction program data between the ROMs are performed by the ROM.
Controlled by the correction function unit 5. In the usual case,
The CPU 7 controls the EEPROM 7 and the I / O interface 6.

The record format of the correction program data stored in the EEPROM 7 is, for example, an address where a correction process is arranged as shown in FIG. 2, that is, a program counter (hereinafter, PC ), Correction ROM addresses 1 to n, storage RAM head addresses 1 to n, a correction program data length n and correction program data written from these addresses.

On the other hand, the RAM 4 is a main storage device of the CPU 2 and is mapped in a memory space of the CPU 2, but does not store a program at the time of system startup. The RAM 4 is a rewritable memory for loading and storing the correction program data during the program correction processing. Therefore, at the time of program correction, the correction program data is written into the RAM 4, and since the RAM 4 can be accessed from the CPU 2, the CPU 2 loads the correction program data stored in the RAM 4 to correct the program. The program can be executed.

The ROM 3 stores a built-in program, and the data stored as the built-in program in the ROM 3 can be changed based on the correction by using the correction function of the ROM correction function unit 5.

The ROM correction function unit 5 has a processing function necessary for correcting a program in the embedded microcomputer using the RAM 4 and controls the I / O interface 6 to control the I / O to be performed by the CPU 2. By selecting a port, it is possible to execute rewriting and reading of the correction program information with respect to the EEPROM 7. The configuration of the ROM correction function unit 5 includes, for example, a program correction circuit and the like for executing a correction process and the like for an embedded program stored in the ROM 3. That is, when the program needs to be corrected, the ROM correction function unit 5
The start address (correction ROM address 1) of the program that needs correction is obtained from the correction program information stored in the PROM, this is set, and then the start address (storage RA) of the RAM 4 to which the program correction function jumps is performed.
The M head address 1) is set, and the correction program data is stored in the RAM 4 based on the obtained address.

Next, the operation will be described in detail with reference to FIGS. FIG. 3 is a main flowchart for executing a program correction method by the program correction device. FIG. 4 is an explanatory diagram for explaining the control operation shown in FIG. 3, and FIG. FIG. 4B is a subroutine showing the same correction processing arranged before the execution of the OSD processing, and FIG.
Indicates subroutines indicating the same correction processing arranged before the execution of the VCD processing.

For simplicity, the description will be made assuming that the hardware has only one program correction function. The OSD process is a process related to an on-screen display in a television receiver, and the VCD process is a process related to a video, a chroma, and a deflection.

When the power of the built-in microcomputer 1 is turned on, the CPU 2 starts operation, resets the program in step S10, executes a program stored in the ROM 3, calls a correction process by this program, and The state is recognized by the CPU 2. At this time, the CPU 2 sets the address immediately before performing the correction process to R
Control is performed so that the data is written to, for example, a stack area of the AM 4.

Thereafter, the CPU 2 sends the ROM correction function unit 5
Is notified that a call has been made to the program correction processing, the CPU 2 temporarily stops its operation and
The program correction function of the OM program correction function unit 5 operates, and the program correction processing in step S11 is started.

In the program correction process in step S11, for example, a process shown in a subroutine of FIG. 4A is performed. In other words, the value of the program counter (PC) that called this correction process, that is, the address value stored in the stack area of the RAM 4 is the value of E shown in FIG.
A search is made for a correction program data record stored in the EPROM 7 (step S20), and the subsequent step S20 is executed.
It is determined whether or not they match in the processing by 21. If a match is found, a flag for identifying this, for example, a ROM identification flag is set to "1" and the
The data is transferred to U2 (step S22), a correction program data record corresponding to the PC value is read (step S24), and the subsequent processing is performed. In other words, by performing the process of whether or not they match, it is determined whether or not to execute the program correction process.

In the subsequent processing, the start address (corrected ROM address 1) of the program requiring correction, read from the corrected program data record in the processing in step S25, is set in the ROM correction function unit 5, and the next step In the process in S26, the start address of the RAM 4 (storage RAM start address 1) to which the program correction function jumps is set, and the corrected program data is stored in the RAM 4 based on the obtained address in the process in step S27. Data transfer is performed in the following manner, for example, the main main (in the figure, MAIN is described).
The program correction processing before the processing operation is completed, and the processing shifts to step S12 of the main routine shown in FIG. On the other hand, if no match is found in the judgment processing in step S21, no data is set to, for example, a ROM identification flag of "0" in step S23 shown in the subroutine of FIG. Assuming that the process is not necessary, the process proceeds to step S12 of the main routine shown in FIG.

Then, the CPU 2 is restarted, and step 1 is executed.
For example, the ROM transferred by the determination
It is determined whether or not the identification flag is "1". If the identification flag is "1", it indicates that a correction process was required. The processing (step S12) based on the program stored in the RAM 4 is avoided (jumped), and the corrected program stored in the RAM 4 is stored in the RAM 4
Is loaded and executed, and the processing is performed in the main processing (step S
Go to 14). On the other hand, if the ROM identification flag is "0" in the judgment processing in step 12a, it indicates that no correction processing is necessary, and therefore, the processing operation by the program without correction, that is, the ROM 3
(Step S)
12), and the process proceeds to the main process (Step S14).

In this embodiment, the built-in program stored in the ROM 3 contains, at each head of a main subroutine that is supposed to be corrected in advance, data for instructing the CALL to perform the above-described correction processing. It is included. That is, by arranging at the head, it is possible to correct the program anywhere in the program area in the subroutine. Accordingly, in the present embodiment, for example, as shown in FIG.
It can be executed even before the OSD processing, before the VCD processing, or the like.

Therefore, after executing the main processing, the CPU 2 shifts the processing to the OSD processing in step S15. Before the execution of the OSD processing, the CPU 2 executes the program correction processing by the ROM correction function unit 5 (FIG. 4 (b)). 4), the OSD process (step S15) is executed.

Thereafter, similarly, the CPU 2 executes the OS
After the execution of the D processing, the processing shifts to the VCD processing in step S16. Before the execution of the VCD processing, the program correction processing by the ROM correction function unit 5 (see FIG. 4C,
After the processing is the same as that shown in FIG.
A CD process (step S16) is executed. In addition, EEP
A plurality of PC values stored in the ROM are provided in accordance with the address where the correction processing is arranged.
The PC value of the correction process executed before the process is PC1,
The PC value of the correction processing executed before the subsequent VCD processing is PCn.

As described above, according to the present embodiment, the number of ROM addresses that can be programmed can be determined almost infinitely without being restricted by hardware for executing the program correction function. A program correction device can be provided.

In the embodiment according to the present invention,
EEPROM7 every time the program correction process is CALL
Although the description has been given of the case where the program correction information is read from the program and executed, the present invention is not limited to this. In such a case, the reading of the program correction information from the EEPROM 7 may be performed collectively at the time of starting the system. In this case, the program correction processing of the ROM correction function unit 5 is performed in the program correction process. May be controlled so that only data setting is performed. That is, the operation is performed without executing step S27 shown in FIG.
Therefore, it is clear that the same effects as those of the above-described embodiment can be obtained in such an embodiment.

[0034]

As described above, according to the present invention,
A program correction device that includes a built-in microcomputer can be configured without increasing the circuit scale, and a program correction function is provided that allows the number of addresses that can be corrected to be almost infinite without being limited by the hardware of the built-in microcomputer. It is possible to provide a program correction device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of a program correction device according to the present invention.

FIG. 2 is a view showing a format of a correction program data record in the EEPROM of FIG. 1;

FIG. 3 is a main flowchart for explaining a program correction method by the apparatus of FIG. 1;

FIG. 4 is an explanatory diagram for explaining the correction processing of FIG. 3;

[Explanation of symbols]

1 embedded microcomputer, 2 central processing unit (CPU), 3 read-only memory (ROM), 4 random access memory (RAM), 5 ROM correction function unit, 6 I / O interface, 7 electrical Erasable programmable read only memory (EEPROM).

Claims (3)

[Claims] A non-rewritable first ROM for storing a program in which a program correction processing instruction is arranged at each head of a subroutine program which is to be executed and which is expected to be corrected in advance; A rewritable RAM accessible from the CPU for storing and loading correction program data for correcting the program, a rewritable second ROM storing the correction program data, A program correction process control required to correct the program in the first ROM can be performed, and the presence or absence of the program correction process is determined from the program counter value when the program correction process instruction is given and the correction program data. However, if a correction process is necessary, the second ROM Program data read, said modifying the read patch data first ROM
R is stored in the RAM at an address corresponding to the start address of the first program, and the CPU executes control based on the modified program data stored in the RAM after the first address of the program in the first ROM.
A program correction device comprising: an OM correction function unit. 2. The ROM correction function unit according to claim 1, wherein:
A system that includes transferring the correction program data from the second ROM to the RAM regardless of a program correction processing instruction arranged at the beginning of each subroutine program of the program stored in the OM, including the time of the program initialization processing 2. The program correction apparatus according to claim 1, wherein the program correction is performed collectively at the time of startup, and the necessary address setting for the CPU is performed for each program correction process. 3. The program correction device according to claim 1, wherein the second ROM is an electrically erasable programmable read only memory.