JPH11233571A - Semiconductor device, underfill material, and thermosetting film material - Google Patents

Semiconductor device, underfill material, and thermosetting film material

Info

Publication number
JPH11233571A
JPH11233571A JP2951098A JP2951098A JPH11233571A JP H11233571 A JPH11233571 A JP H11233571A JP 2951098 A JP2951098 A JP 2951098A JP 2951098 A JP2951098 A JP 2951098A JP H11233571 A JPH11233571 A JP H11233571A
Authority
JP
Japan
Prior art keywords
circuit board
silicon chip
weight
thermosetting
chem
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2951098A
Other languages
Japanese (ja)
Inventor
Enjiyou Tsuyuno
円丈 露野
Toshiaki Ishii
利昭 石井
Akira Nagai
永井  晃
Takumi Ueno
巧 上野
Kuniyuki Eguchi
州志 江口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2951098A priority Critical patent/JPH11233571A/en
Publication of JPH11233571A publication Critical patent/JPH11233571A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Landscapes

  • Compositions Of Macromolecular Compounds (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To remove a silicon chip without damage at a low temperature and small shearing force while maintaining a high temperature cycle reliability by specifying a shearing bond strength of a silicon chip and a circuit board. SOLUTION: A solder bump electrode 2 of a silicon chip 1 is positioned to a land of a circuit board 3 and is subjected to solder connection by IR reflow. Thereafter, a clearance between an electronic part and the circuit board 3 is filled with thermosetting resin composition 4 prepared by a specific method and is set, and a semiconductor device is produced. That is, in the semiconductor device, shearing bond strength of the silicon chip 1 and the circuit board 3 is set at 5 MPa or more at 25 deg.C and at 1 MPa or less at 250 deg.C. Straight chain aliphatic hydrocarbon compound of 10C-30C or less which is chemically bound to thermosetting resin is added to the thermosetting resin composition 4 which sticks the silicon chip 1 to the circuit board 3.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は面実装半導体装置,
モジュールならびにリペア法、及びアンダーフィル材に
関する技術分野に属する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount semiconductor device,
It belongs to the technical field of modules and repair methods, and underfill materials.

【0002】[0002]

【従来の技術】樹脂によって回路基板に固定された電子
部品の基板からのリペアに関しては、特開昭61−269318
号公報,特開平6−5664号公報に開示がある。また、Rep
airbility of underfill encapsulated Flip−Chip pac
kages IEEE,524−528,1995がある。
2. Description of the Related Art Japanese Patent Application Laid-Open No. 61-269318 discloses a method for repairing an electronic component fixed on a circuit board by a resin.
And Japanese Patent Application Laid-Open No. 6-5664. Also, Rep
airbility of underfill encapsulated Flip−Chip pac
kages IEEE, 524-528, 1995.

【0003】[0003]

【発明が解決しようとする課題】しかし、特開昭61−26
9318号公報のように熱可塑性樹脂を用いる方式はリペア
には優れるが、リフロー後の温度サイクル信頼性が悪い
という問題がある。また、特開平6−5664 号公報のよう
に単なる熱硬化性樹脂を用い、熱劣化によりシリコンチ
ップを取り外すリペア方法は、チップ取り外し工程で高
温と高剪断力が必要であり、大型のシリコンチップを用
いた場合、剪断力でチップが破壊してしまったり、樹脂
の回路基板を用いた場合、高温で回路基板が劣化,変形
してしまったりして有効ではない。
SUMMARY OF THE INVENTION However, Japanese Patent Application Laid-Open No. 61-26
The method using a thermoplastic resin as disclosed in Japanese Patent No. 9318 is excellent in repair, but has a problem in that the temperature cycle reliability after reflow is poor. Further, a repair method of removing a silicon chip by thermal degradation using a mere thermosetting resin as disclosed in Japanese Patent Application Laid-Open No. 6-5664 requires a high temperature and a high shearing force in a chip removing step, and a large silicon chip is required. When used, the chip is broken by shearing force, and when a resin circuit board is used, the circuit board is deteriorated or deformed at high temperatures, which is not effective.

【0004】従って、本発明は上述した従来の問題点に
鑑みなされたもので、その目的は高い温度サイクル信頼
性を有しながら、低い温度,小さな剪断力で、また、シ
リコンチップや回路基板を損傷することなくシリコンチ
ップの取り外しが出来る半導体装置を提供することにあ
る。
SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above-mentioned conventional problems, and has as its object to provide a high temperature cycle reliability, a low temperature, a small shear force, and a silicon chip or circuit board. An object of the present invention is to provide a semiconductor device from which a silicon chip can be removed without being damaged.

【0005】[0005]

【課題を解決するための手段】本発明の目的は、以下の
手段によって達成される。
The object of the present invention is achieved by the following means.

【0006】シリコンチップの能動面を回路基板側に向
け導電性材料を介して回路基板に電気的に接続しシリコ
ンチップと回路基板の間隙を熱硬化性樹脂組成物で充填
硬化した半導体装置においてシリコンチップと回路基板
の剪断接着強度が25℃で5Mpa以上、250℃で1
Mpa以下である事を特徴とする半導体装置により達成
できる。
In a semiconductor device in which the active surface of the silicon chip is directed toward the circuit board and electrically connected to the circuit board via a conductive material, the gap between the silicon chip and the circuit board is filled with a thermosetting resin composition and cured. The chip and the circuit board have a shear adhesive strength of 5 Mpa or more at 25 ° C. and 1 at 250 ° C.
Mpa or less can be attained by a semiconductor device characterized by being below Mpa.

【0007】これは、25℃でシリコンチップと回路基
板の剪断接着強度5Mpa以上であれば、半導体装置の
使用時にシリコンチップと回路基板は十分接着している
ため、高い信頼性を維持出来る。また、不良などの発生
によりシリコンチップを取り外す必要が生じたとき、シ
リコンチップと回路基板の剪断接着強度が250℃で1
Mpa以下であれば、250℃に加熱し、剪断力を加え
ることで、シリコンチップを損傷する事無くシリコンチ
ップの取り外しができる。また、250℃での10分以
下の加熱であれば、有機回路基板を用いても基板の劣化
や変形は少なく、十分再利用できるためである。
If the shear strength between the silicon chip and the circuit board at 25 ° C. is 5 Mpa or more, the silicon chip and the circuit board are sufficiently bonded when the semiconductor device is used, so that high reliability can be maintained. Further, when it becomes necessary to remove the silicon chip due to the occurrence of a defect or the like, the shear adhesive strength between the silicon chip and the circuit board is 1 at 250 ° C.
If it is not more than Mpa, the silicon chip can be removed without being damaged by heating to 250 ° C. and applying a shearing force. In addition, if the heating is performed at 250 ° C. for 10 minutes or less, even if an organic circuit substrate is used, deterioration and deformation of the substrate are small, and the substrate can be sufficiently reused.

【0008】この様に、シリコンチップと回路基板の剪
断接着強度が、25℃で5Mpa以上、250℃で1M
pa以下となる半導体装置は、シリコンチップと回路基
板を接着している熱硬化性樹脂組成物に熱硬化性樹脂と
化学結合する炭素原子数10以上30以下の直鎖状脂肪
族炭化水素化合物を含有することにより達成できる。
As described above, the shear adhesive strength between the silicon chip and the circuit board is 5 Mpa or more at 25 ° C. and 1 M at 250 ° C.
In a semiconductor device having a pa or less, a linear aliphatic hydrocarbon compound having 10 to 30 carbon atoms chemically bonded to a thermosetting resin is added to a thermosetting resin composition bonding a silicon chip and a circuit board. It can be achieved by containing.

【0009】[0009]

【化10】 ―R1 1=Cn2n+1 …(化10) 10≦n≦30(nは正数)Embedded image —R 1 R 1 = C n H 2n + 1 (Formula 10) 10 ≦ n ≦ 30 (n is a positive number)

【0010】[0010]

【化11】 ―R1−O−R2― R1=Cn2n+1 2=Cm2m+1 …(化11) 10≦n+m≦30(n,mは正数)Embedded image —R 1 —O—R 2 —R 1 = C n H 2n + 1 R 2 = C m H 2m + 1 (Formula 11) 10 ≦ n + m ≦ 30 (n and m are positive numbers)

【0011】[0011]

【化12】 Embedded image

【0012】上記の様にして目的が達成できる理由は、
熱硬化性樹脂と化学結合した炭素原子数10以上30以
下の直鎖状脂肪族炭化水素化合物(化10),(化1
1),(化12)は熱硬化性樹脂組成物の硬化物がTg
より低温のガラス状態の時、硬化物の剪断接着強度をほ
とんど低下させないのに対し、熱硬化性樹脂組成物の硬
化物がTgより高温のゴム状態の時、硬化物の剪断接着
強度を大きく低下させるためである。
The reason why the object can be achieved as described above is as follows.
A linear aliphatic hydrocarbon compound having 10 to 30 carbon atoms chemically bonded to a thermosetting resin (Chemical Formula 10), (Chemical Formula 1)
1) and (Chem. 12) show that the cured product of the thermosetting resin composition is Tg.
When the glass is at a lower temperature, the shear bond strength of the cured product is hardly reduced. On the other hand, when the cured product of the thermosetting resin composition is in a rubber state having a temperature higher than Tg, the shear bond strength of the cured product is significantly reduced. It is to make it.

【0013】この理由は、硬化物の凝集力の強いガラス
状態では、直鎖状脂肪族炭化水素の運動は硬化物の凝集
力に拘束され、硬化物全体の接着強度にあまり影響を与
えないが、硬化物の凝集力が低下したゴム状態では、直
鎖状脂肪族炭化水素は激しく運動し、硬化物全体の接着
強度を大きく低下させるものと考えられる。
The reason is that, in the glass state of the cured product having a strong cohesive force, the motion of the linear aliphatic hydrocarbon is restricted by the cohesive force of the cured product and does not significantly affect the adhesive strength of the entire cured product. On the other hand, in the rubber state in which the cohesive force of the cured product is reduced, it is considered that the linear aliphatic hydrocarbon moves violently and greatly reduces the adhesive strength of the entire cured product.

【0014】この直鎖状脂肪族炭化水素化合物の炭素原
子数が10より少ない場合、ゴム状態の接着力の低下効
果がほとんどなく、炭素原子数が30より大きくなると
熱硬化性樹脂組成物に分散混練する作業性が悪くなって
しまう。このため、直鎖状脂肪族炭化水素化合物の炭素
原子数を10以上30以下にする事が望ましい。
When the number of carbon atoms of the linear aliphatic hydrocarbon compound is less than 10, there is almost no effect of lowering the adhesive force in a rubber state, and when the number of carbon atoms is more than 30, it is dispersed in the thermosetting resin composition. The workability of kneading becomes worse. For this reason, it is desirable that the number of carbon atoms of the linear aliphatic hydrocarbon compound be 10 or more and 30 or less.

【0015】この様な、直鎖状脂肪族炭化水素化合物は
樹脂成分の総重量の20重量%以上90重量%以下含有
させた時最も効果を発揮する。それは、含有量が樹脂成
分の総重量の20重量%より少ないとゴム状態の接着力
の低下効果がほとんどなく、チップ取り外し時に大きな
剪断力が必要となり、チップ損傷を招いてしまう。一
方、含有量が90重量%以上だと、ガラス状態の接着力
も低下してしまうため温度サイクル信頼性が低下してし
まうためである。
Such a linear aliphatic hydrocarbon compound is most effective when contained in an amount of from 20% by weight to 90% by weight based on the total weight of the resin component. If the content is less than 20% by weight of the total weight of the resin component, there is almost no effect of lowering the adhesive force in the rubber state, and a large shearing force is required at the time of chip removal, resulting in chip damage. On the other hand, if the content is 90% by weight or more, the adhesive strength in a glassy state is also reduced, so that the temperature cycle reliability is reduced.

【0016】[0016]

【化13】 ―R1 1=Cn2n+1 …(化13) 8≦n≦30(nは正数)Embedded image -R 1 R 1 = C n H 2n + 1 (Formula 13) 8 ≦ n ≦ 30 (n is a positive number)

【0017】[0017]

【化14】 ―R1−O−R2― R1=Cn2n+1 2=Cm2m+1 …(化14) 8≦n+m≦30(n,mは正数)Embedded image —R 1 —O—R 2 —R 1 = C n H 2n + 1 R 2 = C m H 2m + 1 (Formula 14) 8 ≦ n + m ≦ 30 (n and m are positive numbers)

【0018】[0018]

【化15】 Embedded image

【0019】また、炭素原子数8以上30以下の直鎖状
脂肪族炭化水素(化13),(化14),(化15)を有す
るアルコキシシラン,チタネート又はアルコキシアルミ
ニウムの少なくとも1種を前記熱硬化性樹脂に化学結合
した直鎖脂肪族炭化水素化合物とともに添加することに
より硬化物のガラス状態の剪断接着強度をほとんど低下
させず、ゴム状態の剪断接着強度を大きく低下させる大
きな効果が得られる。これは、シリコンチップ表面を被
覆した直鎖状脂肪族炭化水素を有するアルコキシシラ
ン,チタネート又はアルコキシアルミニウム等と熱硬化
性樹脂に化学結合した直鎖状脂肪族炭化水素が相互作用
するためだと考えられる。
In addition, at least one of alkoxysilane, titanate and alkoxyaluminum having a linear aliphatic hydrocarbon having 8 to 30 carbon atoms (Chemical Formula 13), (Chemical Formula 14), or (Chemical Formula 15) is converted to the above-mentioned heat. By adding the cured product together with the linear aliphatic hydrocarbon compound chemically bonded to the curable resin, a significant effect of substantially reducing the shear bond strength in the glass state of the cured product and greatly reducing the shear bond strength in the rubber state can be obtained. This is thought to be due to the interaction between the alkoxysilane, titanate, or alkoxyaluminum having a linear aliphatic hydrocarbon coated on the silicon chip surface and the linear aliphatic hydrocarbon chemically bonded to the thermosetting resin. Can be

【0020】しかし、直鎖状脂肪族炭化水素を有するア
ルコキシシラン,チタネート又はアルコキシアルミニウ
ム等単独では硬化物のガラス状態の剪断接着強度をほと
んど低下させず、ゴム状態の剪断接着強度を大きく低下
させる効果は見られない。あくまでも、熱硬化性樹脂に
化学結合した直鎖脂肪族炭化水素化合物の働きを助ける
働きをしているようだ。
However, an alkoxysilane, a titanate, an alkoxyaluminum or the like having a linear aliphatic hydrocarbon alone hardly reduces the shear strength in the glassy state of the cured product, and greatly reduces the shear strength in the rubbery state. Is not seen. It seems to help the function of the linear aliphatic hydrocarbon compound chemically bonded to the thermosetting resin.

【0021】熱硬化性樹脂組成物としては、エポキシ樹
脂,アクリル樹脂,ポリイミド樹脂,マレイミド樹脂,
フェノール樹脂などが利用出来る。これらの樹脂は単独
で用いられる他、2種以上混合して用いることが出来
る。また、無機充填材を混合して低熱膨張化を図ること
でシリコンチップと回路基板の熱応力を緩和し、温度サ
イクル信頼性を向上することが出来る。さらに、ゴム成
分を添加して低弾性率化を図ることでもシリコンチップ
と回路基板の熱応力を緩和し、温度サイクル信頼性を向
上することが出来る。
As the thermosetting resin composition, epoxy resin, acrylic resin, polyimide resin, maleimide resin,
Phenol resin can be used. These resins can be used alone or in combination of two or more. In addition, by reducing the thermal expansion by mixing the inorganic filler, the thermal stress of the silicon chip and the circuit board can be reduced, and the reliability of the temperature cycle can be improved. Furthermore, by adding a rubber component to lower the elastic modulus, the thermal stress of the silicon chip and the circuit board can be reduced, and the reliability of the temperature cycle can be improved.

【0022】本発明における半導体装置をリペアする方
法として、例えば図3(a)ないし(d)に示すようにシ
リコンチップを取り外す方法には、シリコンチップを2
50℃に加熱してシリコンチップの中心を軸として回転
の剪断力をかけて取り外す方法,シリコンチップを加熱
してシリコンチップの側面から基板と水平方向に剪断力
をかけて取り外す方法などがある。シリコンチップを取
り外した後、基板側に残った樹脂を研磨し平坦化し、そ
の上に新しいシリコンチップを搭載する。
As a method for repairing a semiconductor device according to the present invention, for example, as shown in FIGS.
There are a method of heating to 50 ° C. to remove by applying a shearing force of rotation about the center of the silicon chip, and a method of heating the silicon chip to remove from the side of the silicon chip by applying a shearing force in a horizontal direction to the substrate. After removing the silicon chip, the resin remaining on the substrate side is polished and flattened, and a new silicon chip is mounted thereon.

【0023】この様に本発明の半導体装置は通常の使用
では高い温度サイクル信頼性を維持する事が出来、25
0℃に加熱することで容易にチップの取り外しを行うこ
とが出来る。
As described above, the semiconductor device of the present invention can maintain high temperature cycle reliability in normal use, and
The chip can be easily removed by heating to 0 ° C.

【0024】[0024]

【発明の実施の形態】実施例1 シリコンチップには外形10×10mmのシリコンチップ
の電極に直径80μmの半田バンプ電極を中心間隔16
0μmで形成したものを用いた。また回路基板にはガラ
スエポキシ基板FR4の2層のものを用いた。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 A solder bump electrode having a diameter of 80 μm is provided on a silicon chip electrode having an outer diameter of 10 × 10 mm.
One formed at 0 μm was used. The circuit board used was a two-layer glass epoxy board FR4.

【0025】図1(a),(b)のようにシリコンチップ
1の半田バンプ電極2を回路基板のランドに位置合わせ
しIRリフローにより半田接続した後、電子部品と回路
基板の間隙に以下の方法で調製した熱硬化性樹脂組成物
4を充填,硬化して半導体装置を作成した。なお、硬化
条件は150℃1時間とした。
As shown in FIGS. 1A and 1B, the solder bump electrodes 2 of the silicon chip 1 are aligned with the lands of the circuit board and connected by soldering by IR reflow. The thermosetting resin composition 4 prepared by the method was filled and cured to prepare a semiconductor device. The curing condition was 150 ° C. for 1 hour.

【0026】熱硬化性樹脂組成物はビスフェノールFジ
グリシジルエーテルに炭素原子数12の直鎖脂肪族炭化
水素化合物を有する無水トドデセニルコハク酸を等量比
1:0.95 で混合し、平均粒径4μmの球形シリカを
60重量%、2E4MZ−CNエポキシ樹脂に対し1重
量部添加し調製した。
The thermosetting resin composition is prepared by mixing bisphenol F diglycidyl ether with tododecenyl succinic anhydride having a linear aliphatic hydrocarbon compound having 12 carbon atoms in an equivalent ratio of 1: 0.95, Spherical silica having an average particle diameter of 4 μm was added by 60% by weight to 2E4MZ-CN epoxy resin, and 1 part by weight was added.

【0027】実施例2 実施例1において外形20×20mmのシリコンチップを
用いたもの。
Example 2 Example 2 in which a silicon chip having an outer diameter of 20 × 20 mm was used in Example 1.

【0028】実施例3 シリコンチップ1には外形10×10mmのシリコンチッ
プの電極に直径80μmの半田バンプ電極2を中心間隔
160μmで形成したものを用いた。また回路基板には
ガラスエポキシ基板3のFR4の2層のものを用いた。
Example 3 A silicon chip 1 was used in which solder bump electrodes 2 having a diameter of 80 μm were formed at a center interval of 160 μm on electrodes of a silicon chip having an outer diameter of 10 × 10 mm. The circuit board used was a two-layer glass epoxy board FR4.

【0029】図1(a),(b)のようにシリコンチップ
1の半田バンプ電極2を回路基板のランドに位置合わせ
しIRリフローにより半田接続した後、電子部品と回路
基板の間隙に以下の方法で調製した熱硬化性樹脂組成物
を充填,硬化して半導体装置を作成した。なお、硬化条
件は150℃1時間とした。
As shown in FIGS. 1A and 1B, the solder bump electrodes 2 of the silicon chip 1 are aligned with the lands of the circuit board and connected by soldering by IR reflow. The thermosetting resin composition prepared by the method was filled and cured to prepare a semiconductor device. The curing condition was 150 ° C. for 1 hour.

【0030】熱硬化性樹脂組成物4はビスフェノールF
ジグリシジルエーテルに炭素原子数12の直鎖脂肪族炭
化水素化合物を有する無水トドデセニルコハク酸を等量
比1:0.95 で混合し、平均粒径4μmの球形シリカ
を60重量%、2E4MZ−CNエポキシ樹脂に対し1
重量部、味の素株式会社製の炭素原子数17の直鎖脂肪
族炭化水素を有するチタネートのプレンアクトKR T
TSを球形シリカに対し1重量部添加し調製した。
The thermosetting resin composition 4 is bisphenol F
Tododecenyl succinic anhydride having a linear aliphatic hydrocarbon compound having 12 carbon atoms is mixed with diglycidyl ether at an equivalent ratio of 1: 0.95, and 60% by weight of spherical silica having an average particle size of 4 μm, 1 for 2E4MZ-CN epoxy resin
Part by weight, titanate pre-act KR T having straight-chain aliphatic hydrocarbon having 17 carbon atoms manufactured by Ajinomoto Co., Inc.
TS was prepared by adding 1 part by weight to spherical silica.

【0031】実施例4 実施例2において外形20×20mmのシリコンチップを
用いたもの。
Embodiment 4 Embodiment 2 in which a silicon chip having an outer shape of 20 × 20 mm is used.

【0032】実施例5 シリコンチップには外形10×10mmのシリコンチップ
の電極に直径80μmの半田バンプ電極を中心間隔16
0μmで形成したものを用いた。また回路基板にはガラ
スエポキシ基板FR4の2層のものを用いた。
Example 5 A silicon chip electrode having an outer diameter of 10 × 10 mm was provided with a solder bump electrode having a diameter of 80 μm at a center interval of 16 mm.
One formed at 0 μm was used. The circuit board used was a two-layer glass epoxy board FR4.

【0033】図1(a),(b)のようにシリコンチップ
1の半田バンプ電極2を回路基板のランドに位置合わせ
しIRリフローにより半田接続した後、電子部品と回路
基板の間隙に以下の方法で調製した熱硬化性樹脂組成物
4を充填,硬化して半導体装置を作成した。なお、硬化
条件は150℃1時間とした。
As shown in FIGS. 1 (a) and 1 (b), the solder bump electrodes 2 of the silicon chip 1 are aligned with the lands of the circuit board and connected by soldering by IR reflow. The thermosetting resin composition 4 prepared by the method was filled and cured to prepare a semiconductor device. The curing condition was 150 ° C. for 1 hour.

【0034】熱硬化性樹脂組成物の調製は以下の方法で
行った。即ち、熱硬化性樹脂組成物はP−アミノフェノ
ールトリグリシジルエーテル及び炭素原子数10の直鎖
脂肪族炭化水素化合物を有するデシルグリシジルエーテ
ルを重量比1:2で混合し、この系に等量比で1:0.
95になるよう無水メチルナジック酸を添加し、更にイ
ミダゾール系硬化促進剤2E4MZ−CNをエポキシ樹
脂に対し1重量部添加した。さらに、平均粒径4μmの
球形シリカを60重量%、味の素株式会社製の炭素原子
数16の直鎖脂肪族アルコキシ基を有するチタネートの
プレンアクトKR 338Xを球形シリカに対し1重量
部添加し調製した。
The preparation of the thermosetting resin composition was carried out by the following method. That is, the thermosetting resin composition is obtained by mixing P-aminophenol triglycidyl ether and decyl glycidyl ether having a linear aliphatic hydrocarbon compound having 10 carbon atoms at a weight ratio of 1: 2, 1: 0.
Methylnadic anhydride was added so that the ratio became 95, and 1 part by weight of an imidazole-based curing accelerator 2E4MZ-CN was added to the epoxy resin. Further, 60 parts by weight of spherical silica having an average particle diameter of 4 μm and 1 part by weight of titanate Prenact KR 338X having a straight-chain aliphatic alkoxy group having 16 carbon atoms manufactured by Ajinomoto Co., Inc. were added to the spherical silica.

【0035】実施例6 実施例5において外形20×20mmのシリコンチップを
用いたもの。
Embodiment 6 Embodiment 6 in which a silicon chip having an outer shape of 20 × 20 mm is used in Embodiment 5.

【0036】実施例7 シリコンチップには外形10×10mmのシリコンチップ
の電極に直径80μmの半田バンプ電極を中心間隔16
0μmで形成したものを用いた。また回路基板にはガラ
スエポキシ基板FR4の2層のものを用いた。
Embodiment 7 On a silicon chip, a solder bump electrode having a diameter of 80 μm is provided at a center interval of 16 μm on a silicon chip electrode having an outer shape of 10 × 10 mm.
One formed at 0 μm was used. The circuit board used was a two-layer glass epoxy board FR4.

【0037】図1(a),(b)のようにシリコンチップ
の半田バンプ電極を回路基板のランドに位置合わせしI
Rリフローにより半田接続した後、電子部品と回路基板
の間隙に以下の方法で調製した熱硬化性樹脂組成物を充
填,硬化して半導体装置を作成した。なお、硬化条件は
80℃1時間,180℃1時間とした。
As shown in FIGS. 1 (a) and 1 (b), the solder bump electrodes of the silicon chip are aligned with the lands of the circuit board.
After solder connection by R reflow, the gap between the electronic component and the circuit board was filled with a thermosetting resin composition prepared by the following method and cured to prepare a semiconductor device. The curing conditions were 80 ° C. for 1 hour and 180 ° C. for 1 hour.

【0038】熱硬化性樹脂組成物の調製は以下の方法で
行った。熱硬化性樹脂組成物は3,4−エポキシシクロ
ヒキシルメチル−3,4−エポキシシクロヘキサンカル
ボキシレートに炭素原子数22の直鎖脂肪族炭化水素化
合物を有するベヘニルメタクリレートを重量比1:1で
混合した系に、スルホニュムス塩系のカチオン重合開始
剤SI−100L(三新化学研究所製)をエポキシ樹脂
に対し2重量部、平均粒径4μmの球形シリカを60重
量%、味の素株式会社製の炭素原子数26の直鎖脂肪族
アルコキシ基を有するチタネートのプレンアクトKR
46Bを球形シリカに対し1重量部添加し調製した。
The preparation of the thermosetting resin composition was carried out by the following method. The thermosetting resin composition is a mixture of 3,4-epoxycyclohexylmethyl-3,4-epoxycyclohexanecarboxylate and behenyl methacrylate having a linear aliphatic hydrocarbon compound having 22 carbon atoms at a weight ratio of 1: 1. 2 parts by weight of a sulfonium salt-based cationic polymerization initiator SI-100L (manufactured by Sanshin Chemical Laboratory), 60% by weight of spherical silica having an average particle size of 4 μm, and carbon Prenact KR of titanate having a linear aliphatic alkoxy group having 26 atoms
46B was added and prepared by adding 1 part by weight to the spherical silica.

【0039】実施例8 実施例7において外形20×20mmのシリコンチップを
用いたもの。
Example 8 The same method as in Example 7 except that a silicon chip having an outer shape of 20 × 20 mm was used.

【0040】実施例9 シリコンチップには外形10×10mmのシリコンチップ
の電極に直径80μmの金バンプ電極を中心間隔160
μmで形成したものを用いた。また回路基板にはガラス
エポキシ基板FR4の2層のものを用いた。
Example 9 A silicon chip having an outer diameter of 10 × 10 mm was provided with a gold bump electrode having a diameter of 80 μm and a center interval of 160 μm.
What was formed in μm was used. The circuit board used was a two-layer glass epoxy board FR4.

【0041】図2(a),(b),(c)のように以下の
方法で調整した熱硬化性フィルム材5を回路基板上に仮
置きし、その後金バンプの付いたシリコンチップ1を回
路基板に荷重を掛けながら加熱し、シリコンチップと回
路基板の電気接続と熱硬化性フィルム材5の硬化を同時
に行った。なお、硬化条件は180℃3分で行った。熱
硬化性フィルム材5はビスフェノールFジグリシジルエ
ーテルに炭素原子数12の直鎖脂肪族炭化水素化合物を
有する無水トドデセニルコハク酸を等量比1:0.95
で混合し、平均粒径4μmの球形シリカを60重量%、
2E4MZ−CNエポキシ樹脂に対し1重量部、味の素
株式会社製の炭素原子数17の直鎖脂肪族炭化水素を有
するチタネートのプレンアクトKR TTSを球形シリ
カに対し1重量部添加し組成物を軟化温度が60℃以上
になるまで熱硬化反応を進行させ、その後、ラミネート
処理を行い厚さ80μmになるよう調整した。
As shown in FIGS. 2 (a), 2 (b) and 2 (c), the thermosetting film material 5 prepared by the following method is temporarily placed on a circuit board, and then the silicon chip 1 with gold bumps is removed. The circuit board was heated while applying a load, and the electrical connection between the silicon chip and the circuit board and the curing of the thermosetting film material 5 were simultaneously performed. The curing was performed at 180 ° C. for 3 minutes. The thermosetting film material 5 contains bisphenol F diglycidyl ether and tododecenyl succinic anhydride having a linear aliphatic hydrocarbon compound having 12 carbon atoms in an equivalent ratio of 1: 0.95.
60% by weight of spherical silica having an average particle size of 4 μm,
1 part by weight of 2E4MZ-CN epoxy resin and 1 part by weight of a titanate, Planeact KR TTS, a titanate having a linear aliphatic hydrocarbon having 17 carbon atoms, manufactured by Ajinomoto Co., Inc. were added to 1 part by weight of spherical silica, and the softening temperature of the composition was lowered. The thermosetting reaction was allowed to proceed until the temperature reached 60 ° C. or higher, and then lamination was performed to adjust the thickness to 80 μm.

【0042】実施例10 実施例9において外形20×20mmのシリコンチップを
用いたもの。
Embodiment 10 Embodiment 9 in which a silicon chip having an outer shape of 20 × 20 mm is used.

【0043】実施例11 シリコンチップ1には外形10×10mmのシリコンチッ
プの電極に直径80μmの金バンプ電極6を中心間隔1
60μmで形成したものを用いた。また回路基板にはガ
ラスエポキシ基板3のFR4の2層のものを用いた。
Embodiment 11 A silicon bump 1 having an outer diameter of 10 × 10 mm and a gold bump electrode 6 having a diameter of 80 μm at a center interval of 1 was mounted on the silicon chip 1.
One formed at 60 μm was used. The circuit board used was a two-layer glass epoxy board FR4.

【0044】図2(a)〜(c)のように以下の方法で
調整した熱硬化性フィルム材を回路基板上に仮置きし、
その後金バンプの付いたシリコンチップを回路基板に荷
重を掛けながら加熱しシリコンチップと回路基板の電気
接続と熱硬化性フィルム材の硬化を同時に行った。な
お、硬化条件は180℃3分で行った。
As shown in FIGS. 2A to 2C, the thermosetting film material prepared by the following method is temporarily placed on a circuit board.
Thereafter, the silicon chip provided with the gold bumps was heated while applying a load to the circuit board to simultaneously perform the electrical connection between the silicon chip and the circuit board and the curing of the thermosetting film material. The curing was performed at 180 ° C. for 3 minutes.

【0045】熱硬化性フィルム材はP−アミノフェノー
ルトリグリシジルエーテル及び炭素原子数10の直鎖脂
肪族炭化水素化合物を有するデシルグリシジルエーテル
を重量比1:2で混合し、この系に等量比で1:0.9
5 になるよう無水メチルナジック酸を添加し、更にイ
ミダゾール系硬化促進剤2E4MZ−CNをエポキシ樹
脂に対し1重量部添加した。さらに、平均粒径4μmの
球形シリカを60重量%、味の素株式会社製の炭素原子
数16の直鎖脂肪族アルコキシ基を有するチタネートの
プレンアクトKR 338Xを球形シリカに対し1重量
部添加し組成物を軟化温度が60℃以上になるまで熱硬
化反応を進行させ、その後、ラミネート処理を行い厚さ
80μmになるよう調整した。
The thermosetting film material is prepared by mixing P-aminophenol triglycidyl ether and decyl glycidyl ether having a linear aliphatic hydrocarbon compound having 10 carbon atoms at a weight ratio of 1: 2, and adding the same in this system. 1: 0.9
5 was added, and 1 part by weight of an imidazole-based curing accelerator 2E4MZ-CN was added to the epoxy resin. Furthermore, 60 parts by weight of spherical silica having an average particle diameter of 4 μm and 1 part by weight of a titanate, Prenact KR 338X having a straight-chain aliphatic alkoxy group having 16 carbon atoms, manufactured by Ajinomoto Co., 1 part by weight, were added to the spherical silica. The thermosetting reaction was allowed to proceed until the softening temperature became 60 ° C. or higher, and then lamination was performed to adjust the thickness to 80 μm.

【0046】実施例12 実施例11において外形20×20mmのシリコンチップ
を用いたもの。
Embodiment 12 Embodiment 12 is the same as Embodiment 11 except that a silicon chip having an outer shape of 20 × 20 mm is used.

【0047】実施例13 シリコンチップには外形10×10mmのシリコンチップ
の電極に直径80μmの金バンプ電極を中心間隔160
μmで形成したものを用いた。また回路基板にはガラス
エポキシ基板FR4の2層のものを用いた。
Example 13 A silicon bump electrode having an outer diameter of 10 × 10 mm and a gold bump electrode having a diameter of 80 μm at a center interval of 160 mm was formed on the silicon chip.
What was formed in μm was used. The circuit board used was a two-layer glass epoxy board FR4.

【0048】図2(a)〜(c)のように以下の方法で
調整した熱硬化性フィルム材を回路基板上に仮置きし、
その後金バンプの付いたシリコンチップを回路基板に荷
重を掛けながら加熱しシリコンチップと回路基板の電気
接続と熱硬化性フィルム材の硬化を同時に行った。な
お、硬化条件は180℃3分で行った。
As shown in FIGS. 2A to 2C, the thermosetting film material prepared by the following method is temporarily placed on a circuit board.
Thereafter, the silicon chip provided with the gold bumps was heated while applying a load to the circuit board to simultaneously perform the electrical connection between the silicon chip and the circuit board and the curing of the thermosetting film material. The curing was performed at 180 ° C. for 3 minutes.

【0049】熱硬化性フィルム材は3,4−エポキシシ
クロヒキシルメチル−3,4−エポキシシクロヘキサン
カルボキシレートに炭素原子数22の直鎖脂肪族炭化水
素化合物を有するベヘニルメタクリレートを重量比1:
1で混合した系に、スルホニウムス塩系のカチオン重合
開始剤SI−100L(三新化学研究所製)をエポキシ
樹脂に対し2重量部、平均粒径4μmの球形シリカを6
0重量%、味の素株式会社製の炭素原子数26の直鎖脂
肪族アルコキシ基を有するチタネートのプレンアクトK
R 46Bを球形シリカに対し1重量部添加し組成物を
軟化温度が60℃以上になるまで熱硬化反応を進行さ
せ、その後、ラミネート処理を行い厚さ80μmになる
よう調整した。
The thermosetting film material is 3,4-epoxycyclohexylmethyl-3,4-epoxycyclohexanecarboxylate and behenyl methacrylate having a linear aliphatic hydrocarbon compound having 22 carbon atoms in a weight ratio of 1:
2 parts by weight of a sulfonium salt-based cationic polymerization initiator SI-100L (manufactured by Sanshin Chemical Research Laboratories) based on the epoxy resin and 6 parts of spherical silica having an average particle size of 4 μm were added to the system mixed in 1.
0 wt%, Ajinomoto Co., Inc., titanate having a straight-chain aliphatic alkoxy group having 26 carbon atoms, Planeact K
One part by weight of R46B was added to the spherical silica, and the composition was allowed to undergo a thermosetting reaction until the softening temperature became 60 ° C. or higher, and then a lamination treatment was performed to adjust the composition to a thickness of 80 μm.

【0050】実施例14 実施例11において外形20×20mmのシリコンチップ
を用いたもの。
Embodiment 14 Embodiment 14 in which a silicon chip having an outer shape of 20 × 20 mm is used in the eleventh embodiment.

【0051】実施例15 実施例1〜14,比較例1〜6で作成した半導体装置の
剪断接着強度は以下の方法で測定した。
Example 15 The shear adhesive strength of the semiconductor devices prepared in Examples 1 to 14 and Comparative Examples 1 to 6 was measured by the following method.

【0052】25℃の剪断接着強度の測定は次の用にし
て行った。
The measurement of the shear adhesive strength at 25 ° C. was performed as follows.

【0053】シリコンチップの上面を構造用接着剤でス
テンレス製の支持金属に接着させた。回路基板側も同様
支持金属に接着させた。支持金属を引っ張り試験機に取
り付け剪断力をかけた。十分強力な構造用接着剤(住友
スリーエム(株)スコッチ・ウエルドsw−2214
等)を用いるとシリコンチップと回路基板の間隙で剪断
破壊した。この時の荷重をシリコンチップと回路基板の
接着面積で割って25℃の剪断接着強度とした。
The upper surface of the silicon chip was bonded to a stainless steel supporting metal with a structural adhesive. The circuit board side was similarly adhered to the supporting metal. The supporting metal was attached to a tensile tester and subjected to a shearing force. Sufficiently strong structural adhesive (Scotch Weld SW-2214, Sumitomo 3M Limited)
) Caused shear fracture in the gap between the silicon chip and the circuit board. The load at this time was divided by the bonding area between the silicon chip and the circuit board to obtain a shear bonding strength of 25 ° C.

【0054】250℃の剪断接着強度の測定は次のよう
にして行った。
The measurement of the shear adhesive strength at 250 ° C. was performed as follows.

【0055】DAGE製万能ボンドテスター、シリーズ
2400PCを用い、回路基板側からホットステージで
250℃に加熱しダイシェアー用のロードセル及びツー
ルを用い、シリコンチップの1辺から剪断力をかけた。
十分な剪断力をかけるとシリコンチップと回路基板の間
隙で剪断破壊した。この時の荷重をシリコンチップと回
路基板の接着面積で割って250℃の剪断接着強度とし
た。
Using a DAGE universal bond tester, Series 2400PC, the circuit board was heated to 250 ° C. on a hot stage and a shear force was applied from one side of the silicon chip using a die shear load cell and tool.
When a sufficient shearing force was applied, shear fracture occurred in the gap between the silicon chip and the circuit board. The load at this time was divided by the adhesive area between the silicon chip and the circuit board to obtain a shear adhesive strength of 250 ° C.

【0056】また、この試験後のシリコンチップの外観
を観察し、チップ破壊の有無を調べた。
Further, the appearance of the silicon chip after this test was observed, and the presence or absence of chip breakage was examined.

【0057】実施例16 実施例1〜14,比較例1〜6で作成した半導体装置の
温度サイクル信頼性は以下の条件で測定した。
Example 16 The temperature cycle reliability of the semiconductor devices prepared in Examples 1 to 14 and Comparative Examples 1 to 6 was measured under the following conditions.

【0058】0℃の恒温層に30分,100℃の恒温層
に30分の温度サイクル条件で行った。不良の判定は、
断線またはショートが生じた時とした。
The test was carried out under a temperature cycle condition of a constant temperature layer at 0 ° C. for 30 minutes and a constant temperature layer at 100 ° C. for 30 minutes. Judgment of failure is
It was when disconnection or short circuit occurred.

【0059】比較例1 シリコンチップには外形10×10mmのシリコンチップ
の電極に直径80μmの半田バンプ電極を中心間隔16
0μmで形成したものを用いた。また回路基板にはガラ
スエポキシ基板FR4の2層のものを用いた。
COMPARATIVE EXAMPLE 1 A solder bump electrode having a diameter of 80 μm was placed on a silicon chip electrode having an outer diameter of 10 × 10 mm.
One formed at 0 μm was used. The circuit board used was a two-layer glass epoxy board FR4.

【0060】図1(a),(b)のようにシリコンチップ
の半田バンプ電極を回路基板のランドに位置合わせしI
Rリフローにより半田接続した後、電子部品と回路基板
の間隙に以下の方法で調製した熱硬化性樹脂組成物を充
填,硬化して半導体装置を作成した。なお、硬化条件は
150℃1時間で行った。
As shown in FIGS. 1A and 1B, the solder bump electrodes of the silicon chip are aligned with the lands of the circuit board, and
After solder connection by R reflow, the gap between the electronic component and the circuit board was filled with a thermosetting resin composition prepared by the following method and cured to prepare a semiconductor device. The curing was performed at 150 ° C. for 1 hour.

【0061】熱硬化性樹脂組成物はビスフェノールFジ
グリシジルエーテルに無水メチルナジック酸を等量比
1:0.95 で混合し、平均粒径4μmの球形シリカを
60重量%、2E4MZ−CNエポキシ樹脂に対し1重
量部添加し調製した。
The thermosetting resin composition was prepared by mixing bisphenol F diglycidyl ether with methylnadic anhydride in an equivalent ratio of 1: 0.95, and adding 60% by weight of spherical silica having an average particle size of 4 μm to a 2E4MZ-CN epoxy resin. To 1 part by weight of the mixture.

【0062】比較例2 比較例1において外形20×20mmのシリコンチップを
用いたもの。
Comparative Example 2 Comparative Example 1 in which a silicon chip having an outer shape of 20 × 20 mm was used.

【0063】比較例3 シリコンチップには外形10×10mmのシリコンチップ
の電極に直径80μmの半田バンプ電極を中心間隔16
0μmで形成したものを用いた。また回路基板にはガラ
スエポキシ基板FR4の2層のものを用いた。
COMPARATIVE EXAMPLE 3 A solder bump electrode having a diameter of 80 μm was formed on a silicon chip electrode having an outer diameter of 10 × 10 mm.
One formed at 0 μm was used. The circuit board used was a two-layer glass epoxy board FR4.

【0064】図1(a),(b)のようにシリコンチップ
の半田バンプ電極を回路基板のランドに位置合わせしI
Rリフローにより半田接続した後、電子部品と回路基板
の間隙に以下の方法で調製した熱硬化性樹脂組成物を充
填,硬化して半導体装置を作成した。なお、硬化条件は
150℃1時間で行った。
As shown in FIGS. 1 (a) and 1 (b), the solder bump electrodes of the silicon chip are aligned with the lands of the circuit board.
After solder connection by R reflow, the gap between the electronic component and the circuit board was filled with a thermosetting resin composition prepared by the following method and cured to prepare a semiconductor device. The curing was performed at 150 ° C. for 1 hour.

【0065】熱硬化性樹脂組成物はビスフェノールFジ
グリシジルエーテルに無水メチルナジック酸を等量比
1:0.95 で混合し、平均粒径4μmの球形シリカを
60重量%、2E4MZ−CNエポキシ樹脂に対し1重
量部、味の素株式会社製の炭素原子数17の直鎖脂肪族
炭化水素を有するチタネートのプレンアクトKR TTSを球
形シリカに対し1重量部添加し調製した。
The thermosetting resin composition was prepared by mixing bisphenol F diglycidyl ether with methyl nadic anhydride in an equivalent ratio of 1: 0.95, and adding 60% by weight of spherical silica having an average particle size of 4 μm to a 2E4MZ-CN epoxy resin. And 1 part by weight of Titanate Preneact KR TTS having a linear aliphatic hydrocarbon having 17 carbon atoms manufactured by Ajinomoto Co., Inc. was added to the spherical silica.

【0066】比較例4 比較例1において外形20×20mmのシリコンチップを
用いたもの。
Comparative Example 4 Comparative Example 1 using a silicon chip having an outer shape of 20 × 20 mm.

【0067】比較例5 シリコンチップには外形10×10mmのシリコンチップ
の電極に直径80μmの金バンプ電極を中心間隔160
μmで形成したものを用いた。また回路基板にはガラス
エポキシ基板FR4の2層のものを用いた。
COMPARATIVE EXAMPLE 5 A silicon chip having an outer diameter of 10 × 10 mm was provided with gold bump electrodes having a diameter of 80 μm at a center interval of 160 mm.
What was formed in μm was used. The circuit board used was a two-layer glass epoxy board FR4.

【0068】図2(a)〜(c)のように以下の方法で
調整した熱硬化性フィルム材を回路基板上に仮置きし、
その後金バンプの付いたシリコンチップを回路基板に荷
重を掛けながら加熱しシリコンチップと回路基板の電気
接続と熱硬化性フィルム材の硬化を同時に行った。な
お、硬化条件は180℃3分で行った。
As shown in FIGS. 2A to 2C, the thermosetting film material prepared by the following method is temporarily placed on a circuit board.
Thereafter, the silicon chip provided with the gold bumps was heated while applying a load to the circuit board to simultaneously perform the electrical connection between the silicon chip and the circuit board and the curing of the thermosetting film material. The curing was performed at 180 ° C. for 3 minutes.

【0069】熱硬化性フィルム材はビスフェノールFジ
グリシジルエーテルに炭素原子数12の直鎖脂肪族炭化
水素化合物を有する無水メチルナジック酸を等量比1:
0.95 で混合し、平均粒径4μmの球形シリカを60
重量%、2E4MZ−CNエポキシ樹脂に対し1重量部
添加し組成物を軟化温度が60℃以上になるまで熱硬化
反応を進行させ、その後、ラミネート処理を行い厚さ8
0μmになるよう調整した。
The thermosetting film material is bisphenol F diglycidyl ether and methylnadic anhydride having a linear aliphatic hydrocarbon compound having 12 carbon atoms in an equivalent ratio of 1:
0.95 and mixed with spherical silica having an average particle size of 4 μm.
1% by weight based on the weight of the 2E4MZ-CN epoxy resin, and the composition was allowed to undergo a thermosetting reaction until the softening temperature reached 60 ° C. or higher.
It was adjusted to be 0 μm.

【0070】比較例6 比較例5において外形20×20mmのシリコンチップを
用いたもの。
Comparative Example 6 Comparative Example 5 using a silicon chip having an outer shape of 20 × 20 mm.

【0071】[0071]

【発明の効果】【The invention's effect】

【0072】[0072]

【表1】 [Table 1]

【0073】[0073]

【表2】 [Table 2]

【0074】表1に実施例及び比較例で記した半導体装
置の構成の特徴を示す。表2には実施例及び比較例で記
した半導体装置のチップ取り外しに要する剪断接着強度
(25℃,250℃)及びチップ取り外し時のチップ破
壊の有無及び、温度サイクル信頼性の結果を示す。
Table 1 shows the features of the structures of the semiconductor devices described in the examples and comparative examples. Table 2 shows the shear bond strength (25 ° C., 250 ° C.) required for chip removal of the semiconductor device described in the examples and comparative examples, the presence / absence of chip destruction upon chip removal, and the results of temperature cycle reliability.

【0075】直鎖脂肪族炭化水素を持たない比較例1〜
6は25℃の接着強度は5Mpa以上で信頼性も良い
が、250℃でも比較的高い1Mpaより大きい接着力
を維持している。このため、250℃でのチップ取り外
しにおいて比較例1,3,5のように10×10mmのシ
リコンチップを用いた半導体装置ではチップ破壊は比較
的生じにくいが、20×20mmのシリコンチップでは、
チップ取り外しの際、大きな応力が必要となるため、チ
ップ破壊を起こしてしまった。
Comparative Examples 1 to 3 having no linear aliphatic hydrocarbon
In No. 6, the adhesive strength at 25 ° C. is 5 Mpa or more and the reliability is good, but the adhesive strength at 250 ° C. is still higher than 1 Mpa, which is relatively high. For this reason, chip destruction is relatively unlikely to occur in a semiconductor device using a 10 × 10 mm silicon chip as in Comparative Examples 1, 3, and 5 at chip removal at 250 ° C., but in a 20 × 20 mm silicon chip,
When removing the chip, a large stress is required, causing chip destruction.

【0076】これに対し、直鎖脂肪族炭化水素化合物を
炭素原子数10以上30以下有する実施例1〜14は2
5℃の接着強度は5Mpa以上で比較的高く、温度サイ
クル信頼性は良い。しかも、250℃で接着力が大きく
低下し1Mpa以下に達している。これは、高温に加熱
することで直鎖脂肪族炭化水素が激しく熱運動するため
接着力が著しく低下したものと考えられる。これによ
り、20×20mmのシリコンチップでもチップ破壊を起
こさず良好にチップの取り外しができた。
On the other hand, Examples 1 to 14 having a linear aliphatic hydrocarbon compound having 10 to 30 carbon atoms have 2
The adhesive strength at 5 ° C. is relatively high at 5 Mpa or more, and the temperature cycle reliability is good. In addition, the adhesive force was significantly reduced at 250 ° C. and reached 1 Mpa or less. This is considered to be due to the fact that heating to a high temperature caused the linear aliphatic hydrocarbon to perform a vigorous thermal motion, so that the adhesive force was significantly reduced. As a result, even a silicon chip of 20 × 20 mm was successfully removed without causing chip destruction.

【0077】本発明の半導体装置は、シリコンチップの
能動面を回路基板側に向け導電性材料を介して回路基板
に電気的に接続しシリコンチップと回路基板の間隙を熱
硬化性樹脂組成物で充填硬化した半導体装置において分
子と化学結合した炭素原子数10以上30以下の直鎖状
脂肪族炭化水素化合物を有するという特徴を持たせるこ
とで、シリコンチップと回路基板の剪断接着強度が25
℃で5Mpa以上、250℃で1Mpa以下の値を満足
させ、高い信頼性と良好なチップ取り外し性の両立を可
能としている。
In the semiconductor device of the present invention, the active surface of the silicon chip is directed toward the circuit board and electrically connected to the circuit board via a conductive material, and the gap between the silicon chip and the circuit board is filled with a thermosetting resin composition. By providing a feature in a filled and cured semiconductor device that it has a linear aliphatic hydrocarbon compound having 10 to 30 carbon atoms chemically bonded to molecules, the shear adhesive strength between the silicon chip and the circuit board is reduced to 25.
It satisfies the value of 5 Mpa or more at 0 ° C. and 1 Mpa or less at 250 ° C., and enables both high reliability and good chip detachability.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例1である半導体装置のプロセス
フローを示す断面図。
FIG. 1 is a sectional view showing a process flow of a semiconductor device which is Embodiment 1 of the present invention.

【図2】本発明の実施例2である半導体装置のプロセス
フローを示す断面図。
FIG. 2 is a sectional view showing a process flow of a semiconductor device which is Embodiment 2 of the present invention.

【図3】本発明の実施例3である半導体装置のリペア法
を示す断面図。
FIG. 3 is a sectional view showing a repair method of a semiconductor device according to a third embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1…シリコンチップ、2…半田バンプ電極、3…ガラス
エポキシ基板、4…直鎖脂肪族炭化水素化合物を有する
熱硬化性樹脂組成物、5…直鎖脂肪族炭化水素化合物を
有するフィルム材、6…金バンプ電極、7…駆動部、8
…ヒーター、9…ヘッド、10…押さえ治具、11…
台、12…研磨用治具、13…粉塵吸引口、14…新し
いシリコンチップ、15…新しい半田バンプ電極。
DESCRIPTION OF SYMBOLS 1 ... Silicon chip, 2 ... Solder bump electrode, 3 ... Glass epoxy board, 4 ... Thermosetting resin composition containing linear aliphatic hydrocarbon compound, 5 ... Film material containing linear aliphatic hydrocarbon compound, 6 ... Gold bump electrode, 7 ... Drive section, 8
... heater, 9 ... head, 10 ... holding jig, 11 ...
Table, 12: Polishing jig, 13: Dust suction port, 14: New silicon chip, 15: New solder bump electrode.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 FI C08L 63/00 C08L 63/00 C (72)発明者 上野 巧 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 (72)発明者 江口 州志 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 6 Identification symbol FI C08L 63/00 C08L 63/00 C (72) Inventor Takumi Ueno 7-1-1, Omikamachi, Hitachi, Ibaraki Prefecture Hitachi, Ltd. (72) Inventor Shuji Eguchi 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd. Hitachi Research Laboratory

Claims (13)

【特許請求の範囲】[Claims] 【請求項1】シリコンチップの能動面を回路基板側に向
け導電性材料を介して回路基板に電気的に接続し、シリ
コンチップと回路基板の間隙を熱硬化性樹脂組成物で充
填硬化した半導体装置において、シリコンチップと回路
基板の剪断接着強度が25℃で5Mpa以上であり、2
50℃で1Mpa以下であることを特徴とする半導体装
置。
1. A semiconductor in which an active surface of a silicon chip is electrically connected to a circuit board via a conductive material with an active surface facing the circuit board, and a gap between the silicon chip and the circuit board is filled and cured with a thermosetting resin composition. In the apparatus, the shear adhesive strength between the silicon chip and the circuit board is 5 Mpa or more at 25 ° C.
A semiconductor device having a temperature of 1 Mpa or less at 50 ° C.
【請求項2】シリコンチップの能動面を回路基板側に向
け導電性材料を介して回路基板に電気的に接続し、シリ
コンチップと回路基板の間隙を熱硬化性樹脂組成物で充
填硬化した半導体装置において、上記熱硬化性樹脂組成
物が上記熱硬化性樹脂組成物中の熱硬化性樹脂成分と化
学結合する炭素原子数10以上30以下の直鎖状脂肪族
炭化水素化合物を上記熱硬化性樹脂組成物中の樹脂成分
の総重量の20重量%以上90重量%以下含有すること
を特徴とする半導体装置。
2. A semiconductor in which an active surface of a silicon chip is directed toward a circuit board and electrically connected to the circuit board via a conductive material, and a gap between the silicon chip and the circuit board is filled and cured with a thermosetting resin composition. In the apparatus, the thermosetting resin composition is used to form a linear aliphatic hydrocarbon compound having 10 to 30 carbon atoms that is chemically bonded to the thermosetting resin component in the thermosetting resin composition. A semiconductor device comprising 20% by weight or more and 90% by weight or less of the total weight of a resin component in a resin composition.
【請求項3】 【化1】 【化2】 シリコンチップの能動面を回路基板側に向け導電性材料
を介して回路基板に電気的に接続し、シリコンチップと
回路基板の間隙を熱硬化性樹脂組成物で充填硬化した半
導体装置において、上記熱硬化性樹脂組成物が(化
1),(化2)の1種または2種を上記熱硬化性樹脂組成
物中の樹脂成分の総重量の20重量%以上90重量%以
下含有することを特徴とする半導体装置。
(3) Embedded image In a semiconductor device in which an active surface of a silicon chip is electrically connected to a circuit board via a conductive material with the active surface facing the circuit board side and a gap between the silicon chip and the circuit board is filled and cured with a thermosetting resin composition, The curable resin composition contains one or two of (Chemical Formula 1) and (Chemical Formula 2) in an amount of 20% by weight or more and 90% by weight or less of the total weight of the resin component in the thermosetting resin composition. Semiconductor device.
【請求項4】シリコンチップの能動面を回路基板側に向
け導電性材料を介して回路基板に電気的に接続し、シリ
コンチップと回路基板の間隙を熱硬化性樹脂組成物で充
填硬化した半導体装置において、上記熱硬化性樹脂組成
物が、上記熱硬化性樹脂組成物中の熱硬化性樹脂成分と
化学結合する炭素原子数10以上30以下の直鎖状脂肪
族炭化水素化合物を上記熱硬化性樹脂組成物中の樹脂成
分の総重量の20重量%以上90重量%以下含有し、か
つ、炭素原子数8以上30以下の直鎖状脂肪族炭化水素
を有するアルコキシシラン,チタネート又はアルコキシ
アルミニウムの少なくとも1種を含有することを特徴と
する半導体装置。
4. A semiconductor in which an active surface of a silicon chip is directed toward a circuit board and electrically connected to the circuit board via a conductive material, and a gap between the silicon chip and the circuit board is filled and cured with a thermosetting resin composition. In the apparatus, the thermosetting resin composition is used for thermosetting a linear aliphatic hydrocarbon compound having 10 to 30 carbon atoms that is chemically bonded to a thermosetting resin component in the thermosetting resin composition. Of alkoxysilane, titanate or alkoxyaluminum containing 20 to 90% by weight of the total weight of the resin component in the conductive resin composition and having a linear aliphatic hydrocarbon having 8 to 30 carbon atoms. A semiconductor device comprising at least one kind.
【請求項5】 【化3】 【化4】 【化5】 【化6】 【化7】 【化8】 【化9】 シリコンチップの能動面を回路基板側に向け導電性材料
を介して回路基板に電気的に接続し、シリコンチップと
回路基板の間隙を熱硬化性樹脂組成物で充填硬化した半
導体装置において、上記熱硬化性樹脂組成物が(化
1),(化2)の1種または2種を上記熱硬化性樹脂組成
物中の樹脂成分の総重量の20重量%以上90重量%以
下含有し、かつ、(化3),(化4),(化5),(化
6),(化7),(化8),(化9)の少なくとも1種を
含有することを特徴とする半導体装置。
(5) Embedded image Embedded image Embedded image Embedded image Embedded image Embedded image In a semiconductor device in which an active surface of a silicon chip is electrically connected to a circuit board via a conductive material with the active surface facing the circuit board side and a gap between the silicon chip and the circuit board is filled and cured with a thermosetting resin composition, The curable resin composition contains one or two of (Chemical Formula 1) and (Chemical Formula 2) in an amount of 20% by weight or more and 90% by weight or less based on the total weight of the resin components in the thermosetting resin composition; A semiconductor device comprising at least one of (Chem. 3), (Chem. 4), (Chem. 5), (Chem. 6), (Chem. 7), (Chem. 8), and (Chem. 9).
【請求項6】シリコンチップの能動面と回路基板の間隙
を封止するアンダーフィル材において、上記アンダーフ
ィル材が炭素原子数10以上30以下の直鎖状脂肪族炭
化水素を有するエポキシ化合物を上記アンダーフィル材
中の樹脂成分の総重量の20重量%以上90重量%以下
含有することを特徴とするアンダーフィル材。
6. An underfill material for sealing a gap between an active surface of a silicon chip and a circuit board, wherein the underfill material comprises an epoxy compound having a linear aliphatic hydrocarbon having 10 to 30 carbon atoms. An underfill material comprising 20% by weight or more and 90% by weight or less of the total weight of the resin component in the underfill material.
【請求項7】シリコンチップの能動面と回路基板の間隙
を封止するアンダーフィル材において、上記アンダーフ
ィル材が熱硬化性のエポキシ樹脂と酸無水物を含有し、
かつ、無機充填材を25体積%以上60体積%以下含有
し、(化1)を上記アンダーフィル材中の樹脂成分の総
重量の20重量%以上90重量%以下含有することを特
徴とするアンダーフィル材。
7. An underfill material for sealing a gap between an active surface of a silicon chip and a circuit board, wherein the underfill material contains a thermosetting epoxy resin and an acid anhydride,
An underfill containing 25% by volume or more and 60% by volume or less of an inorganic filler; and 20% by weight or more and 90% by weight or less of the total weight of the resin components in the underfill material. Fill material.
【請求項8】シリコンチップの能動面と回路基板の間隙
を封止するアンダーフィル材において、上記アンダーフ
ィル材が炭素原子数10以上30以下の直鎖状脂肪族炭
化水素を有するエポキシ化合物を上記アンダーフィル材
中の樹脂成分の総重量の20重量%以上90重量%以下
含有し、かつ、炭素原子数8以上30以下の直鎖状脂肪
族炭化水素を有するアルコキシシラン、チタネート又は
アルコキシアルミニウムの少なくとも1種を含有するこ
とを特徴とするアンダーフィル材。
8. An underfill material for sealing a gap between an active surface of a silicon chip and a circuit board, wherein the underfill material comprises an epoxy compound having a linear aliphatic hydrocarbon having 10 to 30 carbon atoms. At least 20% by weight or less and 90% by weight or less of the total weight of the resin component in the underfill material and at least one of alkoxysilane, titanate and alkoxyaluminum having a linear aliphatic hydrocarbon having 8 to 30 carbon atoms. An underfill material comprising one kind.
【請求項9】シリコンチップの能動面と回路基板の間隙
を封止するアンダーフィル材において、上記アンダーフ
ィル材が熱硬化性のエポキシ樹脂と酸無水物を有し、か
つ、無機充填材を25体積%以上60体積%以下有し、
かつ、(化1)を上記アンダーフィル材中の樹脂成分の
総重量の20重量%以上90重量%以下含有し、かつ、
(化3),(化4),(化5),(化6),(化7),(化
8),(化9)の少なくとも1種を含有することを特徴
とするアンダーフィル材。
9. An underfill material for sealing a gap between an active surface of a silicon chip and a circuit board, wherein the underfill material contains a thermosetting epoxy resin and an acid anhydride, and contains 25 inorganic fillers. Volume% or more and 60 volume% or less,
And (Chemical Formula 1) is contained in an amount of 20% by weight or more and 90% by weight or less based on the total weight of the resin component in the underfill material;
An underfill material comprising at least one of (Chem. 3), (Chem. 4), (Chem. 5), (Chem. 6), (Chem. 7), (Chem. 8), and (Chem. 9).
【請求項10】シリコンチップの能動面と回路基板を接
着する熱硬化性フィルム材において、上記熱硬化性フィ
ルム材が炭素原子数10以上30以下の直鎖状脂肪族炭
化水素化合物を有するエポキシ化合物を上記熱硬化性フ
ィルム材中の樹脂成分の総重量の20重量%以上90重
量%以下含有することを特徴とする熱硬化性フィルム
材。
10. A thermosetting film material for bonding an active surface of a silicon chip to a circuit board, wherein the thermosetting film material has a linear aliphatic hydrocarbon compound having 10 to 30 carbon atoms. Is contained in an amount of 20% by weight or more and 90% by weight or less of the total weight of the resin component in the thermosetting film material.
【請求項11】シリコンチップの能動面と回路基板を接
着する熱硬化性フィルム材において、上記熱硬化性フィ
ルム材が熱硬化性のエポキシ樹脂を有し、かつ、無機充
填材を25体積%以上60体積%以下有し、かつ、(化
1)を上記熱硬化性フィルム材中の樹脂成分の総重量の
20重量%以上90重量%以下含有することを特徴とす
る熱硬化性フィルム材。
11. A thermosetting film material for bonding an active surface of a silicon chip to a circuit board, wherein the thermosetting film material has a thermosetting epoxy resin, and contains 25% by volume or more of an inorganic filler. A thermosetting film material comprising 60% by volume or less and (Chemical Formula 1) in an amount of 20% by weight or more and 90% by weight or less based on the total weight of the resin components in the thermosetting film material.
【請求項12】シリコンチップの能動面と回路基板を接
着する熱硬化性フィルム材において、上記熱硬化性フィ
ルム材が炭素原子数10以上30以下の直鎖状脂肪族炭
化水素化合物を有するエポキシ化合物を上記熱硬化性フ
ィルム材中の樹脂成分の総重量の20重量%以上90重
量%以下含有し、かつ、炭素原子数8以上30以下の直
鎖状脂肪族炭化水素を有するアルコキシシラン,チタネ
ート又はアルコキシアルミニウムの少なくとも1種を含
有することを特徴とする熱硬化性フィルム材。
12. A thermosetting film material for bonding an active surface of a silicon chip to a circuit board, wherein said thermosetting film material has a linear aliphatic hydrocarbon compound having 10 to 30 carbon atoms. Of 20 to 90% by weight based on the total weight of the resin component in the thermosetting film material, and having a linear aliphatic hydrocarbon having 8 to 30 carbon atoms. A thermosetting film material comprising at least one kind of alkoxyaluminum.
【請求項13】シリコンチップの能動面と回路基板を接
着する熱硬化性フィルム材において、上記熱硬化性フィ
ルム材が熱硬化性のエポキシ樹脂を有し、かつ、無機充
填材を25体積%以上60体積%以下有し、かつ、(化
1)を上記熱硬化性フィルム材中の樹脂成分の総重量の
20重量%以上90重量%以下含有し、かつ、(化
3),(化4),(化5),(化6),(化7),(化8),
(化9)の少なくとも1種を含有することを特徴とする
熱硬化性フィルム材。
13. A thermosetting film material for bonding an active surface of a silicon chip to a circuit board, wherein said thermosetting film material has a thermosetting epoxy resin, and contains 25% by volume or more of an inorganic filler. 60% by volume or less, and (Chemical Formula 1) in an amount of 20% by weight or more and 90% by weight or less of the total weight of the resin component in the thermosetting film material, and (Chemical Formula 3), (Chemical Formula 4) , (Chem. 5), (Chem. 6), (Chem. 7), (Chem. 8),
A thermosetting film material comprising at least one of the following (Chem. 9).
JP2951098A 1998-02-12 1998-02-12 Semiconductor device, underfill material, and thermosetting film material Pending JPH11233571A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2951098A JPH11233571A (en) 1998-02-12 1998-02-12 Semiconductor device, underfill material, and thermosetting film material

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2951098A JPH11233571A (en) 1998-02-12 1998-02-12 Semiconductor device, underfill material, and thermosetting film material

Publications (1)

Publication Number Publication Date
JPH11233571A true JPH11233571A (en) 1999-08-27

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Country Link
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