JPH11225093A - Signal receiver for ds-cdma cecllular system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable soft handover by alternatively connecting plural arithmetic registers to a corresponding matched filter by means of a register multiplexer so as to intermittently receive signals of plural base stations with a single matched filter. SOLUTION: A spread code is supplied for a matched filter by two systems of arithmetic registers CAL-REG1 and CAL-REG2. Inputting registers INP-REG1 and INP-REG2 are respectively connected to these registers. Separate spreadig codes Pa and Pb are respectively inputted to these inputting registers and these spreadig codes are transferred to the arithmetic registers from the inputting registers. A phase/multiplexer outputs the data array of CAL-REG1 and CAL- REG2 as it is or the data array in a circulation shifting state immediately before to a poststage. The outputs of PMUXs 1 and 2 are inputted to a register multiplexer RMUX to alternatively output the output of CAL-REG1 or CAL-REG 2 as MUXCNT.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of sample-and-hold circuits for holding input signals in time series, a plurality of matched filters for calculating a correlation between the input signals held in these sample-and-hold circuits and spreading codes. , An operation register provided for each matched filter, for storing the spread code and supplying the spread code to the matched filter, and a signal receiving apparatus for a DS-CDMA cellular system.

[0002] This type of CDMA cellular system is important in realizing an inter-cell asynchronous system since it is possible to identify a base station and a mobile station, and it is not necessary to manage time spanning between cells. Here the inter-cell asynchronous system is GPS
And the base station system is inexpensive without depending on the time synchronization system. Further, since the time synchronization system identifies a base station based on a signal arrival time difference, a long code for each base station is not set, and a problem based on misidentification of the base station may occur. In addition, in order to realize a practical system, the signal receiving device of the mobile station, besides despreading of a combined code of a long code and a short code, not only fading compensation for multipath and rake combining processing,
Performs identification and evaluation of multiple base stations for initial cell search and peripheral cell search, and also makes transmission rate variable by making spreading factor variable, and supports multi-code transmission to improve communication speed.

[0003]

2. Description of the Related Art Such a CDMA cellular system is not preferable as a characteristic of a mobile station because a signal receiving apparatus may become complicated and large-scale. In particular, when receiving signals from a plurality of base stations during soft handover, a traffic channel requires a plurality of matched filters, and the circuit scale is further increased.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of such a background, and an object of the present invention is to provide a small signal receiving apparatus capable of coping with soft handover.

[0005]

In the signal receiving apparatus according to the present invention, one or more matched filters are provided with a plurality of operation registers, and the plurality of operation registers are selectively handled by a register multiplexer. It is connected to a matched filter and receives signals from a plurality of base stations intermittently with one matched filter.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The following DS-CDMA according to the present invention
An embodiment of a signal receiving device of a cellular system will be described with reference to the drawings.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, one matched filter in a signal receiving apparatus has a plurality of sample and hold circuits SH1 to SHn to which an analog input signal Vin is connected.
Vin is held in these sample and hold circuits. These sample and hold circuits operate in response to the system clock, and sequentially sample and hold Vin. By adopting a configuration in which data transfer is not performed between the sample and hold circuits, a data transfer error can be eliminated.

The outputs of the sample-and-hold circuits SH1 to SHn are input to the corresponding multiplexers MUX1 to MUXn, and each multiplexer distributes the output of the sample-and-hold circuit into two systems in response to a spreading code (a 1-bit code string). The output signal of each system of the multiplexer is input to the addition circuit ADD, and the addition circuit outputs the spread code “1”,
It has "p" and "m" processing systems respectively corresponding to "0". Further, the output of the addition circuit ADD is input to a scaler (indicated by a symbol “SCALER”), and an appropriately scaled output signal Vout is generated.

The sample-and-hold circuit is connected in parallel with Vin so as to take in Vin sequentially, and the filter operation is executed by cyclically shifting the spread code in synchronization with the sampling timing.
At this time, switching of the multiplexers MUX1 to MUXn is controlled at high speed.

FIG. 6 shows a circuit configuration after the matched filter. In FIG. 6, the number of matched filters is limited to eight for easy understanding, and the two matched filters MF01 and MF02 are connected to the perch channel group Pc.
h, four matched filters MF21 to MF2
4 is assigned to the traffic channel group Tch, and two matched filters MF11 and MF12 are assigned to the shared group Cch.

The output of the four matched filters of the groups Pch and Cch is a four-input one-output multiplexer MU.
Xp1 to MUXpS, respectively, and each multiplexer selectively outputs the output of MF01, MF02, MF11, and MF12. Each multiplexer MUXp1-M
Multipath signal / sample hold circuits SHp1 to SHpS are respectively connected to the output of UXpS, and each sample hold circuit holds one peak generated in Pch and Cch one by one.

The output of the six matched filters of the groups Tch and Cch is a six-input one-output multiplexer MU.
Xt1 to MUXtR, and each multiplexer is MF21, MF22, MF23, MF24, MF
11. The output of the MF 12 is alternatively output. Multipath signal / sample hold circuits SHt1 to SHtR are connected to the outputs of the multiplexers MUXt1 to MUXtR, respectively.
The peaks generated in step are retained one by one. Pch, Tch,
The output of the Cch matched filter is further applied to the peak detection circuit P
Dp and PDt, these peak detection circuits detect and average correlation peaks in the output of the matched filter, sort the average power, select peaks to be extracted, and register the phases of the selected peaks. . PD
p and PDt are sample and hold circuits SHp1 to SHpS
And control signals for SHt1 to SHtR are output.
Decoded by Ct. This control signal generates a sampling signal to each sample and hold circuit. As a result, peak detection and selection are performed for all or a part of the matched filter.

The common group Cch can be applied to both the perch channel side and the traffic channel side.
Therefore, the traffic channel is variable in the range of 4 to 6 channels, and the perch channel is variable in the range of 2 to 4 channels. Since the common group is provided and the number of channels is made variable, the degree of freedom of the communication mode can be increased.

Each sample and hold circuit SHp1 to SHp
S, the outputs of SHt1 to SHtR have an A / D conversion circuit A
Dp1 to ADpS and ADt1 to ADtR, respectively, and are converted into digital signals by these A / D conversion circuits. Outputs of the A / D conversion circuits ADp1 to ADpS are input to a multipath signal / multiplexer MUX31.
The outputs of the A / D conversion circuits ADt1 to ADtR are input to the multipath signal / multiplexer MUX32. These multiplexers MUX31 and MUX32 selectively output data of the sample-and-hold circuit, and perform subsequent fading compensation and rake combining in a time-division manner. By this time division processing, a circuit for fading compensation and rake combining becomes small. A / D conversion circuit A
It is also possible to provide one A / D conversion circuit in place of Dp1 to ADpS and use this in a time-division manner to digitize the signals of all the sample and hold circuits SHp1 to SHpS. The same applies to the conversion circuits ADt1 to ADtR.

The MUX 31 sequentially stores the correlation output of the A / D conversion circuit of the perch channel in the memory ME.
The signals are stored in M31, and the I-phase and Q-phase signals are subjected to fading compensation by a fading compensation circuit PC31. The fading-compensated signal is applied to a rake combining circuit RC.
The rake combination output Sout1 is input to the MB 31 and is generated. The MUX 32 sequentially stores the correlation output for the phase at which the peak power of the traffic channel occurs in the memory ME.
These signals are stored in M32, and the I-phase and Q-phase signals are subjected to fading compensation by a fading compensation circuit PC32. The fading-compensated signal is applied to a rake combining circuit RC.
The rake combination output Sout2 is input to the MB 32 and is generated.

FIG. 4 is a timing chart for explaining the operation of the circuit of FIG. 6, and shows the processing of the perch channel by the MF01 and the processing of the traffic channel by the MF21. For example, in a certain symbol period, for a certain base station, three multipath signals (“Peak”) are matched with a perch channel matched filter MF01.
01 ". ) Occurs, the sample hold is performed using three of the sample hold circuits SHp1 to SHpS. It is also assumed that two multipaths have occurred for another base station. On the other hand, the matched filter MF21 of the traffic channel calculates five multipath signals (“Peak21”) as the sum of these multipaths.
Indicated by ) Occurs, the sample and hold circuit SHt
The sample-and-hold is performed using five of the signals 1 to SHtR. The sample data of the perch channel is stored in the memory MEM31 (indicated by "MEM01"), and the sample data of the traffic channel is stored in the memory 32 (indicated by "MEM21"). Thereafter, fading compensation for the stored data and rake combining are performed.

The matched filter MF01 receives the signals from the base station a and the base station b. As shown in Peak01, the received signal from the base station a is converted into a three-path multipath signal and the received signal from the base station b. A two-pass multipath has occurred. In addition, since such a delay profile basically does not cause a sudden change, a delay profile of a certain symbol period can be applied as a delay profile of the next period.
Therefore, the multipath phase of each base station in the traffic channel can be estimated in advance.

At the time of soft handover, signals of a base station that is currently receiving signals and signals of neighboring base stations are received, and signals of a plurality of base stations are simultaneously received and evaluated until the next base station is determined. There is a need. In FIG. 4, as described above, the base station a and the base station b are simultaneously received to perform soft handover. The reception of the signal is performed by the matched filter MF21 of the traffic channel, and the spread code is switched at the timing when the correlation peak of each base station occurs.

In FIG. 2, the supply of the spreading code to the matched filter is performed by two systems of operation registers CAL-REG.
1, CAL-REG2, and these registers include input registers INP-REG1, INP-REG2
Are connected respectively. Separate spread codes Pa and Pb are input to these input registers, respectively, and these spread codes are transferred from the input register to the operation register.
The last stage of CAL-REG1 and CAL-REG2 is fed back to the first stage, and CAL-REG1 and CAL-REG2
Each of the data in the phase-multiplexer PMUX1, PMUX
UX2. The phase / multiplexer outputs the data array of CAL-REG1 and CAL-REG2 as it is or the data array in the cyclic shift state immediately before (one chip time earlier) to the subsequent stage. PMUX
1. The output of PMUX2 is the register multiplexer RM
UX, CAL-REG1 or CAL-RE
The output of G2 is alternatively output as MUXCNT.

In FIG. 3, the phase / multiplexer PM
UX1 is the first stage of the register CAL-REG1 (data D1
Indicated by ) And a two-input / one-output data multiplexer DMUX1 corresponding to the second stage (indicated by data D2), and a data multiplexer DMU corresponding to the second and third stages
X2,. . . , A data multiplexer DMUXn-1 corresponding to the (n-1) th stage to the last stage, and a data multiplexer DMUXn corresponding to the last stage and the first stage,
In a normal correlation operation without peak overlap, DMUX1-DUX
MUXn outputs D1 to Dn, respectively. When the correlation calculation is performed at a timing delayed by one chip time from the peak overlap timing, DMUX1 to DMUXn
2 to Dn and D1 respectively. This is data corresponding to D1 to Dn one chip time earlier. Note that P
The MUX 2 is configured in the same manner as the PMUX 1 and will not be described. Also, if a multiple-input / one-output multiplexer is used so that the data sequence of a plurality of chip times ago can be reproduced,
It can deal with peak overlap or continuous peak overlap of a plurality of operation registers.

On the other hand, in the sample and hold circuit, as shown in FIG.
Is provided, and Vin is also connected to SHEX. S
The output of HEX is input to multiplexer MUXEX,
The output is input to the adder ADD. If the overlap of the correlation peaks occurs, for example, immediately after SH1 samples Vin, it is predicted one symbol before and the data is stored in SHEX instead of SH2.
This data acquisition is performed simultaneously with the SH2 data acquisition. New data of SH1 and operation register CAL-
When the correlation calculation using the spreading code of REG1 is completed, the calculation using the same data and the spreading code of CAL-REG2 is performed next. However, since new data is taken in for SH2, the old data of SH2 is stored in SHEX, and an operation is performed using a data string including the old data.

If the sub-sample and hold circuit is not provided, one input signal to be stored is updated with a new input signal during the correlation operation by CAL-REG2, and an error occurs in the operation result. However, in a normal DS-CDMA cellular system, since the number of taps (the number of times of multiplication of the correlation operation) is sufficiently large, this error can be ignored. That is, a configuration in which the sample and hold circuit SHEX is saved can be realized.

The signal input to the sub-sample and hold circuit is
This can be performed at the timing of the peak overlap, and the data stored in SH1 to SHn is not updated and new data is held in one or a plurality of sub-sample and hold circuits until the peak overlap is avoided. . This eliminates the need to predict the peak overlap one or more symbol periods earlier.

The above operation will be described with reference to the timing chart of FIG. 4. In the matched filter MF01 of the perch channel, the spreading codes P01, a,
P01 and b are applied alternately, and peaks of signals from both base stations are detected as indicated by Peak01. On the other hand, in the matched filter MF21 of the traffic channel, the spreading codes Pa and Pb of both base stations are switched and applied within each symbol period, and the k-th,
In the (k + 1) -th symbol period, signals from both base stations are received. Since the correlation peaks do not overlap in the k-th and (k + 1) -th symbol periods, all of the correlation peaks are sampled and held in the subsequent sample hold circuits SHt1 to SHt.
All correlation peaks (indicated by S / H) can be extracted simply by sampling by tR. After the (k + 2) th symbol period, the peak of the base station a and the peak of the base station b overlap at the position of the correlation peak indicated by PP, but the correlation calculation of the base station b is delayed as described above. As a result, the peak of the base station b is generated with a delay as shown in the figure PD, and the duplication is prevented. The sample and hold circuit samples the correlation peak thus generated. The correlation output of MF01 is stored in the memory MEM01, and the correlation output of MF21 is stored in the memory MEM21. After that, fading compensation (PHC01, PHC
21) is performed, and rake combining is further performed. If a plurality of sub-sample and hold circuits are provided, it is possible to cope with correlation peaks that are repeated a plurality of times, and to perform accurate calculations. Assuming that the number of duplications is d, {1 symbol period-1 chip time}, {1 symbol period-2 chip time},. . . , {1 symbol period− (d−1) time} in sequence, and sequentially uses them to output a correlation peak.

When the number of peak overlaps is smaller than the total number of taps, it goes without saying that the sub-sample and hold circuit can be omitted. Also, if CAL-REG1 and CAL-REG2 are used alternately for continuous overlap, the error in each correlation operation will be the input signal 1
And the error can be reduced. At this time, the number of sub-length delay registers is sufficient, so that the circuit scale can be reduced.

As a configuration of the matched filter, the configuration shown in FIG. 5 can be employed, and sample-hold circuits SHA1 to SHA
n are connected in series, and the analog input signal Vin input to the first-stage SHA1 is sequentially transferred to the subsequent stage. SHA1 to SH
The output of An is supplied to multiplexers MUX1 to MUXn similar to FIG. 1 via multiplexers SMUX1 to SMUXn.
And the outputs of these multiplexers are
DD and scaled by a scaler SCALER. Sub-sample and hold circuit SHAEX is connected to the subsequent stage of sample and hold circuit SHAAn.
The output of HAn is input to SHAEX. The multiplexers SMUX1 to SMUXn have two inputs and one output,
SHA2 to SHAEX are input in addition to SHA1 to SHAn. That is, SMUX1 is SHA
1 or the output of SHA2, and the k-th multiplexer SMUXk outputs SHAk or SHAk + 1.
Outputs the output of

In such a matched filter, CA
When the correlation peaks of L-REG1 and CAL-REG2 overlap, the correlation peaks of CAL-REG1 are calculated by connecting SHA1 to SHAn to MUX1 to MUXn, and then SHA2 to SHAEX are converted to MUX1 to MUXn.
CAL-REG2 correlation peak is calculated by the connection corresponding to. After that, the connection of SMUX1 to SMUXn is restored. It is to be noted that the SHAEX can be omitted, and a plurality of SHAEXs can be provided or can be omitted for continuous peak overlap, as in the above embodiment.

FIG. 7 shows another embodiment, in which the processing of the perch channel matched filter MF01 in FIG. 4 is performed by using the traffic channel matched filter MF2.
1 and the processing performed by the MF21 is performed by the MF22.
It is done in. In the MF21, the spreading codes Pa and Pb of the base stations a and b are alternately used for each symbol period.
The signals of both base stations are received by switching a and Pb as needed. The subsequent processing is the same as in FIG. Thus, it is also possible to perform soft handoff only with the matched filter of the traffic channel.

FIG. 8 shows still another embodiment, in which soft handoff is performed only by one matched filter MF21 of the traffic channel. In the MF21, at the k-th symbol period, the currently received base station a
Is used. Here, in order to perform soft handoff, the spreading code Pb for the base station b is used in the gap between the current correlation peaks in the (k + 1) th and (k + 2) th symbol periods. As a result, the correlation peak of both base stations can be detected, and after the (k + 3) th symbol period, signals from both base stations are received using Pa and Pb as appropriate.

FIG. 9 is a flowchart showing the details of the processing in FIG. 8, and when it is determined that a handover is necessary as a result of the peripheral cell search (step S1) (step S1).
2) First, the candidate BNC1 to BNCn of the new base station is specified (step S3). Here, the loop counter is initialized (step S4). Let the correlation peak of the current received signal be P
When c1 to Pcm are set, a correlation operation is first performed on BNCi in the gap between these peaks (step S5). Here, when it is determined that there is a peak (step S6), the peak position is determined (step S6).
8). If no peak exists, there is a possibility of overlap with the current correlation peak, so the correlation timing is delayed from the position of the peak Pc1 (step S1).
7) Adopt the first peak as the correlation peak for that base station. Then, the base station candidates are sequentially changed (step S12), and peak detection is performed (step S5).
When the peak detection has been completed for all the candidates (step S10), new base stations BN1 to BNp are specified (step S14). Thereafter, diversity handover (step S15), cyclic integration, and power calculation are performed to select one new base station (step S16).

In FIG. 10, the sample-and-hold circuit SH1 is connected to a switch SW43 to which an input signal Vi4 (corresponding to Vin in FIG. 1) is connected, an input capacitance C42 connected to the switch SW43, and to this input capacitance. An inverting amplifier circuit INV4, a feedback capacitance C connecting an output of the inverting amplifier circuit to an input;
41, and retains Vin when the SW 43 shifts from the closed state to the open state. INV4 has a refresh switch SW4 connected to its input / output in parallel with C41.
2, a refresh switch SW44 for connecting the reference voltage Vref is connected to the input of C42. The reference voltage is equal to the threshold voltage of INV4.
Is always Vref, so that when SW44 is closed, both ends of C42 are at the same potential and the charge is eliminated.
When SW42 is closed, both ends of C41 are short-circuited, so that the electric charge of C42 is eliminated. Further, a switch SW41 connected to the ground is connected to the input of the INV4. When the switch SW41 is closed, the input of the INV4 is connected to the ground, the CMOS constituting the INV4 shifts to a saturation region, and power consumption stops. Note that the other sample and hold circuits are configured in the same manner, and thus description thereof is omitted. The SHA1 shown in FIG. 5 has a configuration in which the two shown in FIG. 10 are connected in series via a switch, and the description thereof is omitted here.

In FIG. 11, the switch SW43 is connected to an input signal Vin5 by connecting a pMOS and an nMOS in parallel to a transistor circuit T5. The switch SW43 is connected to the output of this transistor circuit. A dummy transistor circuit DT5 whose output is short-circuited, and the gates of T5 and DT5 have CL
K0 and its inverse are input as control signals.
The control signal is supplied to the pMOS of T5 by the inverter I5.
And nMOS are mutually inverted, and the nMOS of DT5 is
And pMOS are mutually inverted. The other switches are configured in the same manner, and the description is omitted. Note that m1 to mn in FIG. 5 are spreading codes, which are supplied to MUX1 to MUXn without being circulated as in FIG.

FIG. 12 shows an adder circuit ADD, and outputs the first path outputs Vo11p to Vo11p to multiplexers MUX1 to MUXn.
Vo1np and second-path output Vo11m to Vo1nm
Are respectively connected to the capacitances Cp1 to Cpn,
Cm1 to Cmn are provided. The outputs of Cp1 to Cpn are integrated to form a capacitive coupling, and the output is input to the inverting amplifier circuit INV71. The output of INV71 is connected to its input via a feedback capacitance CF71. The outputs of Cm1 to Cmn are integrated to form a capacitive coupling, and the output is inverted by an inverting amplifier circuit INV.
72. The output of INV72 is connected to its input via a feedback capacitance CF72.
Further, the output of the INV 71 is input to the INV 72 via the intermediate capacitance CC7, thereby enabling addition and subtraction. Here, Cp1 to Cpn, Cm1 to Cm
The capacitance ratio of mn, CC7, CF71, CF72 is expressed by equation (1).
In this case, the output voltage Vout6 is expressed as Expression (2).

(Equation 1)

In FIG. 13, multiplexer MUX1
Is composed of a pair of multiplexers MUX91 and MUX92. The MUX91 has an input voltage Vin9 and a reference voltage Vref.
Pair of CMOS switches T91 respectively connected to
2, consisting of T911. On the other hand, the MUX 92 has the input voltage Vi.
n9, a pair of C connected to the reference voltage Vref, respectively.
It comprises MOS switches T921 and T922. T91
1, T922 is connected to Vin9, and T912, T9
Vref is connected to 21. MUX91, MU
X92 is controlled by a control signal Pct, and Pct is T9
11 nMOS, T912 pMOS, T921 nM
A signal which is input to each gate of the pMOS of OS and T922 and which is obtained by inverting Pct by the inverter I9 is T.
911 pMOS, T912 nMOS, T921 pMOS
MOS and the gate of the nMOS of T922. When Pct goes high, MUX 91
Becomes Vin9, and at the same time, the output m of MUX92.
Becomes Vref. Conversely, when Pct is at a low level, p
= Vref and m = Vin9. Note that the other multiplexers MUX2 to MUXn have the same configuration, and a description thereof will be omitted.

Although the input signal is an analog signal in the above embodiment, it goes without saying that a digital signal can be used as an input signal and the processing circuit can be a digital circuit.

[0036]

According to the signal receiving apparatus of the present invention, one or more matched filters are provided with a plurality of operation registers, and the plurality of operation registers are selectively connected to the corresponding matched filters by a register multiplexer. In addition, since signals from a plurality of base stations are intermittently received by one matched filter, it is possible to cope with soft handover and to have an excellent effect that the apparatus is small.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a matched filter according to the present invention.

FIG. 2 is a block diagram showing a register for storing a spreading code of the matched filter.

FIG. 3 is a block diagram showing a phase / multiplexer in FIG. 2;

FIG. 4 is a timing chart showing an operation of the matched filter.

FIG. 5 is a block diagram showing another matched filter.

FIG. 6 is a block diagram showing a circuit subsequent to the matched filter.

FIG. 7 is a timing chart showing the operation of another embodiment.

FIG. 8 is a timing chart showing the operation of still another embodiment.

FIG. 9 is a flowchart of the embodiment of FIG.

FIG. 10 is a circuit diagram showing a sample and hold circuit in FIG. 1;

11 is a circuit showing a switch in FIG.

FIG. 12 is a circuit diagram showing the addition circuit of FIG. 1;

FIG. 13 is a circuit diagram illustrating the multiplexer of FIG. 1;

[Explanation of symbols]

SH1 to SHn, SHEX, SHA1 to SHAn, SH
p1 to SHpS, SHt1 to SHtR. . . Sample hold unit MUX1 to MUXn, SMUX1 to SMUXn, MUX
p1 to MUXpS, MUXt1 to MUXtR, MUX3
1, MUX32, CMUX, RMUX, MUX31-
MUX3n. . . Multiplexers SEL1 to SELn. . . Selector ADD. . . Adder circuit SCALER. . . Scalers MF01, MF02, MF11, MF12, MF21,
MF22, MF23, MF24. . . Matched filter Pch. . . Perch channel group Cch. . . Shared group Tch. . . Traffic channel group PDp, PDt. . . Peak detection circuit DECp, DECt. . . Decoders ADp1 to ADpS, ADt1 to ADtR. . . A / D
Converters MEM31, MEM32. . . Memory PC31, PC32. . . Fading compensation circuits RCMB31, RCMB32. . . Rake combining circuit INP-REG. . . Input registers CAL-REG1, CAL-REG2. . . Operation register SW41, SW42, SW43, SLSW1, SRSW
1, SLSW2, SRSW2, RSW. . . Switches C41, C42, Cp1 to Cpn, Cm1 to CMn, C
C7. . . Capacitance INV4, INV71, INV72. . . Inverting amplifier circuits I5, I9. . . Inverters T911, T912, T921, T922. . . CMO
S switch Pct. . . Pre-control signal Vref. . . Reference voltages Vin, Vi4, Vin5, Vo11p to Vo1np,
Vo11m to Vo1nm, Vin9. . . Input voltage Vout, Sout1, Sout2, Vo4, Vout
6. . . Output voltage. 1 Reference number = YZ1977074A

Claims (10)

[Claims] 1. A plurality of sample-and-hold circuits for holding an input signal in time series; a plurality of matched filters for calculating a correlation between an input signal held in these sample-and-hold circuits and a spreading code; And an operation register for storing the spread code and supplying the spread code to the matched filter; and a plurality of matched filters including a long code specifying a base station and a short code specifying a mobile station. In a signal receiving apparatus of a DS-CDMA cellular system using a synthesized code as the spreading code, one or more matched filters are provided with a plurality of operation registers, and the plurality of operation registers are selectively provided by a register multiplexer. , Connected to the corresponding matched filter, which allows multiple base stations A signal receiving apparatus for a DS-CDMA cellular system, wherein a soft handover is performed by supplying a corresponding spreading code to the matched filter. 2. The circuit according to claim 1, wherein the sample and hold circuit is connected in parallel with the input signal and controlled so as to sequentially take in the input signal, and the arithmetic register cyclically shifts in synchronization with the sampling timing of the sample and hold circuit. 2. The signal receiving device of the DS-CDMA cellular system according to 1. 3. A sample-and-hold circuit comprising a series connection from an initial-stage sample-hold circuit connected to an input signal to a final-stage sample-hold circuit, and the input signal is transferred through these sample-hold circuits toward the final stage. The signal receiving device of a DS-CDMA cellular system according to claim 1, wherein: 4. A phase shifter between an arithmetic register and a register multiplexer or a register multiplexer.
A multiplexer is provided, which outputs the spread code of the operation register to the matched filter as a data string corresponding to the current cyclic shift state or the previous cyclic shift state, and simultaneously correlates with the spread codes of a plurality of operation registers. At the timing of peak overlap where a peak occurs, the phase / multiplexer is switched to perform a correlation operation by the plurality of operation registers while maintaining a cyclic shift state at the same timing, thereby avoiding all peak overlaps. D according to claim 2
Signal receiving device for S-CDMA cellular system. 5. The apparatus according to claim 1, further comprising a plurality of sub-sample and hold circuits connected to the input signal in parallel with the sample and hold circuit. Before (one symbol period minus one chip time),
(1 symbol period-2 chip time) before,. . . , (1 symbol period-(d-1) chip time) before (d is a natural number)
Are sequentially stored in the sub-sample and hold circuit, and when the correlation operation is performed by the plurality of operation registers, the first operation register performs the correlation operation using the input signal of the sample and hold circuit, and the other operation registers perform the sub operation. 3. A signal receiving apparatus for a DS-CDMA cellular system according to claim 2, wherein the input signals of the sample and hold circuit are sequentially used. 6. The apparatus according to claim 1, further comprising one or more sub-sample-and-hold circuits connected to the input signal in parallel with the sample-and-hold circuit. While sequentially storing, the correlation operation is performed by the signal of the sample and hold circuit and the spreading code of the operation register,
While storing the latest input signal in the sub-sample and hold circuit, a correlation operation is performed using the signal of the sample and hold circuit and the spreading code of each operation register. 3. A signal receiving apparatus for a DS-CDMA cellular system according to claim 2, wherein a sub-sample-and-hold circuit is used in place of the sample-and-hold circuit to store the data. 7. A matched filter is assigned to a perch channel and a traffic channel, performs a path search for signals of a plurality of base stations to be received using the matched filter in the perch channel, and, based on a result of the path search, performs a traffic search. 2. The signal receiving apparatus for a DS-CDMA cellular system according to claim 1, wherein signals from a plurality of base stations are received by one matched filter of a channel. 8. A path search of a plurality of base stations by switching a spreading code for each symbol period in one matched filter of a traffic channel, and based on a result of the path search, a plurality of base stations are matched by the matched filter. 2. The signal of claim 1,
A signal receiving apparatus for the DS-CDMA cellular system according to claim 1. 9. A connection relationship between the operation register and the sample-and-hold circuit in synchronization with the transfer of the input signal so that the correspondence between the input signal stored in the sample-and-hold circuit and the spread code in the operation register is kept constant. At the timing of peak overlap in which correlation peaks occur simultaneously due to the spread codes of a plurality of operation registers, the correlation operation by these operation registers is performed sequentially, and accordingly, the shift operation follows the shifted input signal. 4. The signal receiving apparatus for a DS-CDMA cellular system according to claim 3, wherein the selector is switched so as to perform the operation, and thereafter, the selector is returned to the original state, thereby avoiding duplication of all peaks. 10. When the overlap of correlation peaks occurs consecutively a plurality of times, a correlation operation by a plurality of operation registers is sequentially performed on each of the overlaps of peaks, so as to follow the shifted input signal. Switch the selector to
10. The DS- according to claim 9, wherein after completion of the correlation operation corresponding to all peak duplications, the selector is returned to the original state, thereby avoiding all peak duplications.
Signal receiving device for CDMA cellular system.