JPH11214981A - Level shift circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a level shift circuit which suppresses the fluctuations of a signal delay time which is caused by the change in high voltage side power supply voltage. SOLUTION: This level shift circuit is provided with a 1st P-channel type MOS transistor 5 and an N-channel type MOS transistor 7, which are connected serially between a high voltage power supply VDDH and a ground, an input terminal IN that is connected to the gate of each 1st transistor, a 2nd P-channel type MOS transistor 6 and an N-channel type MOS transistor 8 which are connected serially between a low voltage power supply VDDL and a ground, an output terminal OUT of a serial circuit of each of the 2nd transistors and a circuit which inputs an output of a serial circuit of each of the 1st transistors to each of the 2nd transistors, connects the gate of the transistor 8 to an output side of the serial circuit of each of the 1st transistors via a 3rd N-channel type MOS transistor 9 and also connects the gate to the supply VDDL.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a level shift circuit for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art The power consumption of semiconductor integrated circuits (hereinafter referred to as "LSIs") has been increasing with the increase in speed and integration. To suppress this, the power supply voltage of the LSIs must be reduced. If the power supply voltage of the LSI cannot be reduced,
Usually, a level shift circuit is used between the high voltage side circuit and the low voltage side circuit. Hereinafter, a conventional level shift circuit will be described with reference to the drawings.

FIG. 2 is a circuit diagram of a conventional level shift circuit for driving a low voltage side circuit from a high voltage side circuit.
VDDH is a high voltage side power supply, VDDL is a low voltage side power supply, I
N is an input terminal whose input signal potential changes between 0 and the potential of the high voltage power supply VDDH, OUT is an output terminal whose output signal potential changes between 0 and the potential of the low voltage power supply VDDL, and 1 is A P-channel type MO having a gate connected to the input terminal IN and a source connected to the high voltage power supply VDDH;
The S transistor (hereinafter referred to as PMOS) 2 has a gate connected to the drain of the PMOS 1 and a source connected to the low-voltage side power supply V.
N-channel type MOS transistors (hereinafter referred to as NMOS) having a gate connected to the input terminal IN, a source connected to the ground, and a drain connected to the drain of the PMOS 1, respectively. An NMOS having a gate connected to the gate of the PMOS2, a source connected to the ground, and a drain connected to the output terminal OUT, respectively, constitutes a level shift circuit as a whole.

The operation will be described below. First, the input I
When a signal having the same potential as the high-voltage power supply VDDH is input to N, the NMOS 3 turns on and the drain of the PMOS 1 and N
The connection point of the drain of MOS3 is at the ground level,
OS2 is turned on, and the voltage of the low voltage side power supply VDDL is output to the output terminal OUT. Next, when a ground level signal is input to the input IN, the PMOS 1 is turned on and the NMOS 4 is turned on.
, The potential of the high-voltage power supply VDDH is applied, and the NMOS 4 is turned on. At this time, the gate potential of the PMOS 2 becomes higher than the potential of the source, the PMOS 2 is turned off, and the ground level is output to the output terminal OUT.

[0005]

However, in such a configuration, when the potential of the high-voltage side power supply VDDH changes, the current capability changes due to a change in the High level of the gate potential of the NMOS 4 and the current capability changes from the input IN. There is a problem that the signal delay time to the output OUT fluctuates greatly.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a level shift circuit capable of suppressing a change in a signal delay time due to a change in a power supply voltage on a high voltage side.

[0007]

A level shift circuit according to the present invention comprises: a first P-channel MOS transistor and an N-channel MOS transistor connected in series between a high voltage power supply and a ground; An input terminal connected to the gate of the second transistor, a second P-channel MOS transistor and an N-channel MOS transistor connected in series between the low-voltage power supply and the ground, and an output terminal of a series circuit of the second transistors. A level shift circuit including a circuit for inputting an output of a series circuit of each of the first transistors to each of the second transistors, wherein a gate of the second N-channel MOS transistor is connected to a third N-channel MOS transistor. Connected to the output side of the series circuit of each of the first transistors via a MOS transistor, and the gate thereof is connected to the low voltage Which are connected to the source.

According to the present invention, it is possible to suppress a delay time variation of a signal from an input to an output based on a change in a high-voltage-side power supply voltage.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a level shift circuit according to an embodiment of the present invention. Note that the same reference numerals are used for the same parts as those of the conventional one.

In FIG. 1, VDDH is a high voltage side power supply,
VDDL is a low voltage side power supply, IN is an input terminal whose input signal potential changes between 0 and the potential of the high voltage side power supply VDDH, OUT is an output signal potential between 0 and the potential of the low voltage side power supply VDDL. The changing output terminal 5 has a gate connected to the input terminal IN and a source connected to the high-voltage power supply VD.
A first PMOS 6 connected to DH has a gate of PMO.
S5, and the source is connected to the low-voltage side power supply V.
A second PMOS 7 connected to the DDL and having a drain connected to the output terminal OUT, a first NMOS 7 having a gate connected to the input terminal IN, a source connected to ground, and a drain connected to the drain of the first PMOS 5; 8 is a second circuit in which the source is connected to the ground and the drain is connected to the output terminal OUT.
NMOS 9 has a gate connected to the low-voltage side power supply VDDL.
And the drain (source) is connected to the second PMO
Connected to the gate of S6 and the source (drain) is
The third NMOS is connected to the gate of the MOS 8, so that the low-voltage power supply VD is connected to the gate of the second NMOS 8.
This is to prevent a potential higher than the potential of DL from being applied.

The operation will be described below. First, the input I
When a signal having the same potential as the high-voltage side power supply VDDH is input to N, the first NMOS 7 is turned on and the first PMOS 5 is turned off, so that the drain of the first PMOS 5 and the first N
The connection point of the drain of the MOS 7 is at the ground level,
Are turned on. At this time, the third NMOS 9 is turned on and the ground level is applied to the gate of the second NMOS 8 to turn it off. Therefore, the output terminal OUT outputs the potential of the low-voltage power supply VDDL set lower than the potential of the high-voltage power supply VDDH.

Next, when a ground level signal is input to the input IN, the first PMOS 5 is turned on, and the first NMOS 5 is turned on.
7 is turned off, the potential of the high-voltage power supply VDDH is applied to the gate of the second PMOS 6, and the second PMOS 6 is turned off.
Turns off. At this time, the potential of the high-voltage power supply VDDH is applied to the drain of the third NMOS 9, but the gate potential is VDDL lower than the potential of the high-voltage power supply VDDH. Power supply VD
Regardless of the potential of DH, the potential becomes lower than the potential of VDDL by the threshold value, the second NMOS 8 turns on, and the output terminal OU
The ground level is output to T. Therefore, even if the potential of the high-voltage power supply VDDH fluctuates, the gate potential of the second NMOS 8 becomes a constant value by the NMOS 9 and its capability does not change, so that the fluctuation of the delay time from the input IN to the output OUT is suppressed. You.

As described above, according to the present embodiment, the gate potential of the second NMOS to which signals having different amplitudes are input is set such that the third NMOS does not apply a potential higher than the potential of the low-voltage power supply VDDL. The second N
The capacity of the MOS does not change, so that the change in the delay time due to the change in the power supply voltage on the high voltage side can be suppressed despite the simple circuit.

[0014]

As described above, according to the present invention, there is obtained an advantageous effect that the fluctuation of the delay time due to the fluctuation of the high voltage side power supply voltage can be suppressed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration of a level shift circuit according to an embodiment of the present invention;

FIG. 2 is a circuit diagram of a conventional level shift circuit.

[Explanation of symbols]

1, 2 P-channel MOS transistors 3, 4 N-channel MOS transistors 5, 6 First and second P-channel MOS transistors 7, 8 First and second N-channel MOS transistors 9 Third N-channel Type MOS transistor

Claims (1)

[Claims] A first P-channel MOS transistor and an N-channel MOS transistor connected in series between a high-voltage side power supply and ground; an input terminal connected to a gate of each of the first transistors; A second P-channel MOS transistor and an N-channel MOS transistor connected in series between a voltage side power supply and ground;
A level shift circuit including an output terminal of a series circuit of transistors and a circuit for inputting an output of the series circuit of each first transistor to each of the second transistors, wherein the second N-channel MOS A gate of the transistor is connected to an output side of a series circuit of the first transistors via a third N-channel MOS transistor, and a gate of the third N-channel MOS transistor is connected to the low-voltage side power supply. A level shift circuit characterized by being connected.