JPH11212942A - Interconnection net work method of large scale parallel processing computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a communication bandwidth wide and also to reduce a delay time by connecting an inverse graph topological interconnection network to a crossbar switch or a high speed bus. SOLUTION: A four-element two dimensional interconnection network connects four nodes (e.g. CSX0 or CSY0) of one row or one column by a 4×4 crossbar switch (or a high speed bus). When a delay time until information arrives from one node to another node through the crossbar switch is tCS and a time until it arrives from one node to an adjacent node through one router is tR, network delays from a node N000 at the lower left to nodes N330 and N331 at the upper right become 2 (tCS+tR) and 2tCS+tR respectively. Also, the number of horizontal and vertical crossbar switches is four respectively. Then, it is possible to increase the number of nodes by more than double without increasing hardwares very so.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the technical field of computers, and more particularly to a new interconnection network method for a large-scale parallel processing computer system.

[0002]

2. Description of the Related Art A computer system having a parallel processing function has a plurality of processors, which perform parallel processing and communicate with each other through an interconnected network. Requirements for interconnected networks include strong functionality, low communication delay, high data transfer rate (ie, wide communication bandwidth), low hardware complexity, and good scalability. Conventionally known interconnected networks include a bus, a crossbar switch, an interconnected network interconnected by a k-element n-dimensional cube, and the like. Next, the principle of operation of these interconnection networks will be described.

FIG. 1 illustrates the principle of connecting a plurality of processors to each other by a conventional bus. The plurality of processors are connected to each other by a bus B, and communication between the plurality of processors uses the bus B in a time-division manner. Do by doing. That is, when communicating between two processors,
Other processors must wait, and after their communication is complete, other processors can use bus B.
The advantage of an interconnected network interconnected by buses is that the cost is lower, but there is the problem that the available bandwidth of each processor is smaller and less scalable. The number of processors that can be connected to the bus is usually four to eight.

FIG. 2 is a principle diagram showing a crossbar switch. PEi (i = 0, 1,..., 7) in FIG. 2 represent processors, and each processor can simultaneously transmit and receive. The transmitting end of one processor is connected to the receiving end of another processor through a crossbar switch as required. Turn ON or O the cross point of the crossbar switch
It can be set to FF, and a portion having a black point at an intersection in FIG. 2 represents ON, and a portion having no black point represents OFF. For example, in FIG.
Indicates that the receiving end of E0 is connected. ON only one crossing point in each row or each column of the crossbar switch
It can be. In FIG. 2, eight cross points are ON at the same time, that is, communication can be performed simultaneously between eight pairs of processors. The advantage of the crossbar switch is that when the communication bandwidth of the interconnection network is wide, the delay is small, and the number of processors is 4 to 8, the crossbar switch is an ideal interconnection network. The complexity of the ware increases with the square of the number of processors, and when the number of processors is large, the cost is very high, and thus there is a problem with the scalability of the crossbar switch.

In a large-scale parallel processing computer system having a large number of processors, an interconnected network is almost k
An interconnected network of original n-dimensional cubes or a variant thereof is used. A two-dimensional interconnected network is a simplified k-ary n-dimensional cubic interconnected network, where n = 2
It is what it was. In a two-dimensional interconnection network as shown in FIG. 3, k = 4. The horizontal and vertical lines in the two-dimensional interconnected network represent network channels (eg, CC), and the black dots at the intersection of the horizontal and vertical network channels represent routers (eg, R03). The router sends the received data to the destination based on a routing algorithm and a routing mechanism.

Each router in FIG. 3 has five terminals, four of which are connected to a network channel (ie, two terminals are horizontal network channels and the other two are vertical network channels). The remaining one terminal is connected to a processor node (for example, N00) indicated by a circle. Processor nodes are referred to below as nodes. One node may include one processor, or may include a plurality of processors.

FIG. 4 shows a quaternary cube interconnected network. As shown in FIG. 4, vertical and horizontal lines represent network channels (eg, CC), and black dots represent routers (eg, N000). The routers and network channels hidden in the figure are not shown, but the nodes connected to the routers are not shown. Assuming that the number of nodes is N in the interconnection network, N = kn in a k-element n-dimensional cubic interconnection network. When k and n are given, the value of N also becomes a definite value. Compared with the crossbar switch, the k-element n-dimensional cubic interconnection network has good expandability, but has a problem that the interconnection network has a large delay. As shown in FIG. 3, it is necessary to pass at least seven routers from the lower left node N00 to the upper right node N33.

In a k-element n-dimensional cubic interconnected network, when n> 1, k> 2, the number of network channels is larger than the number of routers. When a processor node is not connected to a router but is connected to a network channel, it becomes an inverse graph topological interconnected network. FIG. 5 shows such a two-dimensional inverse graph topological interconnected network. In FIG. 5, the number of nodes is the same as in FIG. 3, but the number of routers and network channels is reduced by half compared to FIG. FIG. 5 shows a straight line, a circle and a black dot in FIG.
Is the same as Inverse graph topological interconnected networks are effective for optical interconnected networks with very wide communication bandwidths, but the cost of optical interconnected networks is high and the conversion of photoelectrics is complex. For electrical interconnected networks, the reduced number of network channels reduces the average communication bandwidth of each processor, affecting high-speed data transfer.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a new type of interconnected network technology for a large-scale parallel processing computer system, and to provide each processor of a large-scale parallel processing computer system having a large number (for example, more than 10,000) of processors. Solve the problem of interlocking.

[0010]

SUMMARY OF THE INVENTION The present invention combines the advantages of an inverse graph topological interconnection network and a crossbar switch or high-speed bus, and proposes a new interconnection network suitable for a large-scale parallel processing computer system. Such a new type of interconnected network has a wide communication bandwidth, short delay time, and good expandability. The first purpose of the inverse graph topological interconnected network is to reduce the number of routers and network channels, but in terms of the number of nodes, for the same number of k and n, k-ary n-dimensional inverse graph topological interconnected network Can connect more nodes than the k-ary n-dimensional cubic interconnected network. In the four-dimensional two-dimensional inverse graph topological interconnection network shown in FIG. 6, the number of connected nodes is 32, which is twice as large as the 16 nodes in FIG.
What is represented by a straight line, a circle, and a black point in FIG. 6 is the same as that in FIG. When the number of nodes that can be connected in the inverse graph topological mutually connected networks and N _IG, 2
For dimensions, N _IG = 2N, for three dimensions, N _IG = 3N
Where N _IG = nN for n dimensions.

In an octagonal inverse graph topological interconnected network, the number of nodes is 3 × 8
³ = 1536, and if one node is connected to eight processors, 12288 processors can be connected to the interconnection network. However, in a normal 8-element cubic interconnected network, the number of nodes is only 8 ³ = 512. Similarly, when 8 processors are connected to one node, only 4096 processors are connected to the interconnected network. Can be connected.

Although the number of nodes can be increased in the inverse graph topological interconnection network, the number of average channels of each node is reduced, and the communication bandwidth is relatively narrowed. Wide communication bandwidth,
In order to reduce network delay and to reduce network delay, the present invention constructs a new interconnection network by placing a small number of crossbar switches (or high-speed buses) in the inverse graph topological interconnection network. The present invention combines an inverse graph topological interconnection network with a crossbar switch or high-speed bus so that in the inverse graph topological interconnection network, processor nodes are connected to network channels instead of connecting to routers. , K nodes of the same row and the same column of the inverse graph topological interconnected network are connected by using a k × k crossbar switch or a high-speed bus to form a new interconnected network. The k-ary n-dimensional cubic new interconnected network can be regarded as one super node, and a large-scale computer system can be composed of a plurality of super nodes. Connected using the new Node 互連 contact network comprising a plurality of terminals, if there are three terminals,
Two of them are connected to the network channel,
The third terminal is connected to a crossbar switch or a high-speed bus,
If there are four terminals, the fourth terminal is connected to the high-speed bus connecting the super nodes, and the three terminals of the node of the new interconnection network are composed of four-terminal high-speed cache memory,
Two terminals of the terminal high-speed cache memory connect the node to the network channel, one terminal connects to the inside of the node, and the other terminal connects to the crossbar switch or the high-speed bus. I do.

[0013]

DETAILED DESCRIPTION OF THE INVENTION Further, in order to sense <br/> solutions features and advantages of the present invention will be further described the present invention based on drawings. FIG. 7 shows a four-dimensional two-dimensional advanced interconnection network. The dotted line in FIG. 7 indicates that four nodes in one row or one column are connected by a 4 × 4 crossbar switch (or high-speed bus) (for example, CSX0 or CSY0). Information is the delay time from one node to via the crossbar switch (or high-speed bus) reaches the other one of the nodes and t _CS, information of the adjacent via one router from one node Assuming that the time required to reach the node is t _R , as shown in FIG. 7, the network delay from the lower left node N000 to the upper right node N330 and node N331 is 2 (t _CS + t _R ) and 2t _CS + t, respectively. Become _R. The network delay between adjacent nodes is only t _CS or t _R. k = 8, and 8 × 8 crossbar switch (or high-speed bus)
, The maximum delay of the network is 2 (t _CS + t _R )
become. As shown in FIG. 7, the number of crossbar switches (or high-speed buses) used is four in each of the horizontal and vertical directions, for a total of eight. Therefore, in the new interconnection network of the present invention, the number of network nodes can be more than doubled without increasing the hardware much. In other words, even if the new interconnection network of the present invention combines the advantages of the inverse graph topological interconnection network and the crossbar switch (or high-speed bus), these problems do not occur.

FIG. 8 shows another two-dimensional advanced interconnection network. Figure 7 shows the new interconnected network.
7 is similar to the interconnected network shown in FIG.
8 is provided along the network channel including the nodes in FIG.
Is provided vertically (for example, CSX0 or CSY0) with a crossbar switch (or high-speed bus) perpendicular to the network channel including the node. 7 and 8 have the same maximum delay time and the same number of crossbar switches (or high-speed buses). If a k × k crossbar switch (or high-speed bus) is used for a k-ary cubic interconnected network, the maximum delay time of the network is 3 (t _CS + t _R ).

The new interconnection network has good scalability. One k-ary n-dimensional cubic new interconnection network can be regarded as one super node, and a plurality of super nodes can become a larger-scale parallel processing computer system. As shown in FIG. 9, if the quaternary two-dimensional new interconnection network of FIG. 7 is made into one super node, a 16-element two-dimensional new interconnection network can be formed from more than 16 nodes, and the corresponding node of the super node Connect by highway bus. The dotted grid in FIG. 9 represents super nodes (for example, SN00), and each super node has 32 nodes (one row and one column, only eight nodes are shown in the figure). A high-speed bus (for example, HSBX0) connecting the super nodes is represented by a thick line, a node (for example, N301) in the super node is represented by a circle, and a crossbar switch (or a high-speed bus) that connects four nodes inside the super node ( For example, CSX3) is represented by a thin line. The number of nodes connected to the expanded new interconnection network has increased 16 times from the original, that is, from the original 32 to 512. Each super node is connected to another super node in the same row or column by 32 buses. In this case, the network delay is not only the delay inside the super node, but also the delay of the two buses and the associated connecting circuit.

Similarly, if the k-ary cubic new interconnection network is a super node, and from such a plurality of super nodes to a larger cubic new interconnection network, the number of nodes can be further increased, And the network delay will only increase the delay of the three buses and associated direct circuits. FIG. 10 shows a new type of interconnected network consisting of 64 nodes. One small cube in the figure represents one super node (for example, SN030), and each super node is composed of an eight-way cube new interconnection network. If one node of each supernode contains two processors, this interconnected network becomes 3 × 8 ³ × 2 × 64 = 1966
You can connect up to 08 processors. If the operation speed of each processor is 500 million operations per second, the operation speed of such a large-scale parallel processing computer system is 100 trillion operations per second.

The new interconnected network proposed in the present invention can connect thousands, tens of thousands, and even more processors, including crossbar switches, k-ary n-dimensional cubic interconnected networks, and inverse graph topological interconnected networks. And the disadvantages do not occur. Compared with the crossbar switch (high-speed bus), the new interconnected network has better scalability, and compared with the k-ary n-dimensional cubic interconnected network, the new interconnected network is more for the same size interconnected network. A large number of processors can be connected and the network delay time is short. Compared with the k-ary n-dimensional cube inverse graph topological interconnected network, the new interconnected network has a wider communication bandwidth and a shorter network delay time. Therefore, the advantages of the new interconnection network proposed in the present invention are as follows: a large number of processors can be connected, the number of processors can be thousands, tens of thousands, and even more; Is shorter, the communication bandwidth is wider, and the scalability is better.

In the new interconnection network, FIG.
As shown in 1, 2, and 3, the node has three terminals, the terminal 1 is connected to the crossbar switch (high-speed bus), and the terminals 2 and 3 are connected to the network channels CC on both sides of the node. The three terminals of the node can be realized by a four-terminal high-speed cache memory.

FIG. 12 is a block diagram of one row or one column of FIG. The four terminals of the four-terminal memory in the figure are respectively connected to two network channels CC, a 4 × 4 crossbar switch (high-speed bus), and a bus inside the node. Using a four-terminal memory for a node requires only four
One terminal connects the node to the network channel conveniently, the memory can temporarily store the data of the closed interconnected network, so that the structure of the router can be simplified, and the node can be connected to the network channel. The feature is that the number of terminals does not need to be changed for two, three, or higher dimensions, since the number of terminals is independent of the number of dimensions of the interconnected network. . The use of a four-terminal memory for a node is a key point of the novel interconnected network technology of the present invention.

In an interconnected network of supernodes, connections between supernodes can be made in several different ways. One of the methods is shown in FIG.
As in 2, 3, and 4, the node has four terminals, terminals 2 and 3 are connected to the network channels CC on both sides of the node, terminal 1 is connected to the high-speed bus inside the super node, and terminal 4 is Connect to the high-speed bus connecting the super nodes. The connection between the super nodes may be connected using a multi-level connection method or another method. In the new interconnection network, since the nodes do not connect to the router, the structure of the router can be simplified because the router need not have one terminal than the router of the usual k-dimensional n-dimensional cubic interconnection network. As shown in FIG. 14, for the new two-dimensional interconnected network, the router only needs to perform data transfer between the horizontal network channel X and the vertical network channel Y. On the other hand, the router is X, Y
It is only necessary to perform the data transfer between the three-way network channels Z and Z.

The network channels and high-speed buses of the new interconnected network use electrical transfer lines, but may use optical fibers. Further, an electric transfer line may be used for short-distance transfer, and an optical fiber may be used for long-distance transfer. An optical fiber may be used for all the network channels. In this case, the function of the router may be realized by optical signals of different wavelengths on the same optical fiber.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a plurality of processors connected by a conventional bus.

FIG. 2 is a schematic diagram showing a conventional crossbar switch interconnection network.

FIG. 3 is a schematic diagram showing a conventional four-dimensional two-dimensional interconnected network.

FIG. 4 is a schematic diagram showing a conventional quaternary cubic interconnection network.

FIG. 5 is a schematic diagram showing a conventional two-dimensional inverse graph topological interconnection network.

FIG. 6 is a schematic diagram illustrating a quaternary two-dimensional inverse graph topological interconnected network.

FIG. 7 is a schematic diagram illustrating an embodiment of a new four-dimensional two-dimensional interconnected network of the present invention.

FIG. 8 is a schematic diagram showing another embodiment of the new four-dimensional two-dimensional interconnection network of the present invention.

FIG. 9 is a schematic diagram of connecting corresponding nodes in the super node of the present invention through a high-speed bus.

FIG. 10 is a schematic diagram illustrating an interconnected network of 64 supernodes of the present invention.

FIG. 11 is a schematic diagram showing a three-terminal node of the present invention.

FIG. 12 is a schematic diagram showing one row or one column of the present invention shown in FIG. 7;

FIG. 13 is a schematic diagram showing a four-terminal node of the present invention.

FIG. 14 is a schematic diagram showing the function of a router of the two-dimensional new interconnection network of the present invention.

Claims (2)

[Claims] 1. An inverse graph topological interconnection network coupled to a crossbar switch or a high-speed bus, wherein in the inverse graph topological interconnection network, a processor node is connected to a network channel instead of being connected to a router; A new interconnected network is constructed by interconnecting k nodes of the same row and column of the inverse graph topological interconnected network using k × k crossbar switches or high-speed buses, respectively. The k-ary n-dimensional cubic new interconnected network can be regarded as one super node, a large-scale computer system can be formed from a plurality of super nodes, and a corresponding node among the super nodes can be processed at high speed. Connected using a bus, Node of the serial new mutual articulation network comprising a plurality of terminals, if there are three terminals, two terminals therein and connected to the network channel, the third
A terminal is connected to the crossbar switch or the high-speed bus, and when there are four terminals, a fourth terminal is connected to a high-speed bus connecting the super nodes. A new type of interconnected network method. 2. The three terminals of the node of the new interconnection network comprise a four-terminal high-speed cache memory. Two terminals of the four-terminal high-speed cache memory connect the node to a network channel, and one terminal has 2. The new interconnection network method for a large-scale parallel processing computer system according to claim 1, wherein the other one terminal is connected to the inside of the node, and another terminal is connected to the crossbar switch or the high-speed bus.