JPH11203160A - Testing method for data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a testing method for a data processor which avoids the generation of an instruction string that becomes failure due to the same factor and is more efficient with high accuracy. SOLUTION: This method generates a test instruction group through a prescribed test instruction group generation condition with a random number as an input, simulates an instruction of a tent instruction group, produces expectation, executes the same instruction on a test object device, gets an execution result, compares the execution result with the expectation, retrieves an instruction that becomes noncoincidence, analyzes the cause and changes a test instruction group generation condition that corresponds to an error cause. Tests for count which designates the operation are carried out and are repeated until they are finished.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing a data processing device, and more particularly to a method for randomly generating a test instruction group to test a processing function of a data processing device under test.

[0002]

2. Description of the Related Art As a technique for supporting high performance of a data processing apparatus, a pipeline processing method in which an instruction is divided into several processing stages and each apparatus (unit) processes a specific stage every one machine cycle is used. Widely adopted. The pipeline processing, which is also called the advance control function, is realized by a complex and large-scale logic, and the degree of the advance control is becoming very deep year by year. For that reason,
For the verification of the advanced control function, a test under a condition that a high load is applied to a data processing device (instruction processor) is important due to the generation of a complicated function combination due to an increase in the number of test instruction groups.

A conventional technique of a random number test program for generating a test instruction group with random number data as an input in a test program for logic verification will be described. Japanese Patent Application Laid-Open No. 8-166892 discloses a method for generating a large-scale test instruction for executing a pipeline processing test in a high-load environment by using a random-number test program that generates a test instruction group by using random number data as an input. A method has been disclosed which makes it easy to find out the cause of the failure by extracting a group of instructions that cause the generation of a test instruction, and enables generation of a large-scale test instruction. But,
Due to the nature of repeating a test using random number data, there is a high probability that an instruction group that generates a defect due to the same factor is generated many times, and the test and defect analysis efficiency is reduced.

[0004]

In the prior art, since the instruction sequence is generated only from the random number data, the test performed in the past is repeated many times. For this reason, an instruction sequence for extracting a defect caused by the same factor is generated many times, resulting in a large number of defects caused by the same factor. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-described problems and to provide a more efficient and more accurate test method for a data processing device by avoiding generation of a defective instruction sequence due to the same factor.

[0005]

In order to achieve the above object,
In the method of repeatedly generating a test instruction group based on a predetermined test instruction group generation condition with random number data as an input and causing the data processing device under test to execute the test instruction group to test the data processing device, the test instruction created by simulation If a mismatch occurs due to a comparison between the expected value of the execution result of the group and the execution result of the data processing device, an instruction and a target function that caused the mismatch are found, an error cause is analyzed, and a test corresponding to the error cause is performed. After changing the instruction group generation condition, the test is continued.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention showing a configuration of a test apparatus of an information processing apparatus. In FIG. 1, the test apparatus generates a test instruction detailed information table (109), a test instruction group (110), and an initial execution value (111) using an instruction generation rate table / function construction rate table (113) and a random number. Test instruction group generation unit (1
01 and the test instruction group (11
0), an instruction simulating unit (102) for generating an expected value (114), and an initial execution value (111).
The test instruction group execution unit (103) for executing the test instruction group (110) by the information processing device to be tested to obtain the execution result value (115), the expected value (114) and the execution result value (115) , An execution result comparison unit (104) for detecting a mismatch, a test instruction group (110), and an execution initial value (1).
11), an error instruction extracting unit (105) for extracting an instruction that generates an error result from the expected value (114) and the execution result value (115), and a test instruction detailed information table (1).
09), test instruction group (110), execution initial value (11
1), instruction generation rate table / function construction rate table (113), expected value (114), and execution result value (11)
The cause of the error is analyzed from 5), and the error analysis result (112)
, An instruction generation rate adjustment unit (107) that updates the instruction generation rate table / function construction rate table (113) using the error analysis result (112), and an error analysis result (112). ), An error message output unit (108) for creating an error message (116) from the expected value (114) and the execution result value (115).

FIG. 2 is a flowchart showing the processing of the entire test apparatus of FIG. A test instruction detailed information table, a test instruction group, and an initial execution value are generated by inputting the instruction generation rate table / function construction rate table and the random number value (201), and the expected value is created by simulating the instructions of the test instruction group (201). 202). Thereafter, the same instruction is executed on the test target device to obtain an execution result value (203), the execution result value is compared with an expected value and checked (204), and an instruction for generating an unmatched execution result value is searched (205). An error analysis result is generated by analyzing the cause of the mismatch of the result of the instruction searched in (205) (206). The instruction adjustment rate adjustment unit (207) updates the instruction generation rate table / function construction rate table based on the analysis result obtained in the error cause analysis (206) so that the same factor defect does not occur. This operation is repeated until the specified number of tests are completed (208).

FIG. 3 is a diagram showing a format of each table used in the embodiment of the present invention. The test instruction detailed information table (301) includes, for each generated instruction, detailed information such as the instruction type, the instruction type, the format, the register number used, and the address accessed if the generated instruction is a memory access instruction. Written.
In the function construction rate table (302), the appearance frequency of the function realized by the generated instruction sequence is set. In the instruction generation rate table, the occurrence frequency of each instruction type corresponding to each function to be realized by the instruction sequence to be generated is written (303), and the occurrence frequency of each instruction type in the instruction type is conflicted. There is one in which the width and its frequency are written (304).

FIG. 4 is a data flow diagram showing the processing of the instruction generation rate adjusting unit. If the purpose is to test the FR conflict function and the floating operation instruction causes a pipeline operation failure (401), the function construction rate is updated so as to reduce the frequency of occurrence of the floating operation register conflict test (402). Then, the instruction generation rate is updated so as to reduce the frequency of occurrence of the error-conflict width of the erroneous instruction (403). By this operation, generation of an instruction pattern that causes an error can be suppressed.

FIG. 5 is a data flow showing a test instruction group generation method during the processing of the test instruction group and execution initial value generation (201) of FIG. A function realized by the instruction sequence generated from the frequency of the function construction rate table is determined (501). In the instruction generation rate table, an instruction appearance frequency table for each instruction type for realizing the selected function is selected. An instruction type to be displayed is selected (502). The instruction to be generated is determined by the frequency of each instruction type in the instruction generation rate table for each instruction type (503) The test instruction detailed information table is determined by the frequency of the conflict width, and the operand is determined based on the resource data used as the target (504). At this time, the conflict width refers to the number of instructions executed from updating a certain resource to using it.

FIG. 6 shows an error instruction extraction process (20) shown in FIG.
It is a figure which shows the flowchart of 5). The initial value of the instruction number counter value N is set to 1 (601). An instruction sequence corresponding to the instruction counter value is selected from the beginning of the target test instruction sequence (60
2) Simulate and execute the instruction sequence to generate an expected value (603). Thereafter, the same command is executed on the target device (604), and the expected value obtained by the simulation and the execution result are compared and checked (605). If the result is correct, the instruction counter is incremented by +1 (606), and the same processing is repeated. If the result is incorrect, it is determined that the last instruction in the executed instruction sequence is an error instruction having a cause of failure, and the process ends.

According to the above-described processing, in the test instruction sequence having a complicated operation sequence in which the information (memory register) on the device under test after execution of the target test instruction sequence cannot identify the faulty part, the cause of the failure is determined. It is possible to specify the test instruction to have.

FIG. 7 shows the error cause analysis (206) of FIG.
6 is a flowchart showing the processing of FIG. Turn off the TLB function, execute the instruction group and generate an execution result value (701),
The generated execution result value is compared with the expected value (702).
If the results are equal, an error due to TLB failure is reported (715). If the results are not equal, the instruction code or operand data is executed by the In-cache to generate an execution result value (703), and the generated execution result value is compared with an expected value (704). If the results are equal, an error due to a bad memory access is reported (714). If the results are not equal, an instruction for pipeline adjustment (SYNC / NOP) is inserted before the error instruction to generate an execution result value (70
5) Compare the generated execution result value with the expected value (70)
6). If the results are equal, it is reported that the error is due to a pipeline failure (713). If the results are not equal, an execution result is generated by changing the register name used by the error target instruction (707), and the generated execution result value is compared with an expected value (708). If the results are not equal, report a data-dependent error (7
09). If the results are equal, a data variation test is performed on the error instruction alone (710), and if an NG is found, a data dependent type error is reported (709). If there is no NG, the error is reported as a physical failure type error (712). Finally, the instruction type,
The instruction type, function construction data, and the like are written in the error analysis result (716).

When the target device supports the degra mode, the same failure analysis can be realized by the function of the target device.

[0016]

According to the present invention, it is possible to reduce the number of steps of failure cause analysis by avoiding the occurrence of defects due to the same factor, and to improve the verification accuracy.
High-accuracy logic verification is possible in a short period of time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a test system for performing a test of a data processing device by a test method according to an embodiment of the present invention.

FIG. 2 is a flowchart showing processing of the entire test system.

FIG. 3 is an example of a data table format used by the test system.

FIG. 4 is a block diagram showing internal processing of an instruction generation rate adjusting unit.

FIG. 5 is a block diagram showing internal processing of a test instruction generation unit.

FIG. 6 is a flowchart illustrating internal processing of an error instruction extracting unit.

FIG. 7 is a flowchart illustrating an internal process of an error cause analysis unit.

[Description of Signs] 101 Test instruction generation unit 102 Instruction simulation unit 103 Test instruction group execution unit 104 Execution result comparison unit 105 Error instruction extraction unit 106 Error cause analysis unit 107 Instruction generation rate adjustment unit 108 Error message output unit 109 Test instruction Group detail information table 110 Test instruction group 111 Initial execution value 112 Error analysis result 113 Instruction generation rate table / function construction rate table 114 Expected value 115 Execution result value 116 Error message

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yutaka Kodama 1st Horiyamashita, Hadano-shi, Kanagawa Prefecture Within Nichi Information Technology Co., Ltd. Within technology

Claims (1)

[Claims] A step of generating a test instruction group based on predetermined test instruction group generation conditions by using random number data as input; a step of generating an expected value of an execution result of the test instruction group by simulation; Step 3 of causing the data processing device under test to execute the group, and Step 4 of comparing the expected value of the execution result created by the simulation with the value of the execution result in the data processing device
And a step 5 of analyzing an instruction and a function causing the mismatch when a mismatch occurs by comparison, and a step 5 of changing the test instruction group generation condition based on the analysis result. A test method for a data processing apparatus, comprising repeating a process from step 1 to step 5 a predetermined number of times according to a group generation condition.