JPH11195718A - Nonvolatile semiconductor memory and manufacture and drive method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform speeding up and preventing disturbance while taking high integration into consideration. SOLUTION: A device is provided with memory transistors M1-Mn for storing information, corresponding to the storage charge amount of a charge storage means (FG and charge trap or the like for instance) and first and second selective transistors (ST11-STn1 and ST12-STn2) connected between a source and a common potential line CSL and a drain and bit lines BL1-BLn for respective memory cells. In such a three-transistor cell constitution, the close arrangement of gate electrodes capable of eliminating the need for a dedicated area for the memory transistor is desirable. Also, it is preferable to changeover control a wire object corresponding to the request bit quality of data for instance, between the memory block of the 3 transistor cell constitution and the memory block provided with the plural memory transistors between the selective transistors, and to suppress area increase as much as possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having charge storage means such as a floating gate and electrically writing and erasing information in the charge storage means, and a method of manufacturing and driving the same. Specifically,
The present invention relates to a storage cell array in which nonvolatile semiconductor storage elements are arranged in parallel with a common line (bit line or source line), and a memory cell arrangement structure capable of preventing deterioration due to repeated writing / erasing and operating at high speed. , A transistor arrangement structure and a manufacturing method in a memory cell with a small area, and a drive for setting an inhibit voltage particularly at the time of writing and controlling a writing target according to the type of data between the memory cell having the above arrangement structure and a normal memory cell And how to.

[0002]

2. Description of the Related Art The cell system of a nonvolatile semiconductor memory device is as follows.
The NOR type can be roughly classified into a NAND type and a NAND type. In the NOR type, a so-called AND type, a DINOR type or the like in which bit lines and source lines are hierarchized, a source line separated type, and a source line between two cells in the row direction are used. Various proposals have been made, such as a common one.

Prior art 1 A so-called AND type array uses an FN (Fowler Nordheim) tunnel ring for both writing and erasing of information for low-voltage driving, so that a gate insulating film is hardly deteriorated with writing and erasing operations. In addition, the memory cell configuration can operate at a high speed to some extent.

FIG. 19 is a circuit diagram showing a part of a general AND type memory cell array. FIG. 20 shows FIG.
9 is a plan view of an AND memory cell array for a portion corresponding to FIG. 9, and FIG. 21 is a table showing general setting conditions of a bias voltage of the AND array. In this AND type memory cell array 100, as shown in FIG. 19, a predetermined number (four in FIG. 19, for simplicity) of memory transistors are connected in parallel between two block select transistors to form an AND column (memory block). Is configured. That is, in the first block, the bit line B1 and the source line S1
, A block selection transistor BT11 having a drain connected to the bit line B1 and a block selection transistor ST11 having a source connected to the common source line S1 are provided, and the source of the block selection transistor BT11 and the block selection transistor ST11 are provided. And memory transistors M11 to M14 are connected in parallel. Similarly, in the second block, the bit line B2
And a source line S2, a block selection transistor BT21 having a drain connected to the bit line B2 and a block selection transistor ST21 having a source connected to the source line S2 are provided.
The memory transistors M21 to M24 are connected in parallel between the source 21 and the drain of the block selection transistor ST21. In the memory cell array 100, many memory blocks having such a configuration are arranged in a matrix.

Each of the block select transistors BT11 and BT21 on the bit line side is connected to a bit line block select signal line W.
B, and the block selection transistors ST11 and ST21 on the source line side are controlled by the source line block selection signal line WS.

In the plan view shown in FIG. 20, an active region of each memory block is formed by a region surrounded by an element isolation region 101 such as LOCOS, as indicated by a bold line in the drawing. At one end of the active region, an impurity diffusion region 102 serving as a drain of the block select transistors BT11 and BT21 is formed on the impurity diffusion region 102 and a bit line B1 or B
And a bit contact BC for connecting to the impurity diffusion region 10 serving as a source of the block select transistors ST11 and ST21.
3 is provided with a source contact SC for connecting this to an upper layer source line S1 or S2. A drain impurity diffusion region 104 also serving as a source of the block selection transistors BT11 and BT21 and a source impurity diffusion region 105 serving also as a drain of the block selection transistors ST11 and ST21 extend in the column direction in the active region and are parallel to each other. The memory transistors are provided in parallel between the impurity diffusion regions 104 and 105.

The AND type memory cell array 1 having such a configuration
00, for example, when writing is performed on the memory transistor M11, as shown in FIG. 21, a positive voltage VM (for example, V _PP /
2: +10 V) to ground the source line block selection signal line WS. In addition, the selected bit line B1 is grounded, and all other bit lines (non-selected bit lines B2,...) Are biased to a positive voltage VM (for example, V _PP / 2: +10 V).
As a result, the block selection transistors BT11 and BT21 connected to the bit lines B1 and B2 are turned on, and the source line S
1, block selection transistors ST11 connected to S2,
ST21 remains off. Therefore, the potential of the selected bit line B1 is applied to the drains of the memory transistors M11 to M14 of the selected block, and is kept at 0 V together with the substrate, while the drains of the memory transistors M21 to M24 of the unselected block are connected to the unselected bit lines. It is held at a predetermined potential Vch (VM- (gate threshold voltage of the block selection transistor BT21)) based on the potential.

After all the word lines W1 to W4 are set to the same potential as the substrate (for example, 0V), a positive high voltage V _PP (for example, + 20V) is applied only to the selected word line W1. Thereby, in the selected block, the selected memory transistor M1
Only 1 is turned on to form a channel, and the channel, the drain and the source in the floating state are all 0.
The voltage is held at V and an electric field due to the gate voltage V _PP is applied to the gate insulating film, and electrons are injected into the floating gate on the gate insulating film from the substrate side by a FN (Fowler-Nordheim) tunnel phenomenon. In the unselected memory transistors M12 to M14 in the same block, no channel is formed and the source and the drain are 0 V together with the substrate. However, since the gate voltage is 0 V, no electric field is applied to the gate insulating film and electrons are injected. Not done. On the other hand, also in the unselected block, the unselected memory transistor M21 connected to the selected word line W1 is turned on, and the other unselected memory transistors M22 to M24 remain off, as in the above-described selected block. However, in the unselected block, the channel, source, and drain of the unselected memory transistor M21 in the on state, and the sources and drains of the other unselected memory transistors M22 to M24 in the off state are close to the unselected bit line voltage. Since the voltage is held at Vch, the electric field applied to the gate insulating film in all the memory transistors is not strong enough to cause electron injection, so that electrons are hardly injected into the floating gate.

As described above, in the writing method under the condition shown in FIG. 21, the voltage of V _PP is applied to the gate electrode of the selected storage element, and the source region is separated from the source region of the adjacent block. Bit line potential (0 V) applied to the channel, source and drain from the drain side
At the same voltage, and no current flows between the source and the drain. For this reason, the FN tunnel phenomenon can be used for charge injection in writing, and as a result, even if writing and erasing are repeated, deterioration of the gate insulating film is small. In the case of a non-selected storage element, an electric field is not applied to the gate insulating film in the selected block, and a high voltage V _PP is applied to all the source and drain and the gate electrode in the non-selected block. Since all the channels are biased to the positive voltage Vch, the electric field applied to the gate insulating film is relaxed, so that the tunnel phenomenon hardly occurs, and the writing in the block is prohibited.

On the other hand, in the case of erasing, as shown in FIG. 21, a negative high voltage (-V _PP ) is applied to the selected word line W1 with all of the select transistors ST11 to ST21 turned off and the substrate grounded. Therefore, electrons are emitted from the floating gate of the memory transistor M11 in the selected row to the substrate. At the time of reading, as shown in FIG. 21, the bit line and source line block selection signal lines WB and WS are biased to the power supply voltage V _CC (for example, 3 V), and the selected bit line B1 is set to a positive voltage VR lower than V _CC. (For example, 1.5 V). As a result, the current flowing through the selected bit line B1 is read according to the difference in the gate threshold voltage Vth of the selected memory transistor M11.

Prior Art 2 FIG. 22 is a diagram showing a basic configuration of an isolated source NOR type memory cell array together with a bias voltage setting condition at the time of writing. This isolated source NOR type memory cell array 110 does not have a select transistor unlike the AND type described above because the bit lines and the source lines are not hierarchized. Therefore, the memory transistor is simply connected in parallel between the bit line and the source line separated in the row direction, and the gate electrode is commonly connected in the row direction by the word line. In FIG. 22, the selected cell to which information is to be written, which is connected to the selected bit line BLsel. And the selected word line WLsel. The non-selected cells connected to the bit line BLunsel. Are arranged in the same column as the cell A and the selected cell S, connected to the selected bit line BLsel., And the unselected word line WLunsel.
Is a non-selected cell connected to B, a non-selected word line WLunse
l and other unselected cells connected to the unselected bit line BLunsel.

In the isolated source line NOR type memory cell array having such a configuration, the source line S
L is open (floating state), the substrate and the selected bit line BLsel. Are both 0 V, the unselected bit line BLunsel. Is at the intermediate potential VM (for example, about 8 V), and the unselected word line W is
Lunsel. Is set to an intermediate potential VM ′ (for example, about 10 V), and a program voltage V _PP which is a positive high voltage is applied to the selected word line WLsel. As a result, a high voltage of approximately V _PP is applied to the gate insulating film of the selected cell S, and electrons are injected from the substrate side into the charge storage means (floating gate in the FG type) which is insulated and separated from the surroundings in the gate insulating film. Then, writing is performed. At this time, unselected cells A to C
With respect to the above, the applied voltage to the gate insulating film is sufficiently lower than that of the selected cell S, so that erroneous writing and erasing at the time of writing are prevented.

In this writing method, the bias voltage at the time of writing to each cell is equal to the AND voltage shown in the prior art 1 described above.
This is almost the same as the voltage setting example for the mold, the source line is open, and the charge injection is performed by FN tunneling as in the prior art 1, thereby preventing the deterioration of the gate insulating film at the time of writing and increasing the speed. . Further, the reading and erasing operations can be performed in the same manner as in the prior art 1.

Prior art 3 In prior arts 1 and 2, writing was performed by injecting charges (electrons) into the charge storage means (floating gate). Conversely, the charge stored in the charge storage means was transferred to the substrate side. There is a writing method to pull out.

FIG. 23 is a diagram showing a basic configuration of an isolated source line NOR type memory cell array together with a bias voltage setting condition at the time of writing in this writing method. The definition of each cell is the same as in FIG. This writing method can also be applied to an AND-type memory cell array, and the writing conditions in this case are shown in parentheses below. In this writing method, the source line is opened (or AN
The source line SL is set to a floating state by turning off the D-type source selection transistor, and the substrate and the unselected bit line BLunsel. (Or the drain impurity diffusion region of the AND-type unselected block, that is, the sub-bit line) are both set to 0V. , The selected bit line BLsel. (Or the sub-bit line of the AND-type selected block) to the intermediate potential VM (for example, the power supply voltage V _CC :
3.3 V), and the unselected word line WLunsel. Is set to the intermediate potential VM '(for example, the power supply voltage V _CC : about 3.3 V). With the bit line potentials transmitted to the drains of the memory transistors, a program voltage (-V _PP ), which is a high negative voltage, is applied to the selected word line WLsel. As a result, approximately (V _PP +
A high voltage (VM) is applied, and electrons stored in the charge storage means (floating gate in the case of the FG type), which is insulated and separated from the surroundings in the gate insulating film, are drawn out to the substrate side, and writing is performed. On the other hand, in all of the non-selected cells A to C, the voltage applied to the gate insulating film is sufficiently lower than that in the selected cell S, so that erroneous writing and erroneous erasing during writing are prevented.

Prior Art 4 FIG. 24 shows a case where a source line is shared between two cells in a row direction.
FIG. 4 is a diagram showing a basic configuration of an R-type (hereinafter, referred to as a shared source line NOR type) memory cell array together with bias voltage setting conditions at the time of writing. The definition of each cell is the same as in FIG. This writing method is
With the shared source line SL, unselected bit line BLunsel., Unselected word line WLunsel., And substrate all set to 0 V, the selected bit line BLsel. Has an intermediate potential VM and the selected word line WLsel. _Apply program voltage V _PP . As a result, electrons accelerated by the electric field due to the source-drain voltage of the selected cell S become channel hot electrons at the drain end and are attracted to the voltage applied to the gate electrode. (Floating gate), and writing is performed. On the other hand, in the non-selected cells A and C, no voltage is applied between the source and the drain, and in the non-selected cell B, no gate voltage is applied. Erasure is to be prevented.

Prior Art 5 FIG. 25 is a diagram showing a part of a NAND type memory cell array together with bias voltage setting conditions at the time of writing. The definition of each cell is the same as in FIG. This NAND type memory cell array 130 has a configuration in which memory transistors are connected not in parallel but in series in each block in FIG. In FIG. 25, the selected cell S
And unselected cells B and unselected cells A and C belong to the same block.

In the NAND memory cell array 130 having such a configuration, at the time of writing, a positive intermediate voltage (for example, 7 to 10 V) is applied to the bit line block selection signal line with the substrate and the source line SL grounded, Ground the line block selection signal line. As a result, with respect to the transistor row of each block, the drain side is connected to the bit line, and the source side is disconnected from the source line (0 V), and becomes a floating state. In addition, the selected bit line BLsel. Is grounded, and the unselected bit line BLunsel. Is biased to a positive intermediate voltage VM (for example, about 7 to 10 V). In this state, the positive intermediate voltage VM ′ (for example, about 10 V) is applied to the non-selected word line WLunsel.
A positive high voltage V _PP (for example, +20 V) is applied to l. As a result, a high voltage of approximately V _PP is applied to the gate insulating film of the selected cell S, electrons are injected from the substrate side into the charge storage means (floating gate) insulated and separated from the surroundings in the gate insulating film, and writing is performed. Done. At this time, for the non-selected cells A to C, the intermediate voltage VM ′ or the program voltage V _{PP is} applied to the gate insulating film from the intermediate voltage VM.
Since only a voltage obtained by subtracting the above is applied, erroneous writing and erroneous erasing during writing are prevented.

On the other hand, in the case of reading, as shown in FIG. 25B, with the substrate and the source line SL grounded, a positive voltage (for example, , Power supply voltage V _CC )
Is applied. Thereby, with respect to the transistor row of each block, the drain side is connected to the bit line, and the source side is connected to the source line (0 V). In addition, unselected bit lines B
Lunsel. Is grounded, and a voltage between the threshold value of the cell in the write state and the threshold value of the cell in the erase state, for example, 0 V, is applied to the selected word line WLsel., And a slightly higher positive voltage (V) is applied to the unselected word line WLunsel. 4.5V when _CC + α, V _CC is 3.3V
Degree). In this state, the selected bit line BLsel.
, A positive read voltage VR (for example, about 1 to 2 V) is applied. Thus, the transistor of the non-selected cell B is turned on and functions as a pass transistor irrespective of the write state, but the on / off state of the transistor of the selected cell S is determined according to the write state. Therefore, the write state of the selected cell S can be read by detecting the presence or absence of the current flowing through the bit line. On the other hand, since no voltage is applied between the source and the drain of the transistor row of the unselected block, no reading is performed.

The above description has been made on the typical driving method of the conventional nonvolatile semiconductor memory device with a focus on the cell structure and writing.
There are an OR type, a virtual ground type and the like, and a writing method includes hot carrier injection by avalanche breakdown, and various cell structures and writing methods have been proposed.

[0021]

In the conventional nonvolatile semiconductor memory device described above, at the time of writing (or reading), a non-selected memory transistor is brought into a weak writing state by a so-called gate disturb (or drain disturb). The erased state becomes weaker or weaker, and writing stress or the like increases during repeated writing and erasing. For example, at the time of writing, FIG.
2 to 25, disturbs due to erroneous writing of unselected cell B in prior arts 1 and 2, disturb due to erroneous erasing of unselected cell C in prior art 3, and non-disturbed in prior art 4 Disturb due to erroneous erasure of the selected cell B is likely to be particularly problematic.
Further, at the time of reading, there is a high possibility that disturb due to erroneous writing of the non-selected cell C in the related art 5 is particularly problematic.

The fact that the unselected cells are disturbed becomes a more serious problem in the case of a multi-valued memory in which it is necessary to narrow the distribution width of the threshold value of each cell. Also,
Even when the cell is miniaturized for realizing a large-capacity memory and the voltage is reduced due to this or from the viewpoint of reducing power consumption, the disturb resistance of the non-selected cells is reduced. It becomes even more important in securing the quality. In addition, the case of multi-value conversion is even more so.

Further, in the above-mentioned conventional nonvolatile semiconductor memory device of the various cell systems, the following two restrictions are caused by the write disturbance.

The first constraint relates to the size of a block which is a rewrite unit. For example, FIG.
In the block shown in FIG. 9, the size of a memory cell row (page) connected to one word line is usually 512 bytes (B), that is, 4096 bits (b). One block is usually composed of about 16 pages, and in this case, the block size is 8 kB. However, a block size suitable for an external storage device is generally 512 B to several kB, and 8 kB is a little too large. So 1
Although it is conceivable to reduce the number of bytes of the page to, for example, 64 B, the writing time per byte becomes eight times as long as the original, which hinders high-speed performance. Further, for the purpose of substantially reducing the block size, it is conceivable to perform an erasing operation by dividing the erasing operation within a block. May be subjected to write stress, which may be accumulated and lead to malfunction. For example, in a flash memory, an erasing operation is generally performed in a block even if the rewriting unit is a block, and the program operation itself is performed in page units. In this case, since the erase operation is performed collectively on the blocks before the write operation, if the page write is performed sequentially from the side closer to the bit line in the example of FIG. The write stress applied to the near page is reset after being accumulated for at most about 15 write operations. On the other hand, when the erasing operation is performed in a divided manner in a block, while a certain page is rewritten up to 1 × 10 ⁶ times, for example,
If there is a page that is never written or erased,
This page is subjected to a stress corresponding to 1 × 10 ⁶ write operations, and as a result, there is a high possibility that the logic of the original stored data is inverted.

A second limitation is that the writing speed cannot be increased with the conventional cell structure. For example, in the NOR type shown in FIG. 23, the writing speed is improved by increasing the drain voltage VM of the selected cell S. In this case, the potential of the unselected word line must be increased to prevent the erroneous writing of the unselected cell B. There is. However, when the non-selected word line voltage VM is increased, the possibility that the non-selected cells C are erroneously erased is increased. In the NOR type shown in FIG. 22, the writing speed is improved by increasing the selected word line voltage V _PP , but in this case, the intermediate voltage applied to the drain of the non-selected cell A on the same page is prevented in order to prevent writing. The voltage VM also needs to be increased. However, when the intermediate voltage VM is increased, it is necessary to increase the voltage of the unselected word line in order to prevent the erroneous erasure of the unselected cell C. As a result, the possibility that the unselected cell B is erroneously written increases. . That is, there is a trade-off between prevention of disturbance of a non-selected page and improvement of the writing speed. This write disturb and the accompanying restrictions on the block size and the write speed are issues common to almost all cell systems, such as not only the AND type and the NOR type, but also the NAND type.

Further, especially in the case of the AND type or the NAND type, there are some structural specific problems as described below. First, in the AND type or the NAND type, since an impurity diffusion layer buried under an oxide film is usually used as a source / drain wiring in a block, a parasitic resistance is added to a source and a drain of each memory transistor. And capacity are added, which hinders speeding up. When the number of memory transistors in a block is increased for higher density, the length of the source / drain wiring becomes longer, which makes it difficult to increase the speed. Since the reading in these cell systems is performed through the impurity diffusion layer, the resistance is easily affected by the fluctuation of the resistance of the impurity diffusion layer. In particular, in the case of the NAND type, the resistance changes in accordance with the write state of the non-selected cell. From that
High-precision reading cannot be performed.

Second, in the AND type, since the channel width of the memory transistor can be as large as that of the gate electrode, it is necessary to increase the width of the word line in order to increase the driving capability. As is apparent, as the width of the word line is increased, the block becomes larger in the column direction. Usually, the minimum line width of the process is used as the width of the word line. However, the driving capability of the memory transistor decreases and the wiring resistance of the word line tends to increase as the capability of the process increases.

Third, in the AND type, since it is necessary to provide the source / drain wiring separately from the adjacent column, an area for the wiring is required for each block, and the size of the memory cell is reduced. However, the area occupied by the entire block is large, and the degree of integration does not increase.

The disturb problem described above, the accompanying restriction on high-speed operation, and the structural problems such as the AND type are not limited to the FG type of the gate structure of the memory transistor. Discrete nonvolatile memories such as MNOS (Metal-Nitride-Oxide Semic
onductor) type, MONOS (Metal-Oxide-Nitride-Oxide
Such problems are common even in the case of a (Semiconductor) type.

The present invention has been made in view of such circumstances, and has as its object to provide a non-volatile semiconductor memory device with improved speed and improved disturbance while considering high integration, and a method of manufacturing and writing the same. .

[0031]

In order to solve the above-mentioned problems of the prior art and to achieve the above object, a nonvolatile semiconductor memory device of the present invention comprises a charge storage means (for example, a floating gate or a discretized memory). And a memory transistor for storing information in accordance with the amount of stored charge in the memory cell, wherein one of the source and the drain of the memory transistor is provided for each of the memory cells. A first select transistor connected between the memory transistor and the bit line, and a second select transistor connected between the other of the source or drain of the memory transistor and the common potential line.

In such a nonvolatile semiconductor memory device, the connection of each memory transistor to the bit line or the source line can be controlled for each cell by the two selection transistors. The source and drain of each cell belonging to the non-selected page can be separated from the bit line and the source line, and there is no need to apply an inhibit voltage to the gate thereof. There is no read disturb. Therefore, the number of pages in the rewrite block is not limited by the write disturb or the like, and the number of pages in the block can be freely set. Also,
Even if the gate voltage (program voltage) or the drain voltage (read voltage) is increased in order to increase the writing or reading speed, there is no effect on the non-selected cells, so that the speed can be easily increased.

In another nonvolatile semiconductor memory device of the present invention, a first nonvolatile semiconductor memory device includes a first semiconductor device connected in series between a bit line and a source line.
The memory cell has three transistors, ie, the select transistor, the memory transistor, and the second select transistor, in the same manner as the nonvolatile semiconductor memory device. In particular, in the present nonvolatile semiconductor memory device, a first impurity region connected to a bit line is provided in a memory cell;
Second impurity regions connected to the source lines are formed on the surface side in the semiconductor layer so as to be separated from each other. Then, on the semiconductor layer of the first and second impurity regions, the first selection transistor, in order from a side closer to the bit line,
The gate electrodes of the memory transistor and the second transistor are arranged so as to be insulated from each other and insulated from the semiconductor layer by a gate insulating film.

Preferably, the first insulating film below the gate electrode of the memory transistor is provided between a side surface of the gate electrode and a side surface of each of the gate electrodes of the first and second select transistors opposed thereto. By extending and also serving as an inter-gate electrode insulating film, the inter-gate insulating isolation structure is simplified. Preferably, the wiring width direction of the gate electrode of the memory transistor coincides with the channel length direction of the memory transistor, so that the effective gate width of the memory transistor is not restricted by the wiring width. In addition, since both side portions of the gate electrode in the wiring width direction extend on the offset insulating film, the wiring resistance is suppressed low.

In the case where the nonvolatile semiconductor memory device is of the FG type, preferably, among the side surfaces of the gate electrodes of the first and second selection transistors, the side surfaces facing the first and second impurity regions are preferably provided. A first sidewall insulating film formed respectively; a second sidewall insulating film formed on both sides of the gate electrode of the memory transistor in the channel length direction on the offset insulating film; A self-aligned contact hole having a second sidewall insulating film on the inner wall and opening on each of the first and second impurity regions; and a self-aligned contact hole buried in the self-aligned contact hole on the first impurity region. And a common potential wiring layer buried in a self-aligned contact hole on the second impurity region. For example, a source line is formed by this common potential wiring layer,
It is preferable that a bit line be formed by an upper wiring connected to the connection plug. The connection plug and the common potential wiring layer are made of conductive silicon whose surface is covered with a high-melting-point metal silicide, so that the resistance is reduced.

In the above-described nonvolatile semiconductor memory device of the present invention, two selection transistors for controlling connection between a memory transistor and a bit line or a common potential line (generally, a source line) are provided for each memory cell. When writing information to the memory cell, for example, the source of the memory transistor can be separated from the source line, and a channel can be formed with the source and the drain kept at the same potential. Writing with current is possible. In addition, at the time of this writing, it is possible to freely control whether another memory transistor connected in the row direction and the column direction is separated from the selected bit line or the like, or whether a voltage at which the electric field applied to the gate insulating film becomes 0 is applied to the unselected bit line. Can be done. For example, in a configuration in which a selection signal line for controlling a selection transistor is shared between cells in a row direction similarly to a word line, conventionally, when a write inhibit voltage is set to a bit line of an unselected cell connected to a selected word line. The voltage value cannot be set freely, with the restriction that other unselected cells connected to the same unselected bit line in the column direction are not erased. On the other hand, in the present invention, it is possible to control to disconnect all the other unselected cells connected in the column direction from the unselected bit lines, and there is no restriction on the write inhibit voltage value.

In the cell structure having such a structure, in a structure in which the gate electrode of the memory transistor is close to the gate electrode of the selection transistor, the source region and the drain region are shared by three transistors in the cell. The area occupied by memory transistors is reduced. In this three-transistor configuration, the source / drain wiring layer conventionally connecting the memory transistors in the block is not required, and not only does the area thereof not increase, but also the additional capacity between the bit line or the source line, The cell configuration has a small parasitic component such as an additional resistance.

On the other hand, in the nonvolatile semiconductor memory device of the present invention, a configuration in which these three-transistor memory cells are included in a part of a memory cell array can be adopted. That is, in this case, a first memory block configured by arranging a plurality of memory cells each including the memory transistor and the first and second selection transistors, and a first selection transistor connected to the bit line And a second memory block configured by arranging a plurality of unit blocks each including a plurality of memory transistors connected between the second selection transistors connected to the common potential line.

When such two types of memory blocks are provided, high reliability data (first data) to be effectively prevented from being erroneously written at the time of writing is stored in the first memory block having a three-transistor cell configuration. Writing the second
Normal data (second data) having a higher allowable frequency of erroneous writing than the high reliability data in the memory block
Can be written. In the three-transistor cell configuration, the number of transistors per bit is generally larger than that of the conventional second memory cell block, which is expected to cause an effective cell area increase.
When two types of blocks to be written are provided in accordance with the type of data, the occupation area of the entire memory cell array can be reduced without impairing operation reliability.

According to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, the first impurity region formed on the surface side in the semiconductor layer and connected to the bit line and the second impurity region connected to the source line are formed.
A first gate electrode for the first select transistor and a second gate electrode for the second select transistor are separated from each other on the semiconductor layer portion between the impurity regions of And a second gate insulating film interposed between the first and second gate electrodes, between the first and second gate electrodes, between the first and second gate electrodes, and between sidewalls of the first and second gate electrodes. Then, a third gate electrode for the memory transistor is formed.

In the FG type nonvolatile semiconductor memory device, preferably, at the same time as the formation of the first and second gate electrodes, an offset insulating film is previously formed on each of the gate electrodes. Then, when forming the third electrode,
Forming a first conductive film on the offset insulating film and the second gate insulating film; patterning the first conductive film in a stripe shape substantially parallel to a series connection direction of the transistors; A dielectric film and a second conductive film are sequentially formed on the first conductive film. Patterned in orthogonal stripes,
A floating gate made of the first conductive film and divided for each cell and a word line made of the second conductive film and laminated on the dielectric film are formed simultaneously.

Preferably, after the formation of the third electrode, a sidewall insulating film is formed on each side surface of the third gate electrode and the first and second gate electrodes. Simultaneously with the formation, a conductive material is buried in the self-aligned contact holes respectively opened on the first impurity region and the second impurity region,
In contact with the connection plug made of conductive material on the impurity region,
Intersecting bit lines are formed on the common potential wiring layer made of a conductive material on the second impurity region via an interlayer insulating layer.

In the method of manufacturing a nonvolatile semiconductor memory device according to the present invention described above, first, the insulation on the side surfaces between the gate electrodes is formed simultaneously with the gate insulating film through which electrons are tunneled. Insulation in the vertical direction of the gate electrode of the transistor is achieved by the offset insulating film formed simultaneously with the gate processing of the select transistor. By forming sidewalls on the outer surfaces of these gate electrodes, bit contact holes and source contact holes are formed in a self-aligned manner. By embedding a conductive material in such a self-aligned contact hole, the source wiring layer can be formed of the conductive material and the resistance can be easily reduced.

In the method for driving a nonvolatile semiconductor memory device according to the present invention, a memory transistor is connected in series between a first selection transistor connected to a bit line and a second selection transistor connected to a common potential line. A method of driving a nonvolatile semiconductor memory device having a memory cell formed therein, wherein at least one of the first and second select transistors is commonly driven between memory cells in a row direction to write and read information. Read or erase. Preferably, at the time of writing, the unselected bit lines are
A voltage that is substantially the same as the voltage applied to the selected word line among the word lines in which the control electrodes of the memory transistors are commonly connected in the row direction is applied. As a result, among the unselected memory transistors connected to the bit line, a memory cell connected to the selected word line and applying a high voltage to the gate hardly receives an electric field on the gate insulating film. More preferably, when the first and second memory blocks are provided as described above, the first data (for example, the high-reliability data) is stored in the first memory block when writing.
And writes the second data (for example, the normal data) in the second memory block. Note that in the nonvolatile semiconductor memory device of the present invention,
By turning off the selection transistor in the non-selected row, the memory transistor is excessively erased and reading can be performed even when the gate threshold voltage becomes negative.

[0045]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A memory transistor in a nonvolatile semiconductor memory device according to the present invention has a charge storage means inside a semiconductor substrate or a laminated film between a semiconductor layer supported on the substrate and a gate electrode (control electrode). . Here, the “semiconductor layer” is a well formed on the front surface side in the semiconductor substrate, an epitaxial growth layer formed on the semiconductor substrate surface, or S
There are various forms such as a semiconductor layer having an OI (Silicon On Insulator) type insulating structure. When the semiconductor layer has an SOI insulating structure, the substrate is not limited to a semiconductor substrate. The "charge storage means" is formed in a gate insulating film including at least a tunnel insulating film in a lowermost layer, and charges electric charges between the substrate side according to a voltage applied to a gate electrode on the gate insulating film. A charge holding medium that exchanges and holds charges. The charge storage means includes, for example, a conductive layer such as FG,
It may be discretized in a plane. Here, “planar discrete charge storage means” means ONO (Oxide-Nit
a carrier trap formed in the bulk of a nitride film such as a ride-Oxide film or a NO (Nitride-Oxide) film or in the vicinity of an interface between an oxide film and a nitride film; A finely divided floating gate made of conductive polysilicon or the like and divided into fine dots.

FIGS. 2 to 4 are element cross-sectional views showing examples of the structure of a memory transistor. In FIG. 2 to FIG.
Semiconductor substrate such as a silicon wafer having a conductivity type of p-type or p-type or the semiconductor layer (hereinafter, referred to as a substrate), 1
a and 1b show a source region and a drain region of the memory transistor. The source region 1a and the drain region 1b are regions having high conductivity formed by introducing an impurity of a conductivity type opposite to that of the substrate 1 at a high concentration, and have various forms. Normally, an LDD (Lightly D) is placed on the substrate surface on the side surface opposite to the source region 1a and the drain region 1b.
In many cases, a low-concentration impurity region called “oped drain” is provided. The gate electrode 2 of the memory transistor is stacked on the substrate region sandwiched between the source region 1a and the drain region 1b via the stacked films 3a to 3c. The gate electrode 2 is generally made of doped polysilicon, which is made conductive by introducing p-type or n-type impurities at a high concentration.
Si) or a laminated film of doped poly-Si and high melting point metal silicide.

In the FG type memory transistor shown in FIG. 2, the laminated film 3a is composed of a gate insulating film 4, a floating gate 5, and an intermediate insulating film 6 in order from the lowest layer. The gate insulating film 4 is usually made of a thermal oxide film, and is optionally subjected to a nitriding treatment to provide a nitrided oxide layer on the surface of the thermal oxide film. The floating gate 5 is, for example, a doped po
The intermediate insulating film 6 is made of, for example, ONO (O
xide-Nitride-Oxide) film.

In the MONOS type memory transistor shown in FIG. 3, the laminated film 3b is composed of a gate insulating film 4, a nitride film 7, a top oxide film 8 and an insulating film in this order from the lowest layer. The intermediate nitride film 7 is made of, for example, silicon nitride. This nitride film 7 is a layer formed for introducing a charge storage means (carrier trap), and can be replaced by another insulating film, for example, an oxynitride film. Of the carrier traps introduced by the formation of the nitride film 7, those functioning as charge storage means are mainly formed near the bulk trap of the nitride film 7 and in the vicinity of the interface between the nitride film 7 and the upper top oxide film 8. It is a deep carrier trap. The top oxide film 8 is made of, for example, thermal silicon oxide, and is provided mainly for the purpose of preventing hole injection from the gate electrode 2 side.

In the MNOS type memory transistor shown in FIG. 4, the laminated film 3c is composed of a two-layer insulating film of a lower gate insulating film 4 and an upper nitride film 9.
The nitride film 9 is made of, for example, silicon nitride and is a layer formed for introducing a carrier trap as in the case of FIG. 3, and the nitride film 9 is formed relatively thick to prevent hole injection.

Hereinafter, embodiments of the cell configuration, layout structure, memory cell array configuration, and driving method of the nonvolatile semiconductor memory device of the present invention will be described in detail with reference to the drawings.

First Embodiment FIG. 1 shows an example in which a memory cell row (page) connected to a single word line is used as a rewriting unit, and shows a main part of a memory array showing a cell configuration according to an embodiment of the present invention. It is a circuit diagram. The rewriting unit in this example is configured by arranging 4096 memory cells in a row direction in a predetermined number, for example, 512 bytes.

In this memory cell array, each memory cell includes a first selection transistor having a drain connected to a bit line, a second selection transistor having a source connected to a source line, and a series connection between the two selection transistors. It is composed of a single connected memory transistor. That is, the memory cell configuration of the present invention is equivalent to the configuration in which a single memory transistor is used in each memory block of the conventional AND type memory cell (or conventional NAND type memory cell array) shown in FIG. However, in the present example, the conventional “bit line block selection signal line” is replaced with “bit line selection signal line” and the “source line block selection signal line” is replaced with “source The names of “line selection signal lines”, “bit line block selection transistors” are replaced with “bit line selection transistors”, and “source line block selection transistors” are replaced with “source line selection transistors”.

More specifically, as shown in FIG. 1, each memory cell has a bit line selection transistor having a drain connected to a bit line and a source line selection transistor having a source connected to a common source line (common potential line). It comprises a transistor and a single memory transistor connected between both select transistors. That is, in the first memory cell, between the bit line BL1 and the common source line CSL, a bit line selection transistor ST11 whose drain is connected to the bit line BL1 and a source line selection transistor whose source is connected to the common source line CSL ST12 is provided, and the memory transistor M1 is connected between the source of the bit line selection transistor ST11 and the drain of the source line selection transistor ST12. Similarly, in the second memory cell, between the bit line BL2 and the common source line CSL, the bit line selection transistor ST21 whose drain is connected to the bit line BL2 and the source is the common source line CS
A source line selection transistor ST22 connected to L is provided, and a memory transistor M2 is connected between the source of the drain selection transistor ST21 and the drain of the source line selection transistor ST22. The memory cells having such a configuration are repeatedly arranged, and in the last n-th memory cell, the bit line BLn and the common source line C
SL, a bit line select transistor STn1 whose drain is connected to the bit line BLn, and a source line select transistor S whose source is connected to the common source line CSL.
Tn2 and a bit line select transistor STn
1 and the drain of the source line selection transistor STn2, the memory transistor Mn is connected.

Each bit line select transistor ST11-S
Tn1 is controlled by a bit line selection signal line SG1,
Each of the source line selection transistors ST12 to STn2 is controlled by a source line selection signal line SG2. FIG.
Although the block 1 has only one page in the block 1, the present invention is not limited to this, and a plurality of pages in which cells having such a two-selection transistor and one memory transistor configuration can be provided.

Next, an embodiment of a method for driving a nonvolatile semiconductor memory device according to the present invention will be described by taking writing as an example. FIG. 5 is a diagram and a table showing locations of application of bias voltages and setting conditions in the writing method according to the present embodiment. In addition,
The procedure for applying the voltage is not limited to the following example.

In the write method according to the present embodiment, for example, when writing is performed on a cell connected to the bit line BL1, 0 V is applied to the selected bit line BL1 and the unselected bit line BL
, BLn, the intermediate voltage VM or the power supply voltage V _{DD is applied to} the bit line selection signal line SG1, and the intermediate voltage VM or the power supply voltage V _DD is applied to the source line selection signal line SG2 and the substrate. Note that the common source line CSL is held at 0V. When the applied voltage of the unselected bit line is VM, the applied voltage of the bit line select signal line SG1 is also set to VM, and when the applied voltage of the unselected bit line is V _DD , the applied voltage of the bit line select signal line SG1 is also set. V _DD . In this state, a positive high voltage (program voltage V _PP ) is applied to the word line WL. Under the above-described bias setting condition, the bit line selection transistor of the selected cell is always on, so that the bit line potential (0 V) is transmitted to the channel of the selected memory transistor. As a result, the high voltage V is applied to the gate insulating film of the selected memory transistor. _PP is applied, and electrons are tunnel-injected into the charge storage means from the entire surface of the channel to perform writing.

On the other hand, in the non-selected cell, the source line selection transistor is turned off and the bit line selection transistor is also turned off immediately, so that the channel of the non-selected memory transistor is in a floating state and is automatically boosted, and its channel potential is increased. Saturates at an intermediate voltage value determined by the coupling ratio between the program voltage V _PP and the floating gate or the like. As a result, an inhibit voltage sufficiently smaller than V _PP is set for the gate insulating film of the non-selected memory transistor, thereby prohibiting writing. The application of the word line voltage is performed after a predetermined time delay from the setting of the other bias voltage, or when the other bias voltage is not set, the voltage is first set to a low voltage, and then the program voltage is set after setting the other bias voltage. Increase the voltage to V _PP . This is because if the word line potential is rapidly increased from the beginning to the program voltage V _PP , a channel is formed in a non-selected memory transistor, or erroneous writing is performed on the non-selected memory transistor before the channel potential rises thereafter. This is to prevent this.

As described above, the nonvolatile memory according to the present embodiment has two select transistors for controlling the connection of the memory transistor to the bit line or the common source line for each memory cell. With this cell configuration, in the write method according to the present embodiment, for example, even if the memory cell row in the configuration of FIG. 1 has an array configuration in which the same bit line is connected in the column direction, all the memory transistors of the non-selected cells are bit lines or It is possible to control disconnection from the common source line. For this reason, the write disturbance to the non-selected row, which has conventionally been a problem, is completely eliminated. Further, in this cell configuration / writing method, it is not necessary to consider write disturbance to an unselected row, so that the number of pages in a rewrite unit (block) can be set arbitrarily.
Further, high-speed operation is enabled by increasing the program voltage V _PP . Also in the read operation, the read disturb for the unselected row is eliminated, and even if the drain applied voltage (read voltage) at the time of reading is increased to achieve the high-speed operation, the read disturb resistance of the unselected cells connected to the same bit line is maintained. Does not worsen. In the erasing operation, for example, a positive high voltage is applied to the substrate or a negative high voltage is applied to the word line. When a negative high voltage is applied to the latter word line, the drain can be selectively set to 0 V or a positive inhibit voltage can be selectively set in the same manner as in the case of the above-described writing, and therefore, for each cell or bit string. Can be erased.

Second Embodiment This embodiment is different from the first embodiment in a writing method when the logic of writing / erasing is inverted (that is, the erasing method in the first embodiment). In addition,
The cell configuration is the same as in the first embodiment, and FIG. 1 can be applied to this example as it is. FIG. 6 is a diagram and a table showing locations of application of bias voltages and setting conditions in the writing method according to the present embodiment. The procedure for applying the voltage is not limited to the following example.

In the write method according to the present embodiment, for example, when writing is performed on the cell connected to the bit line BL1, for example, 選 択 of the write voltage is applied to the selected bit line BL1.
, BLn of the non-selected bit lines BL2,.
V, the power supply voltage V _PP ,
0 V is applied to the source line selection signal line SG2 and the substrate. Note that the common source line CSL is held at 0V. In this state, a negative voltage, for example, VM
And a voltage (-VM) having the opposite polarity and the same absolute value. Under the above-described bias setting condition, the bit line selection transistor of the selected cell is immediately turned on.
Voltage (VM-Vth) dropped by the gate threshold voltage of GI
Is transmitted to the drain of the selected memory transistor. As a result, a high voltage (2VM-Vth) is applied to the gate insulating film of the selected memory transistor, and the electrons stored in the charge storage means are drawn out to the drain side to write. Is performed.

On the other hand, in an unselected cell, the bit line selection transistor is always turned on, and here also the bit line potential is transmitted to the drain of the unselected memory transistor. VM
Is applied, and this is the applied voltage (2 VM
−Vth), which inhibits writing.

In this embodiment, substantially the same effects as in the first embodiment can be obtained. That is, even in an array configuration in which the memory cell rows are connected to the same bit line in the column direction, all the memory transistors of the non-selected cells can be controlled to be separated from the bit line or the common source line, which has conventionally been a problem. Write disturbance to the non-selected rows is completely eliminated. Further, the number of pages of the block can be set arbitrarily, and the program voltage VM is set to the first
Since it can be reduced to about １ ／ of the embodiment, damage to the gate insulating film can be further reduced. Further, by increasing the VM, high-speed operation can be performed. further,
Also in the read operation, the read disturb for the non-selected row is eliminated, and high-speed read is possible. In the erase operation, the same operation as the write operation of the first embodiment is performed for each cell or each bit string. Can be erased.

Third Embodiment The present embodiment shows a specific cell structure which saves space, a method of manufacturing the same (an embodiment of the manufacturing method of the present invention), and a specific driving method. FIG. 7A is a plan view of four cells showing an example of cell arrangement, and FIG. 7B is an equivalent circuit diagram corresponding to the arrangement example of FIG. 7A. FIG. 8 is similar to FIG.
It is sectional drawing along the AA of (a).

In FIG. 7, BC is a bit contact for connecting a bit line and a bit line selection transistor, SC
Indicates a source contact SC connecting the source line and the source line selection transistor. In this arrangement example, the bit contact BC and the source line VSS (source contact SC) are shared between two cells adjacent in the column direction, and the cell area is reduced. An element isolation region 13 such as LOCOS is arranged as an inter-cell isolation layer in the row direction. This element isolation region 13 has a source contact S
In order to secure an area for arranging C, the bit contact BC
Are also separated in the column direction for every two cells sharing the same. Then, three transistors (one memory transistor and two selection transistors) are arranged in series between the bit contact BC and the source line VSS. It looks like 8.

Referring to FIG. 8, a first impurity region (drain region 14) and a second impurity region (source region 16) common to three transistors in a cell are located at a distance from each other on the front surface side in substrate 12. Is formed. The gate electrode 22 of the bit line selection transistor BT22 and the gate electrode of the source line selection transistor ST22 are formed on the substrate in the space between the drain region 14 and the source region 16 via a first gate insulating film 20 made of, for example, silicon oxide. 24 are spaced apart from each other.
On the substrate in the space between the two gate electrodes 22 and 24, and on both side surfaces facing each other between the two gate electrodes 22 and 24, the second gate insulating film 26 is coated.
A first offset insulating film 28 is formed on 2 and 24.

The insulating films 26 and 28 are made of, for example, silicon oxide. The insulating films 26 and 28 are used as interlayer insulating films, and the memory transistor M22 is formed thereon.
, A dielectric film 30 (corresponding to the intermediate insulating film in FIG. 2), a control gate CG (word line W2), and a second offset insulating film 32. The material of these laminated films is, for example, that the floating gate FG is conductive polysilicon and the dielectric film 30 is ONO
(Oxide-Nitride-Oxide) The film and control gate CG are conductive polysilicon or polycide, and the second offset insulating film 32 is silicon oxide. These stacked films forming the gate electrode structure of the memory transistor extend from the space between the gate electrodes 22 and 24 of both the select transistors onto the first offset insulating films 28 and 28 on the gate electrodes 22 and 24, respectively. And the upper layer side is formed widely. As a result, the bit line width becomes the minimum line width in the process (usually, the gate electrodes 22 and 2 of the selection transistor).
4 (L / S (Line and Space)) and lower resistance.

Gate electrode 2 of bit line select transistor
2 and a first sidewall insulating film 34 made of, for example, silicon oxide or the like is formed on the side surface of the first offset insulating film 28 on the source region side. On the first offset insulating film 28 obliquely above the first sidewall insulating film 34, a second sidewall insulating film 36 made of, for example, silicon oxide or the like is formed. The first and second sidewall insulating films 34 and 36 are similarly formed on the source region 16 side. As a result, the bit contact BC on the drain region 14 and the source contact S elongated in the row direction on the source region 16.
C is formed in a self-aligned manner.

A connection plug 3 is provided in the bit contact BC.
7, and a source wiring layer 46 serving as a common source line VSS is buried in the source contact SC. This source wiring layer 46 corresponds to the “common potential wiring layer” in the present invention. In this example, the connection plug 37 and the source wiring layer 46 are composed of lower conductive layers 38 and 42 made of, for example, polycrystalline silicon and upper refractory metal silicides 40 and 44. The connection plug 37 and the source wiring layer 46 may be made of only a metal or a high melting point metal. This is because the wiring layer (source wiring layer 46) is particularly long and narrowly wired through the cells, so that it is necessary to reduce the resistance. An interlayer insulating layer is formed so as to cover the source wiring layer 46 and almost the entire area on the gate electrode of the memory transistor. Wired. The interlayer insulating layer includes, for example, an etching stopper film 48 made of lower silicon nitride and an upper silicon oxide film 50. Although not particularly shown, second and third metal wiring layers are further laminated thereon, if necessary, with an interlayer insulating layer interposed therebetween, and the uppermost surface is coated with an overcoat.

In such a three-transistor cell structure, the word line W is provided above the bit line selection transistors BT11 to BT22 and the source line selection transistors ST11 to ST22.
1 and W2 are formed so as to be partially overlapped with each other, so that the area does not increase by the amount of the memory transistor. Therefore, the occupied area of the memory cell is small for the three transistors. There is an advantage that it can be completed. When the area per cell in terms of the number of transistors is compared with, for example, an AND type having a conventional configuration, the present cell structure is equivalent to an AND type having a total of four memory transistors and two selection transistors. Further, in this cell configuration, unlike the conventional AND type and NAND type, a source / drain wiring layer (for example, 104 and 105 in FIG. 20) formed of an impurity diffusion layer in a block is not required, so that the wiring region Not only need to be secured, but also the parasitic resistance and the parasitic capacitance of the source and drain can be reduced. Further, in the memory transistor of this example, the gate width direction coincides with the channel length direction, and the setting of the channel width is not restricted by the wiring width in the process. That is,
In the conventional example shown in FIG. 20, the channel width is determined by the width of the word lines (W1 to W4), but this is not the case in the present example. In FIG. 20, the source lines (S1, S1
2) While bit lines (B1, B2) are required,
In this example of FIG. 7A, since the source line is common, it is easy to increase the channel width if the cell occupies the same area.

Next, the manufacturing method of the present invention will be described in order with reference to FIGS. First, although no particular cross-sectional view is shown, for example, p
A semiconductor substrate 12 of the mold type is prepared, and FIG.
The element isolation region 13 is formed in the region indicated by the thick line in FIG. Then
As shown in FIG. 9, a first gate insulating film 20 is formed on a substrate 12.
Is thinly formed by, for example, a thermal oxidation method, and a polycrystalline silicon film 23 and a first offset insulating film 28 are formed thereon.
For example, the layers are sequentially stacked by a CVD method.

As shown in FIG. 10, the laminated films 20, 23, 28 on this substrate are patterned using the same resist pattern until the substrate surface is partially exposed, thereby forming the gate electrode ( The bit line select gate electrode 22) and the gate electrode of the source line select transistor (source line select gate electrode 24) are formed so as to sandwich the first gate insulating film 20 and the first offset insulating film 28 from above and below. The exposed substrate portion and the side surfaces of the gate electrodes 22 and 24 are thermally oxidized, for example, to form a gate insulating film (memory gate insulating film 26a) of the memory transistor on the substrate portion and a side insulating film 26b on the side surface of the gate electrode. Are formed simultaneously. Note that the memory gate insulating film 26a and the side wall oxide film 26b may be replaced by a CVD film instead of the thermal oxidation.

Then, as shown in FIG. 11, a polycrystalline silicon film 29 to be a floating gate FG of the memory transistor is formed on the entire surface, and although not shown in FIG. It is long in the direction orthogonal to the bit line selection gate electrode 22 and the source line selection gate electrode 24, and is patterned in the element isolation region 13 in a parallel stripe shape in which both ends in the width direction partially overlap. Thereby, for the floating gate FG, first, the cell separation in the row direction is achieved.

Next, after a dielectric film 30 for capacitive coupling between the control gate electrode CG and the floating gate electrode FG of the memory transistor is formed on the entire surface (FIG. 1).
2) Further, a polycrystalline silicon film 31 to be a control gate electrode CG and a second offset insulating film 32 are sequentially formed on the entire surface by, for example, a CVD method (FIG. 13). Thus, the formation of the stacked film forming the gate electrode structure of the memory transistor is completed.

As shown in FIG. 14, the laminated film, that is, the polycrystalline silicon film 29, the dielectric film 30, the polycrystalline silicon film 31, and the second offset insulating film 32 are sequentially formed from the lower layer as shown in FIG. 22 and the inter-electrode region of the source line selection gate electrode 24, and the electrodes 22, 2 on both sides.
The patterning is widened so as to be parallel to 4 and partially overlap each other in the width direction of each of the electrodes 22 and 24. This patterning is performed using the same resist pattern as a mask until the first offset insulating film 28 and the memory gate insulating film 26 are exposed. As a result, in the plan view of FIG. 7A, a word line W2 which is parallel to the bit line selection signal line WS2 and the source line selection signal line WB2 and partially overlaps with both is formed. At the time of this patterning, the polycrystalline silicon film 29 having a stripe shape in the row direction is formed.
Are separated in the column direction, thereby forming an isolated floating gate FG for each cell. Then, the exposed memory gate insulating film 26 is used as a through film to form a source gate.
Drain impurities (for example, arsenic ions) are ion-implanted into the substrate, and impurity-doped regions 14a and 16a are formed in the substrate region immediately below the memory gate insulating film 26.

In the step shown in FIG. 15, the first side wall of the upper offset insulating film 28 and the side wall of the first offset insulating film 28 are formed on both side walls of the bit line selection gate electrode 22 and the source line selection gate electrode 24 exposed in the state of FIG. A side wall insulating film is formed, and at the same time, a second side wall insulating film is formed diagonally above the side wall of the gate electrode structure of the memory transistor. The formation of these sidewall insulating films can be achieved by performing anisotropic etching after depositing an oxide film over the entire surface by a CVD method or the like. At this time, the inner portion of the memory gate insulating film 26 exposed on the surface in the state of FIG. 14 is etched, whereby the bit contact BC and the source contact SC are opened while being surrounded by the sidewall insulating film. Is done. The reason why the bit contact BC has a hole shape is that when the element isolation region 13 is LOCOS, a side wall is also formed on the LOCOS side due to a surface step, and the source in which the element isolation region 13 is isolated is formed. In the formation region of the contact SC, the source contact SC is also formed to be elongated in the row direction along the separation shape. Thereafter, when the concentration of the source / drain impurities is further increased, if necessary, an n-type impurity such as arsenic or phosphorus is ion-implanted into the substrate through the bit contact BC and the source contact SC at a high concentration. Drain heavily doped regions 14b and 16b are formed in the substrate.

After the introduced impurities are thermally diffused by annealing to form a drain region 14 and a source region 16 common to the three transistors, as shown in FIG. 16, a conductive material is placed in both contacts BC and SC. Embed. There are various methods for embedding, and for example, there is a method of selectively epitaxially growing silicon from an exposed substrate portion. Also, after depositing polycrystalline silicon on the entire surface, the deposited film is polished by CMP, or coated with a resist, and then etched back to leave the resist as a flattening dummy in the concave portion of the deposited film. The polycrystalline silicon layers 38 and 42 can be formed by a method of lowering and further etching back.

Next, a high melting point metal is deposited on the polycrystalline silicon layers 38 and 42 and reacted (alloyed) to form high melting point metal silicides 40 and 44. Thereafter, the conductive layers 38 and 42 buried on the bit contact side become LOCOS of the element isolation region 13 between the bit line selection transistors.
Above, it is removed by etching using the resist pattern as a mask and divided in the row direction, thereby forming a connection plug 37 for each cell. If an attempt is made to form a contact in the source / drain region in a self-aligned manner after stacking an interlayer insulating film by a normal method without forming this connection plug, if the contact size is smaller than the depth, This connection plug formation is particularly important because the entire contact is buried, making it very difficult to open the contact reaching the substrate. Thereafter, a silicon nitride film (etching stopper film 48) and a silicon oxide film 50 are stacked and deposited to form an interlayer insulating layer. The silicon nitride film 48 is formed under the silicon oxide film 50 in the step of opening the contact hole when etching the silicon oxide film 50 when forming a contact hole for connecting a bit line thereafter. Second offset insulating film 3
This is to prevent the second and second sidewall insulating films 36 from being etched.

Next, the interlayer insulating layer is etched using a resist pattern having an opening formed widely above the bit contact as a mask, and a contact 49 for connecting a bit line is opened as shown in FIG. If the bit line connection contact 49 is formed wide as shown in the drawing, it is formed in a self-aligned manner using the second sidewall insulating film 36 in the direction in which the bit line extends. Subsequently, the contact 49 is covered with a metal such as aluminum, and a bit line is formed in a direction orthogonal to the word line. Thereafter, the non-volatile memory device is completed by forming second and third metal wiring layers as necessary.

In this manufacturing method, the second gate insulating film 26 is formed between the floating gate FG and the select gate electrode 2.
That the bit contact BC, the source contact SC and the bit line connection contact 49 can be formed in a self-aligned manner;
The manufacturing process is compared because the offset insulating film processed together with the gate electrode is often used as an interlayer insulating layer, and the number of lithography steps for patterning the interlayer insulating layer is as small as one contact formation for bit line connection. Simple. Further, it is not necessary to take a margin such as a margin for mask alignment, which is suitable for high integration.

Finally, the operation of the memory cell array having the three-transistor cell structure shown in FIG. 7 will be described. FIG. 17 is a table showing bias voltage setting conditions for the memory cell array. The procedure for applying the voltage is not limited to the following example.

In the memory cell array shown in FIG. 7B, for example, when writing is performed on the memory transistor M11, as shown in FIG. 17, the bit line (selected bit line B1) of the selected column is set to 0 V or the bit line selection. The transistor BT11 is weakly biased (for example, 1.5 V is applied) to such an extent that a channel is easily formed, and the bit lines (non-selected bit lines B2,...) Of the other unselected columns are set to a positive high voltage VM (eg, +20 V) Bias. Further, a positive high voltage VM (for example, +20) is applied to the bit line selection signal line WB1 of the selected row.
V) to ground the source line selection signal line WS1 of the selected row. As a result, the bit line selection transistors BT11 and BT21 connected to the bit lines B1 and B2 are turned on, and the source line selection transistor ST1 connected to the source line VSS.
1, ST21 remains off. Therefore, in the selected row, the potential of the selected bit line B1 is applied to the drain of the selected memory transistor M11, and is kept at 0 V or a weak positive voltage together with the substrate.

On the other hand, for the non-selected rows, the bias voltage is set so that the ON / OFF relationship of the selection transistors is opposite on the bit line side and the source line side to that on the selected row. That is, the bit line selection signal line WB2 of the non-selected row
And a positive voltage (for example, +3 V to +20 V) that turns on the source line selection transistors ST12 and ST22 for the source line selection signal line WS2 in the non-selected row.
Is applied. Thereby, the bit line selection transistor B
T12 and BT22 are turned off, and source line select transistors ST12 and ST22 are turned on. Therefore, in the unselected row, all the memory transistors M12, M12
,... Of the bit lines B1, B
Are separated from the source line VS.
It is fixed to the potential of S (0 V).

.. From the state where all word lines W1, W2,.
The program voltage V _PP which is a positive high voltage only (eg, +2
0V). As a result, in the selected row, the selected memory transistor M11 is turned on to form a channel, and the channel, the drain and the source in the floating state are both held at 0 V (or a weak positive voltage of about 1.5 V), A large electric field due to the program voltage V _PP is applied to the gate insulating film, and electrons are applied to the floating gate on the gate insulating film from the substrate side by FN (Fowler-Nordheid).
m) Injected by tunneling. The drain of the unselected memory transistor M21 in the same selected row is connected to the bit line selection transistor BT21 from the unselected bit line B2.
, A voltage that is lower than the voltage of the bit line selection signal line WB1 by about the gate threshold voltage of the bit line selection transistor BT21 is applied. In order to boost the voltage, substantially the same voltage is applied between the gate and the channel of the non-selected memory transistor M21, the write electric field is not substantially applied, and the disturbance via the word line (word line disturbance) is free. it can.

On the other hand, in the non-selected rows, the word lines W2,... Remain at 0 potential, and a state where no electric field is applied to the gate insulating film of the memory transistor together with the substrate is secured.

As described above, according to the writing method under the conditions shown in FIG. 17, for the selected storage element, the channel, the source, and the drain can be set to the same voltage at the bit line potential 0 V applied from the drain side as in the related art. In addition, since no current flows between the source and the drain, the FN tunnel phenomenon can be used for charge injection. As a result, even if writing and erasing are repeated, deterioration of the gate insulating film is small. As for the unselected storage elements, the memory transistors in the unselected rows can be controlled to be completely disconnected from the unselected bit lines as described above, so that the disturbance (drain disturbance) via the bit lines becomes free. Furthermore, since the unnecessary unselected cells can be controlled to be separated from the bit lines, when setting the voltage of the unselected bit lines, the influence of the voltage setting on the cells of the unselected rows (drain disturbance) as in the related art is considered. The voltage can be set freely without any consideration. Therefore, according to the program voltage V _PP ,
It is possible to set the voltage of an unselected bit line so as to minimize or minimize the electric field applied to the gate insulating film. In this case, word line disturbance (gate disturbance) can be made free.

At the time of reading, as shown in FIG. 17, the source line selection signal lines WS1 and WS2 and the selected word line W1 are supplied with a positive voltage, for example, a power supply voltage V of about + 3V.
_DD is biased, and the unselected word line W2 is grounded.
As for the bit line selection signal line, the bit line selection signal line WB1 of the selected row is biased to the power supply voltage _VDD , while the bit line selection signal line WB2 of the non-selected row is held at the ground potential (0 V). . In this state, the bit lines B1, B
2, ... a, or launch simultaneously from 0V to the power supply voltage V _DD, raises the selected bit line from 0V to the power supply voltage V _DD, the unselected bit line B2, ... and an open or V _DD. When the voltage applied to the unselected bit line B2 is V _DD , the channel potential of the unselected memory transistor M21 becomes V _DD , so that no voltage is applied between the gate and the channel, and the soft write (weak write) ) Does not occur. However, in this case, since the current also flows through the unselected bit line B2, it may be opened to reduce power consumption. As a result, according to the difference in the gate threshold voltage Vth of the selected memory transistor M11, a read current flows through the selected bit line B1, and the amount is detected to determine the cell information.

Conventionally, a read voltage applied to the selected bit line B1 can be applied only to about 1.5 V in order to prevent soft write to unselected cells belonging to the selected column. In this read method, the selected bit line voltage (read voltage) was made higher than in the past, and as a result, high-speed read became possible. Further, in this reading method, reading is possible even when the memory transistor is excessively erased and the gate threshold voltage is in negative depletion. That is, when the memory transistor M11 is read from the selected bit line B1, since the selection transistor BT12 does not exist in the unselected row in the related art, the memory transistor M12 is read.
Is excessively erased, a current flows from the bit line B1 to the source line VSS even if the bias voltage of the word line W1 is 0 V, and the current flowing from the bit line B1 is the current from the selected memory transistor M11. Or
It was impossible to identify whether the current was from the unselected memory transistor M12. The unselected memory transistors M12,... Connected to the bit line B1 are orders of magnitude more than the number of selected memory transistors M11 (ie, one). For example, the number of the non-selected memory transistors is 31 when the bit line is divided, and 1 when the bit line is not divided.
023. In this example, the bit line selection transistors BT12, BT22,.
Even if the read voltage is increased, the current is prevented from leaking from the non-selected cells. In the case of erasing, erasing can be performed in word line units in the same manner as in the prior art by setting the bias voltage shown in FIG.

Fourth Embodiment This embodiment is a case where a memory cell having a three-transistor configuration as shown in the above-described first to third embodiments is provided in a part of a memory cell array. In the three-transistor cell configuration, high reliability can be ensured as described above, but since the number of transistors per bit is larger than in the conventional configuration, the occupied area of the entire memory cell array tends to increase inevitably. In this case, it is important to suppress the increase in the cell area as much as possible by a structural measure as in the third embodiment. On the other hand, some types of write data do not require high reliability. For example, in the field of audio recording, even if the audio data has some defective bits and the bit quality is not good, it does not cause a practical problem if the frequency of occurrence of the defect is up to a certain level. Text data is required to have high reliability. The present embodiment relates to a memory cell array configuration suitable for such a case.

FIG. 18 is a configuration diagram of a memory cell array of the nonvolatile semiconductor memory device according to the present embodiment. This memory cell array includes a first memory block (block A) having a memory cell configuration similar to that of the first embodiment and a second memory block (block B) having a configuration similar to that of the related art. . Although an AND type is illustrated as the second memory block in FIG. 18, a cell type capable of increasing the density of the second memory block is desirable, and for example, a NAND type may be used. Further, other NOR type can be adopted. 1 similar to the first and second embodiments can be applied to the block A, and the specific structure is not limited. However, in order to save space, a structure similar to that of the third embodiment is used. Is desirable. Although the specific structure of the block B is not limited, for example, the configurations shown in FIGS. 19 and 20 can be adopted.

The control method of writing, erasing and reading of the block A has been described in the first to third embodiments.
The description here is omitted. As shown in FIG.
In the case of the ND type, the control can be performed by a general method, for example, in the same manner as in the prior arts 1 and 2. Block B
Is other than the AND type, various control methods as described in the prior art can be adopted.

In the memory cell array configuration of the present embodiment,
Even if the block B does not have a selection transistor for each cell as in a normal NOR type configuration, when a certain memory cell is selected on the block B side, the block A side has a selection transistor for each cell. Therefore, there is an advantage that cells on the block A side connected to the selected bit line are not erroneously written. Also, in a read operation, when a certain cell is read on the block B side, the memory cell of the block A can be separated from the selected bit line by turning off the select transistor. As a result, unnecessary current does not flow from the block A to the selected bit line, and as a result, there is an advantage that read accuracy is increased.

In this embodiment, it is possible to assign a write target according to the type of data. That is, in the above example of audio recording, block A having a three-transistor cell configuration is used.
(In this case, the capacity is, for example, 512 bytes for one word line) for recording text data requiring a relatively high bit quality, and the block B of the conventional configuration may be used for voice data whose bit quality may be somewhat poor. It can be used for data recording. Thus, it is possible to select and store an optimum block having a disturbance resistance sufficient to compensate for the bit quality according to the bit quality (data type) required when storing the data. In other words, if all cells have a three-transistor configuration and high reliability is guaranteed in all regions, good data with low bit quality may be stored in blocks with high disturbance resistance. Quality can be eliminated.
A highly reliable cell having a three-transistor configuration with a high disturbance resistance has a larger occupation area than a normal cell with a low disturbance resistance, but the ratio of the total number of bits of the high reliability cell to the storage data should be optimized. Thus, the occupied area of the entire memory cell array can be minimized.

[0093]

According to the nonvolatile semiconductor memory device, the method of manufacturing the same, and the method of writing according to the present invention, for example, when performing write / erase by FN tunneling which can be driven at a low voltage, connection / disconnection of a bit line and a source line is performed. Can be controlled in units of rows, for example, so that unselected cells connected to the same word line or bit line as the selected cell are not disturbed at all by electrical disconnection, or the allowable range of bias voltage setting is expanded. Even if the disturbance can be received in principle, it is possible to set a bias voltage that is substantially free of disturbance. In addition, since the driving voltage can be increased, which is likely to be disturbed, the parasitic component such as an additional capacitance between the memory transistor and the bit line or the source line is small, and the word line resistance can be reduced. Configuration. Further, in the read operation, the read operation can be made disturbance-free, and the read operation can be performed with high reliability and high accuracy without being affected by the fluctuation of the resistance as in the case where the wiring is formed by the impurity diffusion layer.

In the cell structure in which the gate electrodes of the three transistors in the cell can be arranged close to each other and the manufacture thereof, the formation of the interelectrode insulation is facilitated, the space for the impurity region between the transistors is not required, and the gate electrode is not required. Are stacked and have self-aligned contacts, so that an increase in cell area can be suppressed as much as possible. Further, when controlling the allocation between the memory block having the three-transistor cell configuration and the normal memory block in accordance with the type of the stored data, the occupied area of the entire memory cell array can be minimized while guaranteeing the bit quality. .

[Brief description of the drawings]

FIG. 1 is a main part circuit diagram of a memory cell array showing a memory cell configuration of a nonvolatile memory device according to an embodiment of the present invention.

FIG. 2 is an element cross-sectional view showing a configuration example of a memory transistor according to an embodiment of the present invention, particularly in the case of an FG type.

FIG. 3 is an element cross-sectional view showing another configuration example of the memory transistor, particularly in the case of a MONOS type.

FIG. 4 is an element cross-sectional view showing still another configuration example of the memory transistor, particularly in the case of an MNOS type.

FIG. 5 is a diagram and a table showing a bias voltage application location and setting conditions in a writing method according to the first embodiment of the present invention.

FIG. 6 is a diagram and a table showing application locations and setting conditions of a bias voltage in a writing method according to a second embodiment of the present invention.

7A is a plan view of four cells showing an example of a cell arrangement, and FIG. 7B is an equivalent circuit diagram corresponding to the arrangement example of FIG. 7A.

FIG. 8 is a sectional view taken along line AA of FIG.

FIG. 9 is a cross-sectional view of an element showing a method for manufacturing a nonvolatile memory device according to an embodiment of the present invention, up to formation of a first offset insulating film.

FIG. 10 is a cross-sectional view following FIG. 9, showing the process up to the selection gate electrode processing.

FIG. 11 is a sectional view following FIG. 10 and shows up to formation of a polycrystalline silicon film to be FG.

FIG. 12 is a sectional view following FIG. 11, showing the process up to the formation of a dielectric film.

FIG. 13 is a sectional view following FIG. 12, showing the process up to the formation of a second offset insulating film;

FIG. 14 is a cross-sectional view following FIG. 13, showing up to the low concentration impurity doping of the source and drain regions.

FIG. 15 is a cross-sectional view following FIG. 14, showing up to high concentration impurity doping of source and drain regions.

FIG. 16 is a cross-sectional view following FIG. 15, showing the steps up to the formation of an interlayer insulating layer;

FIG. 17 is a table showing bias voltage setting conditions of a write, erase, and read method according to the third embodiment, using the memory cell array of FIG. 7 as an example.

FIG. 18 is a diagram illustrating a schematic configuration of a memory cell array according to a fourth embodiment of the present invention.

FIG. 19 is a circuit diagram showing a part of a general AND type memory cell array according to Prior Art 1.

FIG. 20 is a plan view of an AND type memory cell array corresponding to FIG. 19;

FIG. 21 is a table showing general setting conditions of a bias voltage of the conventional AND type array shown in FIG.

FIG. 22 shows a general isolation source line NO according to the conventional technology 2
FIG. 2 is a circuit diagram showing a basic configuration of an R-type memory cell array and write bias conditions.

FIG. 23 is a circuit diagram showing another write bias condition according to Prior Art 3 and having the same configuration as that of FIG. 22;

FIG. 24 is a circuit diagram showing a basic configuration of a common source line NOR type memory cell array according to the related art 4 and write bias conditions.

FIG. 25 is a circuit diagram showing the basic configuration and bias conditions of a general NAND type memory cell array according to Prior Art 5; FIG. 25 (a) shows a write operation and FIG. 25 (b) shows a read operation.

[Explanation of symbols]

1,12 ... semiconductor substrate (or semiconductor layer), 1a, 16 ...
Source region, 1b, 14 ... drain region, 2 ... gate electrode (or control gate), 3a to 3c ... laminated film,
4 gate insulating film, 5 floating gate (charge storage means), 6 intermediate insulating film, 7, 9 nitride film, 8 top oxide film, 10 memory cell array, 13 element isolation region, 20, 26 ... Gate insulating film (first or second gate insulating film), 22: gate electrode of bit line select transistor, 24: gate electrode of source line select transistor, 2
8, 32: offset insulating film, 30: dielectric film, 34,
36: sidewall insulating film, 37: connection plug, 3
8, 42 ... conductive layer, 40, 44 ... refractory metal silicide, 46 ... source wiring layer (common potential wiring layer), 48, 5
0: interlayer insulating layer, M1 to Mn, M22, etc .: memory transistor, ST11 to STn1, BT22, etc .: bit line selection transistor (first selection transistor), ST12
To STn2, ST22, etc. Source line selection transistor (second selection transistor), BC bit contact, SC source contact, BL1 (or B1), B
L2 (or B2) ... bit line, WL1 (or W1), W
L2 (or W2) ... word line, CSL (or VSS) ...
Source line (common potential line), WB2 (or SG1) etc .... bit line selection signal line, WS2 (or SG2) etc .... source line selection signal line, FG ... control gate, CG ... floating gate.

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 27/115

Claims (20)

[Claims] 1. A nonvolatile semiconductor memory device having a memory transistor in a memory cell for storing information in accordance with an amount of charge stored in a charge storage means, wherein a source or a drain of the memory transistor is provided for each memory cell. Non-volatile semiconductor having a first select transistor connected between one of the memory transistors and a bit line, and a second select transistor connected between the other of the source or drain of the memory transistor and a common potential line Storage device. 2. The memory transistor according to claim 1, wherein the memory transistors are arranged on a surface of a semiconductor substrate or a semiconductor layer supported by the substrate and are spaced apart from each other, and are connected to a source or a drain of the first or second selection transistor, respectively. A first and a second impurity region, a gate insulating film in contact with the semiconductor substrate or the semiconductor layer between the first and the second impurity region, and a stacked film including at least the gate insulating film and the charge storage means. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising: a control electrode laminated on the semiconductor substrate or the semiconductor layer. 3. The nonvolatile semiconductor memory device according to claim 2, wherein said laminated film has a conductive floating gate as said charge storage means on said gate insulating film. 4. The semiconductor device according to claim 1, wherein the charge storage means is provided at least in the plane facing the semiconductor substrate or the semiconductor layer in the nitride film constituting the multilayer film and in the vicinity of the interface between the nitride film and the oxide film. The nonvolatile semiconductor memory device according to claim 2, further comprising a charge trap discretized by: 5. A first memory block configured by arranging a plurality of memory cells each including the memory transistor and the first and second selection transistors, and a first selection transistor connected to the bit line 2. The device according to claim 1, further comprising: a second memory block configured by arranging a plurality of unit blocks each including a plurality of memory transistors connected between the second selection transistors connected to the common potential line. Non-volatile semiconductor storage device. 6. A first selection transistor is arranged in series with a memory transistor and between a first impurity region connected to a bit line and a second selection transistor connected to a common potential line.
A memory cell is formed by arranging a second select transistor between the first and second select transistors. A semiconductor substrate or a semiconductor layer supported by the substrate is provided between the first and second select transistors. A non-volatile semiconductor, wherein a gate electrode of the memory transistor is provided via a first insulating film formed on the substrate and a second insulating film formed on a side wall of the gate electrode of the first and second select transistors Storage device. 7. The nonvolatile semiconductor memory device according to claim 6, wherein said first insulating film and said second insulating film are integrally formed of the same material. 8. A gate electrode of the memory transistor,
7. A floating gate on the first insulating film, and a control gate laminated on the floating gate via a dielectric film.
3. The nonvolatile semiconductor memory device according to 1. 9. An offset insulating film is provided on each of the gate electrodes of the first and second select transistors, and both sides of the gate electrode of the memory transistor in the channel length direction extend on the offset insulating film. 7. The nonvolatile semiconductor memory device according to claim 6, wherein 10. A first sidewall insulating film formed on each of the side surfaces of the gate electrodes of the first and second select transistors facing the first and second impurity regions, respectively. A second sidewall insulating film formed on both sides of the gate electrode of the memory transistor in the channel length direction on the offset insulating film; and the first and second sidewall insulating films on inner walls, A self-aligned contact hole opened on each of the first and second impurity regions; a connection plug buried in the self-aligned contact hole on the first impurity region; The nonvolatile semiconductor memory device according to claim 9, further comprising a common potential wiring layer buried in the self-aligned contact hole. 11. The nonvolatile semiconductor memory device according to claim 10, wherein said connection plug and said common potential wiring layer are made of conductive silicon whose surface is covered with a refractory metal silicide. 12. The common potential line is formed of the common potential wiring layer, and the bit line is in contact with the connection plug and crosses over the common potential wiring layer via an interlayer insulating layer. The nonvolatile semiconductor memory device according to claim 10, wherein: 13. A first memory block including a plurality of memory cells each including the memory transistor and the first and second selection transistors, and a first selection transistor connected to the bit line. 7. The nonvolatile memory according to claim 6, further comprising: a second memory block configured by arranging a plurality of unit blocks each including a plurality of memory transistors connected between the second selection transistors connected to the common potential line. Semiconductor memory device. 14. A nonvolatile semiconductor memory in which a first selection transistor, a memory transistor, and a second selection transistor are connected in series and formed on a semiconductor substrate or a semiconductor layer supported by the substrate when forming a transistor in a memory cell. A method of manufacturing a device, comprising: a semiconductor region formed on a surface side in a semiconductor substrate or a semiconductor layer, between a first impurity region connected to a bit line and a second impurity region connected to a common potential line Forming a first gate electrode for the first select transistor and a second gate electrode for the second select transistor on each other and via a first gate insulating film, respectively; A second gate insulating film is interposed between the first and second gate electrodes, between the first and second gate electrodes, and between the first and second gate electrodes, and between side walls of the first and second gate electrodes. So, the method of manufacturing the nonvolatile semiconductor memory device having a step of forming a third gate electrode of for the memory transistor. 15. An offset insulating film is previously formed on each of said gate electrodes simultaneously with the formation of said first and second gate electrodes, and said third electrode forming step comprises the steps of: A step of forming a first conductive film on a second gate insulating film; a step of patterning the first conductive film in a stripe substantially parallel to a series connection direction of the transistors; Forming a dielectric film and a second conductive film in order on the conductive film; and forming the second conductive film and the dielectric film together with the underlying first conductive film in a direction substantially parallel to the series connection direction of the transistor. A floating gate that is patterned into orthogonal stripes and is made of the first conductive film and divided for each cell;
And simultaneously forming a word line made of the second conductive film and laminated on the dielectric film.
3. The method for manufacturing a nonvolatile semiconductor memory device according to 1. 16. A step of forming a sidewall insulating film on each side surface of the third gate electrode and the first and second gate electrodes after forming the third electrode, and forming the sidewall insulating film. Simultaneously burying a conductive material in each of the self-aligned contact holes opened on the first and second impurity regions; and contacting the connection plug made of the conductive material on the first impurity region, 15. The method of manufacturing a nonvolatile semiconductor memory device according to claim 14, further comprising: forming a bit line crossing over a common potential wiring layer made of a conductive material on the second impurity region via an interlayer insulating layer. 17. The method according to claim 17, wherein the conductive material is embedded by selective CVD.
The method for manufacturing a nonvolatile semiconductor memory device according to claim 16, wherein the method is performed by: 18. A non-volatile semiconductor in which a memory cell is formed by connecting a memory transistor in series between a first selection transistor connected to a bit line and a second selection transistor connected to a common potential line. A method of driving a storage device, comprising: driving at least one of the first and second selection transistors in common between memory cells in a row direction to write, read, or erase information; Drive method. 19. A voltage substantially the same as that of a word line selected from word lines in which control electrodes of said memory transistors are commonly connected in the row direction to said unselected bit lines during said writing. 3. The method for driving a nonvolatile semiconductor memory device according to claim 1. 20. A first memory block configured by arranging a plurality of memory cells each including the memory transistor and the first and second selection transistors; and a first selection transistor connected to the bit line. And a second memory block configured by arranging a plurality of unit blocks each having a plurality of memory transistors connected between the second selection transistors connected to the common potential line. A method for driving a non-volatile semiconductor storage device, comprising: writing, when writing, first data to the first memory block; and writing second data to the second memory block.