JPH11194997A - Bidirectional serial interface communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform bidirectional serial communication through one communication line and one clock line and to change the setting of a control signal, an address and the number of bits of data. SOLUTION: The data and further the control signal or address in accordance with the necessity of an LSI(large scale integration) to be connected area transmitted through one communication line, and the timing of this transmission is determined by the clock of one clock line 17. A communication format to be transmitted through the communication line is made into bit stream determined for respective peripheral LSI 11, 12 and 13, and this bit stream is transmitted/received at the timing of the clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DSP (Digital Si
gnal Processor) and CPU and its peripheral LSI (Large Sc
The present invention relates to a bidirectional serial interface communication device that transmits and receives data to and from a communication device through a communication line.

[0002]

2. Description of the Related Art When data is transmitted / received between a DSP and a peripheral LSI, both control lines, address lines and data lines may be provided in parallel since both handle parallel data. However, when such parallel wiring is performed, the number of pins of each chip and the number of connection lines connecting the pins are extremely increased, and the size of the chip itself and the size of the substrate on which these chips are mounted are increased. For this reason, a method of transmitting data serially is used.

FIG. 8 is a diagram showing an example of a conventional method of connecting a DSP and its peripheral LSI. The DSP and peripheral LSI have one communication line and two clock lines for a total of 3
It is connected by a book connection line. Specific examples of the peripheral LSI include an A / D converter and a D / A converter. Communication is D
One-way serial communication from the SP to the peripheral LSI.

FIG. 9 shows a communication sequence between the DSP shown in FIG. 8 and a peripheral LSI. It should be noted that although the case where the number of peripheral LSIs is three is shown, communication is performed in the same manner even when the number changes. Clock 1 indicates the timing at which the DSP transmits serial data, and is transmitted one bit at a time in one cycle. One LSI
, Data is transmitted in units of 8 bits, and each peripheral LS
I. Clock 2 indicates the timing of switching to each peripheral LSI, and one cycle is 8
It is the length of the cycle. At the rising edge of clock 2,
Switching to each peripheral LSI is performed, and LSI-1, LS
Data is transmitted in the order of I-2, LSI-3, LSI-1,....

[0005]

However, in the above-mentioned prior art configuration, communication is one-way serial communication from the DSP to the peripheral LSI, and data cannot be transferred from the peripheral LSI to the DSP. In addition, when the number of peripheral LSIs is increased, the priority order or the order of the peripheral LSIs when transmitting data is fixed, so that there has been a problem that the interface circuit must be redesigned. Furthermore, since the communication system is fixed, when exchanging the peripheral LSI of the communication partner, it is necessary to select an LSI of the same communication system as before, or to modify the interface unit to a circuit corresponding to the peripheral LSI of the communication partner. Had also occurred.

The present invention has been made in view of the above problems, and provides a bidirectional serial interface communication device capable of performing bidirectional serial communication using one communication line and one clock line. With the goal. It is another object of the present invention to provide a communication device capable of changing the setting of the number of bits of a control signal, an address, and data.

[0007]

In the bidirectional serial interface communication device according to the present invention, a control signal and an address are transmitted over one communication line as necessary for data and peripheral LSI, and the timing of this transmission is set to one. This is performed using a clock transmitted through the clock line.

According to the present invention, bidirectional serial communication between a DSP or CPU and these peripheral LSIs can be performed using two lines.

[0009]

According to the first aspect of the present invention, one communication line for transmitting a control signal and an address as necessary for a peripheral LSI to be connected to data, and one clock line for transmitting a clock signal. And DSP or CPU and peripheral LS
I and connect control signals, addresses, and data to each peripheral LS
I is converted into a bit string of a format defined for I, transmitted and received according to a clock signal, and performs bidirectional serial communication.

Peripheral LSIs connected to a DSP or CPU for transmitting and receiving data have a communication format unique to each peripheral LSI, such as a memory, such as a memory, or an address or RNW in addition to data. Some require that a control signal such as a (read negative write signal) be transmitted together. Thus, each peripheral LSI
By using one communication line for transmitting a bit string in a format corresponding to the above and one clock line for transmitting a clock that determines the transmission timing of this bit string, DS
Bidirectional serial communication between the P or CPU and each peripheral LSI can be performed.

According to the second aspect of the present invention, the number of bits constituting at least one of the control signal, the address, and the data is variable.

When the DSP or CPU and each peripheral LSI are connected by one communication line and one clock line, the configuration of the control signal, address, and data bit strings constituting the communication format is the same as the configuration unique to each peripheral LSI. Has become. For this reason, when exchanging a certain peripheral LSI, it was necessary to use an LSI having the same communication format as that.
By making the communication format variable by the DSP or the CPU, it is possible to exchange with an LSI having a communication format different from that of the original peripheral LSI.

According to the third aspect of the present invention, the peripheral LSI includes a bit string of unique data and a peripheral L to be further connected.
Some SIs have bit strings of control signals and addresses,
A control line is provided from the DSP or CPU for a peripheral LSI in which a predetermined number of bit strings may be the same from the beginning, and a peripheral LSI that does not communicate is disabled.

If there is a possibility that the first few bit strings of the communication format may be the same for some peripheral LSIs, such peripheral LSIs may be provided with a control line from a DSP or CPU for operating or disabling the LSI. Provided,
At the time of communication, only the target peripheral LSI is operated.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of wiring between LSI chips according to the present invention. DSP10
Are connected by a serial data line 16 and a clock line 17 so as to communicate with the peripheral LSIs 11, 12, and 13. D
The SP 10 is composed of a DSP core 14 which forms a central part thereof, and a bidirectional serial interface circuit 15 which communicates with peripheral LSIs 11 to 13. A serial data line (communication line) 16 and a clock line 17 respectively exit from the bidirectional serial interface circuit 15 and branch to peripheral LSIs 11 to 13.

FIG. 2 is a block diagram showing an example of the bidirectional serial interface circuit of the present invention. The command register 21 performs various settings predetermined by software according to an instruction from the DSP core 14. The tri-state controller 22 generates a signal for controlling the tri-state buffer 27 for controlling the serial data line 16 by DS.
This is performed according to an instruction from the P core 14. Transmission data buffer 23
Temporarily holds the address, data, and control signals from the DSP core 14 and combines them according to an instruction from the command register 21 for a peripheral LSI of a transmission partner, and outputs the combined signals as parallel signals. The conversion circuit 24 converts the signal into a serial signal.

The S / P conversion circuit 25 includes peripheral LSIs 11 to 1
3 is converted into a parallel signal, and the received data buffer 26 temporarily holds the signal, and transmits the data to the DSP core 14. The surrounding L
In the case of reception from the SIs 11 to 13, the control signal and the address are instructed from the DPS core 14 as described in FIG.
The tri-state buffer 27 performs high impedance control according to an instruction from the tri-state controller 22.
The output from the P / S conversion circuit 24 and the input to the S / P conversion circuit 25 are controlled.

Reference numeral 30 denotes an address bus, 31 denotes a data bus,
Reference numeral 32 denotes a control line such as an RNW (Read Negative Write) for informing whether to perform a write (transmission) operation or a read (reception) operation. 33 is a tri-state controller 2
2, a control line for controlling the transmission data buffer 23, and a control line for controlling the reception data buffer 26, all output from the command register 21.

Reference numeral 36 denotes a control line for a control signal output from the tri-state controller 22 for controlling the tri-state buffer 27; 37, a signal line for transmitting a parallel signal from the transmission data buffer 23 to the P / S conversion circuit 24;
8, a signal line for transmitting a parallel signal from the S / P conversion circuit 25 to the reception data buffer 26; a signal line 39, for transmitting a serial signal from the P / S conversion circuit 24 to the tri-state buffer 27; The clock line for transmitting the receiving clock is connected to the clock line 17 in FIG.

FIG. 3 shows the reception data buffer 2 shown in FIG.
3 is a schematic block diagram showing a configuration in which the range of a settable communication signal (control signal, address, data) is set to 8 bits. The same configuration applies to other bit numbers, such as 16 and 32 bits. AIN, BIN, CIN, DI
N, EIN, FIN, GIN. HIN is an input signal held in the transmission data buffer 23, A1 to A9, B1 to B
8, C1 to C7, D1 to D6, E1 to E5, F1 to 4,
G1 to G3, H1 to H2 are tri-state buffers, A
OUT, BOUY, COUT, DOUT, EOUT, F
OUT, GOUT, and HOUT are transmission data buffers 23.
Is an output signal to be output to the P / S conversion circuit 24. The tristate buffers A1 to A9 and H1 to H2 are controlled by a control line 34 from the command register 21.

FIG. 4 is a timing chart when a signal is transmitted from the DSP to one peripheral LSI. Reference numerals 16 and 17 are the serial data line 16 and the clock line 17 shown in FIG. 50 is a 1-bit start bit, 51 is a 1-bit address bit, 52 is a 1-bit RNW bit indicating transmission or reception, and 53 is a 1-bit high impedance bit for avoiding bidirectional data collision. , 2
It is provided before and after the bit data 54. 55 is a 1-bit stop bit indicating the end of a series of signals, 5
Reference numeral 6 denotes a bit which is provided before the start bit 50 and after the stop bit 55 and indicates a high level state indicating that data communication is not performed on the signal line. The bit string represented on the serial data line 16 is the corresponding peripheral LS
I shows a communication format of I, and each peripheral LSI has a unique communication format. DSP 10 is transmitted to LSI
The transmission is performed in the communication format.

The operation of the thus configured bidirectional serial interface communication device will be described. First, the DSP core 14 sets the communication format of the serial interface of one of the peripheral LSIs 11 to 13 for communication in the command register 21 shown in FIG. Assuming that the transmission data buffer 23 shown in FIG. 2 has a settable range of 8 bits for the communication format in terms of hardware, the signal transmitted on the serial data line 16 shown in FIG. ) Is performed, and communication is performed using this communication format. FIG. 3 shows the configuration of the transmission data buffer 23 in the case of 8-bit bit assignment. When communication is performed in units of 32 bits, bit assignment is performed in a range of 32 bits. FIG.
The communication format is determined by the number of start bits 50, address bits 51, RNW bits 52, high-impedance bits 53, data bits 54, high-impedance bits 53, and stops 55 assigned to the serial data line 16 of the first embodiment. You.

If the settable range is 32 bits and the number of data bits is 8, the remaining 24 status bits (control signal and address) can be set between 0 and 24 bits. The start bit 50 has a maximum of 1 bit, the address bit 51 has a maximum of 16 bits, the RNW bit 52 has a maximum of 1 bit, the high impedance bit 53 has a maximum of 2 bits before and after the data bit 54, and the stop bit 55 has a maximum of 2 bits. Is a bit. When the peripheral LSI is a memory or the like, it is possible to transmit and receive a maximum of 32 data bits without assigning all the status bits and using only the data bits.

In the transmission, the transmission data buffer 23 selects parallel data to be transmitted to the signal line 37 and supplies the parallel data to the P / S conversion circuit 24 by setting the command register 21. FIG. 3 shows an address bus 30 and a data bus 31.
And a total of eight control lines 32, and the transmission data buffer 23
Indicates a case where tri-state buffers corresponding to these eight lines are provided. Which signal is output to AOUT, BOUT, COUT and the like is determined by a tri-state buffer controlled by the command register 21. For example, AOUT is AIN, BOUT is EIN, C
When it is desired to output HIN to OUT and output a high level to DOUT to HOUT, tristate buffers A1, B4,
C6, D6, E5, F4, G3, and H2 are set to through.

The signal supplied to the P / S conversion circuit 24 is
The signal is output to the signal line 39 as a serial signal, and is input to the tri-state buffer 27. At the same time, the output from the tri-state controller 22 controls the tri-state buffer 27 via the signal line 36 according to the setting of the command register 21, and as a result, the output serial data line 16 is determined. Similarly, in the case of reception, the signal line 3
9 is output to the DSP core 14.
The section in which the data bit 54 shown in FIG. 4 is transmitted is controlled to have high impedance. At this time, the signal input from the serial data line 16 is S / P
The data is converted into parallel by the conversion circuit 25, and the reception data buffer 26 takes in the signal when all the signals transmitted by the setting of the command register 21 have been converted into parallel. Done.

FIG. 5 is a timing chart in which the DSP 10 receives the transmission signal from the peripheral LSI transmitted from the DSP 10 in FIG. Since the communication format is specific to the peripheral LSI, it is the same as the case shown in FIG. Note that the DSP
When the data 10 is received from the peripheral LSI, the control signal and the address are transmitted from the DSP 10 to the peripheral LSI, and only the data is transmitted from the peripheral LSI to the DSP 10. As described above, the communication between the DSP 10 and the peripheral LSP is always performed under the initiative of the DSP 10, and the peripheral LSI operates passively. D when receiving
The operation of the SP core 14 is 56, 50 to 53, 53 and 56.
Between the address bus 30 and the control line 32 as shown in FIG.
Is directed from the DSP core 14 to the reception data buffer 26, and the address and the control signal are
Send to When the data 54 is transmitted from the peripheral LSI, the output of the DSP 10 (the data line 16 becomes high impedance Hiz to prevent collision with the transmitted data 54).

FIG. 6 shows a second embodiment of the present invention. DS
In the communication format of the peripheral LSIs 11 to 13 connected to P10, there is a possibility that the first few bits such as an address are the same. FIG. 7 shows such an example.
For example, the communication format of the peripheral LSI-2 is composed of 32 bits of data only, and the communication format of the peripheral LSI-1 is a case where the address and the data are each 8 bits.
In this case, when the 8 bits of the address of the peripheral LSI-1 and the 8 bits of the data of the peripheral LSI-2 are the same,
In such a case, the signal lines a and b are wired from the DSP 10 to the peripheral LSI-1 and the peripheral LSI-2, respectively, and when one of the LSIs operates, the other LSI is stopped.

[0028]

As is apparent from the above description, according to the present invention, the DSP or CPU and the peripheral L are controlled by one communication line and one clock line for carrying control signals, addresses and data.
Bidirectional serial communication can be performed between SIs. In addition, since the communication format of the communication line is variable, communication with an LSI having a different communication format can be performed.
An LSI chip can be selected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a connection between a DSP of the present invention and a peripheral LSI;

FIG. 2 is a block diagram illustrating an example of a DSP interface circuit.

FIG. 3 is a block diagram showing a configuration of a transmission data buffer in the interface circuit.

FIG. 4 is a timing chart at the time of transmission of an interface circuit.

FIG. 5 is a timing chart at the time of reception of an interface circuit.

FIG. 6 is a diagram showing a connection method when the first few bits of a communication format may be the same;

FIG. 7 is a diagram illustrating an example of a case where the first few bits of a communication format may be the same;

FIG. 8 is a diagram showing a connection example of conventional one-way serial communication.

FIG. 9 is a timing chart when the communication of FIG. 8 is performed;

[Explanation of symbols]

 Reference Signs List 10 DSP 11 to 13 Peripheral LSI 14 DSP core 15 Bidirectional serial interface circuit 16 Serial data line 17 Clock line 21 Command register 22 Tri-state controller 23 Transmission data buffer 24 P / S conversion circuit 25 S / P conversion circuit 26 Receive data buffer

Claims (3)

[Claims] 1. A DSP comprising one communication line for transmitting a control signal and an address and one clock line for transmitting a clock signal as required by data and a peripheral LSI connected thereto.
Alternatively, a bidirectional serial interface communication device that connects a CPU to a peripheral LSI, converts control signals, addresses, and data into bit strings in a format defined for each peripheral LSI, transmits and receives according to a clock signal, and performs bidirectional serial communication . 2. The bidirectional serial interface communication device according to claim 1, wherein the number of bits constituting at least one of the control signal, address, and data can be made variable. 3. The peripheral LSI has a bit string of its own data and a bit string of a control signal and an address depending on a peripheral LSI to be connected, and the bit strings from the beginning to a predetermined number may be the same. Peripheral LSI
2. A bidirectional serial interface communication device according to claim 1, wherein a control line is provided from said DSP or CPU so that peripheral LSIs that do not communicate are inactive.