JPH11184550A - Computer system and timer interruption control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a computer system with which a CPU power saving function or a CPU clock switching function is more efficiently operated by controlling a timer interruption interval. SOLUTION: When the idle state of a system is detected, a monitor system 101 to be periodically called for monitoring the operating conditions of the system acquires an availability rate of a CPU 11 and reloads a register 131 of a system controller 13. Thus, a timer interruption interval is set corresponding to the acquired availability rate of the CPU 11, and the supply of a clock to the CPU 11 is stopped by estimating that the supply of the clock to the CPU 11 in a stop state is restarted with a timer interruption. Namely, the timer interruption is appropriately controlled so that the longer the idle state lasts, for example, the larger the interval to generate the timer interruption is set.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a notebook-type portable computer system and a timer interrupt control method applied to the system, and more particularly to a CPU interrupt control method for controlling a timer interrupt generation interval. The present invention relates to a computer system and a timer interrupt control method for operating a power saving function, a CPU clock switching function, and the like more efficiently.

[0002]

2. Description of the Related Art In recent years, computers for personal use (personal computers) have been remarkably spread in offices and homes, and various types of personal computers, such as notebook computers, which are easily carried, have been developed. This type of personal computer
Generally, a rechargeable battery is used as a power supply for operating the system. This type of personal computer has various power management functions in order to save the power consumption of a battery whose power capacity is limited.

As one of the power management functions, there is a CPU power saving function for reducing the power consumption of the CPU by stopping the supply of a clock to the CPU when the system is in an idle state. This C
The supply of the clock to the CPU stopped by the PU power saving function is restarted in response to a timer interrupt periodically generated at predetermined intervals. Therefore, in the CPU power saving function, while the system is in the idle state, the occurrence of a timer interrupt triggers
This means that the restart and stop of the supply of the clock to the PU are repeated.

As another power management function, the frequency of the clock supplied to the CPU is normally suppressed to a low level, and the frequency is increased as necessary when the load on the system increases. Therefore, there is a CPU clock switching function for minimizing the power consumption of the CPU. The switching of the frequency of the clock supplied to the CPU also utilizes the fact that the supply of the clock to the stopped CPU is restarted with a timer interrupt that occurs periodically at a predetermined interval. Thus, the supply of the clock to the CPU is temporarily stopped, and the clock frequency is reset during the stop.

[0005] By the way, in the conventional personal computer, since the set value indicating the interval at which the timer interrupt is generated is held as a fixed value, the following inconvenience occurs. (1) Although the system is in an idle state for a long time, a timer interrupt is generated at a fixed interval, so that the clock supply to the CPU is restarted more than necessary (see FIG. 9). (2) To cope with the increase in system load,
In spite of switching to increase the frequency of the clock supplied to the CPU, it is necessary to wait for a fixed (relatively long) interval for a timer interrupt that triggers processing restart (see FIG. 10).

[0006]

As described above, in the conventional computer system, the set value indicating the interval at which the timer interrupt is generated is held as a fixed value. Therefore, the power management function (CPU saving) utilizing this timer interrupt is held. (Power function and CPU clock switching function).

[0007] The present invention has been made in view of such circumstances, and a computer system that controls the interval at which a timer interrupt is generated to more efficiently operate a CPU power saving function, a CPU clock switching function, and the like. And a timer interrupt control method.

[0008]

According to the present invention, in order to achieve the above-mentioned object, a set value indicating an interval at which a timer interrupt is generated is rewritably stored in a system controller which generates a timer interrupt at a predetermined interval. And a timer interrupt generating means for generating a timer interrupt at intervals indicated by the set value stored in the register.

According to the present invention, the interval at which a timer interrupt is generated, which has been conventionally fixed, can be controlled by software according to the situation. By enabling the software to control the interval at which the timer interrupt is generated, for example, (1) if the system is idle for a long period of time, the interval is increased. (2) The system When switching is performed to increase the frequency of the clock supplied to the CPU in order to cope with the increase in the load on the CPU, it is easy to temporarily reduce the interval. Become.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a part of the configuration of a computer system according to an embodiment of the present invention. As shown in FIG. 1, this computer system
CPU 11, memory 12, system controller 13,
A clock oscillation circuit 14, a BIOS-ROM 15, and a magnetic disk device (HDD) 16 are provided.

The CPU 11 includes an application program including a utility such as an operating system 100 stored in the memory 12 and a monitor system 101 for monitoring the operating status of a system operating under the operating system 100.
The system BIOS (Basic) stored in the ROM 15
I / O System).

The memory 12 is a memory device for storing application programs including an operating system 100 and a monitor system 101 which are controlled to be executed by the CPU 11, and data for processing these programs.

The system controller 13 includes a CPU 11
And generates a system interrupt signal (SMI) including a timer interrupt notification to the clock oscillation circuit 14 and sends a signal for instructing the clock oscillation circuit 14 to stop / restart clock supply. When the system controller 13 generates a timer interrupt, if the supply of the clock to the CPU 11 is stopped, first, the clock oscillation circuit 14
Sends a signal instructing the restart of clock supply to
Thereafter, the CPU 11 is notified of a timer interrupt. Further, the system controller 13 is provided with a register group 131 for storing a plurality of set values, and one of these registers rewritably stores a set value indicating an interval at which a timer interrupt is generated. . Then, the system controller 13 generates a timer interrupt at intervals indicated by the stored set values. Also,
The set value indicating the high / low of the frequency of the clock generated by the clock oscillation circuit 14 is also set to 1 in the register group 131.
Are rewritably stored. The set value indicating the level of the clock frequency is transferred to the clock oscillation circuit 14 when a signal instructing restart of the clock supply is transmitted. Further, when one of the registers 131 is read, the system controller 13 sends a signal for instructing the clock oscillation circuit 14 to stop supplying the clock. And this system controller 1
3 is a feature of the present invention in that a set value indicating an interval at which a timer interrupt is generated is stored in a rewritable manner.

The clock oscillation circuit 14 is a circuit for generating and outputting a clock to be supplied to the CPU 11, and stops or restarts the supply of the clock to the CPU 11 in response to an instruction from the system controller 13, and restarts the supply. The frequency of the clock at the time.

The BIOS-ROM 15 stores a system BIOS.
This is for storing S, and is constituted by a flash memory so that a program can be rewritten. The system BIOS includes an IRT routine executed at system startup, a device driver for controlling various I / O devices, a group of subroutines provided for directly controlling hardware, and generation of an SMI (system interrupt). It includes a system management program that is executed in response.

The magnetic disk drive (HDD) 16
Is one of the PCI devices, and is a large-capacity recording medium for storing various programs and data as auxiliary storage of the memory 12.

Hereinafter, the principle of operation of the computer system according to the present embodiment when the supply of the clock to the CPU 11 is stopped in the idle state will be described. Here, C
When stopping the supply of the clock to the PU 11,
The usage rate of the CPU 11 is acquired at regular intervals, and the past C
An object of the present invention is to prevent the clock supply to the CPU 11 from being restarted more than necessary by setting the interval at which the timer interrupt is generated in consideration of the PU usage rate.

FIGS. 2 and 3 show a monitor system 101.
Is on the memory 12 or the magnetic disk device (HDD) 16
The configuration of the various information tables secured above is shown. FIG.
FIG. 6 is a diagram illustrating a table for storing a current usage rate of the CPU 11, a current interrupt interval, and the like. Also, FIG.
It is a figure which shows the table which stores the set value of the interruption interval set according to U utilization. This table is
It stores the number of classifications in the case of classifying the U usage rate, the upper limit of the usage rate for each classification, and the rule for determining the interrupt interval for each classification.

FIG. 4 shows an example of information storage in the table shown in FIG. In this case, the computer system of this embodiment operates at the current CPU usage rate of 30%, the current interrupt interval of 20 ms, the minimum interrupt interval of 5 ms, and the maximum interrupt interval of 100 ms.

Now, in the computer system of this embodiment, it is assumed that the rule for determining the interrupt interval is determined as shown in FIG. The monitor system 102 is called up periodically to monitor the operation state of the system.
Acquire the usage rate of U11. At this point, the usage rate has increased from 30% shown in FIG. 3 to 40%.
It is assumed that 0% has been acquired.

Next, the monitor system 102 sets an interrupt interval according to the obtained CPU usage rate. Since the value of 40% belongs to the category 2 in the table shown in FIG. 5, the timer interrupt interval, which was 20%, is reset to twice 40 ms. This setting
The subroutine of the system BIOS is called (the timer interrupt interval (40 ms) is passed as a parameter) and executed by rewriting the register 131 of the system controller 13.

After setting the interrupt interval, the monitor system 101 stops supplying the clock to the CPU 11. The stop of the clock supply is determined by the system B
This is executed by calling a subroutine of the IOS and reading the register 131 of the system controller 13.

Thereafter, 40 ms later, the system controller 13 generates a timer interrupt, and the supply of the clock to the CPU 11 is restarted with the generation of the timer interrupt. FIGS. 6 and 7 show an operation procedure when the supply of the clock to the CPU 11 is stopped in the idle state.

That is, according to the computer system of this embodiment, for example, as the idle state continues for a longer time, appropriate timer interrupt control such as setting a larger interval for generating a timer interrupt can be performed.

Next, the operation principle when the computer system of this embodiment switches the clock frequency will be described. Here, when switching is performed to increase the frequency of the clock supplied to the CPU 11 in order to cope with an increase in the load on the system, the timer interrupt interval is temporarily reduced to thereby promptly resume the processing. The purpose is to realize.

When the monitor system 102 detects that the load on the system has risen above a predetermined level, and determines that the frequency of the clock supplied to the CPU 11 should be increased, the monitor system 102 first sets a timer. The interrupt interval is set to the minimum value determined for switching the CPU clock. This setting is performed by calling a subroutine of the system BIOS (the timer interrupt interval (minimum value) is passed as a parameter) and rewriting the register 131 of the system controller 13.

Next, the monitor system 101 includes the CPU 1
The frequency of the clock supplied to 1 is reset to a high level. This setting also calls a subroutine of the system BIOS (the high-level frequency is passed as a parameter), and the register 13 of the system controller 13
This is executed by rewriting 1.

When both the timer interrupt interval and the clock frequency have been set, the monitor system 101
Stops the supply of the clock to the CPU 11.
The supply of the clock is stopped by calling a subroutine of the system BIOS and reading the register 131 of the system controller 13.

Thereafter, after a predetermined minimum value for switching the CPU clock, the system controller 13 generates a timer interrupt, and the occurrence of the timer interrupt causes the supply of the clock to the CPU 11 to the high level after the switching. Will be restarted at this frequency. Therefore, the restart of the interrupted process is promptly performed.

After the switching of the clock frequency is completed, the monitor system 101 resets the timer interrupt interval to a predetermined value for normal operation again according to the above-described procedure. As a result, the system controller 13 generates a timer interrupt thereafter at regular intervals. FIG. 8 shows an operation procedure for switching the clock frequency.

That is, according to the computer system of this embodiment, it is possible to greatly reduce the period during which the process must be interrupted when switching the frequency of the clock supplied to the CPU 11.

[0032]

As described above in detail, according to the present invention, the interval at which a timer interrupt is generated, which is conventionally fixed, can be controlled by software according to the situation. When the system is in an idle state for a long period of time, such as when the interval is increased, or when switching is performed to increase the frequency of the clock supplied to the CPU in response to an increase in the load on the system. In addition, the interval can be easily reduced temporarily.

That is, by controlling the interval at which the timer interrupt is generated, the CPU power saving function, the CPU clock switching function, and the like can be operated more efficiently.

[Brief description of the drawings]

FIG. 1 is an exemplary view showing a part of a configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is an exemplary view showing a table, which is stored in a memory or a magnetic disk device (HDD) by the monitor system of the embodiment and stores a current usage rate of a CPU, a current interrupt interval, and the like.

FIG. 3 is an exemplary view showing a table storing a set value of an interruption interval set according to a CPU usage rate, which is secured in a memory or a magnetic disk device (HDD) by the monitor system of the embodiment.

FIG. 4 is a view showing an example of information storage in a table shown in FIG. 2;

FIG. 5 is an exemplary view showing rules for determining an interrupt interval according to the embodiment;

FIG. 6 is an exemplary flowchart illustrating an operation procedure when stopping supply of a clock to a CPU in an idle state according to the embodiment;

FIG. 7 is an exemplary flowchart showing an operation procedure when stopping supply of a clock to a CPU in an idle state according to the embodiment;

FIG. 8 is an exemplary flowchart showing the operation procedure when switching the clock frequency of the embodiment.

FIG. 9 shows a conventional computer system that generates a timer interrupt at fixed intervals even though the system is idle for a long period of time. FIG. 7 is a diagram for explaining the inconvenience that is restarted.

FIG. 10 is a diagram showing a configuration of C in order to cope with an increase in the load on the system caused by the conventional computer system.
FIG. 7 is a diagram for explaining a disadvantage that a timer interrupt, which is a trigger for restarting a process, must wait for a fixed interval for a fixed interval, even though switching is performed to increase the frequency of a clock supplied to a PU.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... CPU 12 ... Memory 13 ... System controller 14 ... Clock oscillation circuit 15 ... BIOS-ROM 16 ... Magnetic disk drive (HDD) 100 ... Operating system 101 ... Monitor system 131 ... Register group in a system controller

Claims (5)

[Claims] 1. A computer system having a system controller that generates a timer interrupt at a predetermined interval, wherein: a register that rewritably stores a set value indicating an interval at which the timer interrupt is generated; A computer system comprising: a timer interrupt generating means for generating the timer interrupt at intervals indicated by the stored set values. 2. When the system controller generates a timer interrupt, the supply of the clock to the stopped CPU is resumed, and the supply of the clock to the CPU is stopped while the system is idle. A computer system having a CPU power saving function of reducing the power consumption of the CPU by repeatedly executing: a register that rewritably stores a set value indicating an interval at which the timer interrupt is generated in the system controller; A timer interrupt generating means for generating the timer interrupt at intervals indicated by the set value stored in the register; a CPU usage rate obtaining means for obtaining the CPU usage rate; and the CPU power saving function To stop the clock supply to Computer system, wherein the CPU usage rate acquisition means to acquire the utilization of the CPU to comprises a timer interrupt control means for setting a register value of the system controller based on the usage rate was the acquired. 3. When the system controller generates a timer interrupt, the supply of the clock to the CPU in a stopped state is resumed by utilizing the fact that the supply of the clock to the stopped CPU is resumed. In a computer system having a CPU clock switching function of resetting the frequency of the clock, the system controller further comprises: a register for rewritably storing a set value indicating an interval at which the timer interrupt is generated; and a register stored in the register. A timer interrupt generating means for generating the timer interrupt at intervals indicated by a set value, wherein when the supply of the clock to the CPU is stopped by the CPU clock switching function, A value of 1 indicates that the system The register value of the controller is set, and after the supply of the clock after switching to the CPU is resumed with the timer interrupt generating means of the system controller generating the timer interrupt, the predetermined value is set for normal operation. A timer interrupt control unit for setting a register value of the system controller with the obtained second value. 4. When the system controller generates a timer interrupt, the supply of the clock to the stopped CPU is resumed, and the supply of the clock to the CPU is stopped while the system is idle. In a timer interrupt control method applied to a computer system having a CPU power saving function for reducing power consumption of the CPU by repeatedly executing the above, when stopping supply of a clock to the CPU by the CPU power saving function. Obtaining a usage rate of the CPU; and setting an interval at which the system controller generates a timer interrupt based on the obtained usage rate of the CPU. . 5. When the system controller generates a timer interrupt, the supply of the clock to the CPU in a stopped state is resumed by utilizing the fact that the supply of the clock to the stopped CPU is resumed. A timer interrupt control method applied to a computer system having a CPU clock switching function for resetting the frequency of the clock, the method comprising the steps of: Setting an interval at which the system controller generates a timer interrupt with a first value set in advance, and supplying a clock after switching to the CPU in response to the system controller generating a timer interrupt. Has been resumed The timer interrupt control method, wherein the system controller in a second value and a step of setting an interval for generating a timer interrupt predetermined normal for operation.