JPH1117954A - Video signal processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce noise at signal edges resulting from detail emphasis processing in the case of noise reduction processing and the detail emphasis processing onto the signal. SOLUTION: Subtractors 21 -2n take difference of processing object pixel data from peripheral pixels other than a processing object pixel and the correlation of the pixels is detected by correlation detectors 31 -3n , a selection means 5 selects only the differences with respect to the high correlation pixels among outputs form the subtractors based on the count result by a counter means 4, an adder 6 sums the selected differences, the sum is divided by a divider means 7 according to the count result to extract noise. Then an adder 8 adds the result to processing object pixels to obtain the processing object pixels whose noise is reduced. In a detail processing section 15, the extracted noise is added to high spatial frequency components extracted by HPFs 111 , 112 at coring circuits 131 , 132 to attenuate the noise and an adder 14 adds the outputs of the coring circuits to the processing object pixels whose noise is reduced to obtain an output whose details are emphasized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a noise reduction circuit and a detail emphasis circuit used in video equipment such as a video camera.

[0002]

2. Description of the Related Art In a conventional video camera signal processing, noise reduction processing (hereinafter referred to as NR processing) is performed.
And detail enhancement processing. Hereinafter, these processes will be described.

NR processing The NR processing aims at improving image quality by reducing noise having spatially high frequency components.

Conventionally, in this NR processing, a spatial LPF (Low
Pass filter) and three-dimensional NR processing such as frame cyclic processing. Here, as the former two-dimensional NR processing, a spatial LPF will be particularly described as an example.

In this technique, LPF processing is performed in the horizontal and vertical directions of a video signal. For example, FIG.
A predetermined number n, such as shown in for two-dimensional signal block consists of pixels (in this example n = 9), appropriate coefficient to each pixel as shown in Equation c _i, the average value is multiplied by _j a _{Ask out} .

A _out = (ΣΣc _i , _j · a _i , _j ) / n where Σc _i , _j = n.

In FIG. 7, _ai , _j is hereinafter referred to as a pixel to be processed, and other than _ai , _j are referred to as peripheral pixels.

Although this processing reduces noise having spatially high frequency components, simple LPF processing attenuates high frequency components in edge portions and detail portions of an image, so that edges become unclear. And the image quality is deteriorated such as the resolution is lowered.

In order to prevent such image quality deterioration, a two-dimensional adaptive LPF described below has been proposed.

In this two-dimensional adaptive LPF, the correlation between the pixel to be processed and the surrounding pixels is checked, and only the pixels having a high correlation are selected and averaged as shown in the following equation to obtain an edge portion. And an output a _{out in} which unnecessary noise is reduced while preventing image quality deterioration in the detail section.

A _out = (ΣΣc _i , _j * a _i , _j ) / n where n is the number of highly correlated pixels in the signal block, and c _i , _j is “ 1 ", and" 0 "when the correlation is low.

Two-dimensional adaptive LPF for calculating the above equation
FIG. 8 shows a specific example of the configuration.

In FIG. 8, 1 is a synchronization means, 18 is 2
This is a dimension NR section.

The synchronizing means 1 extracts a predetermined number n (n = 9 in the example shown in FIG. 7) of pixel signals from a video signal input from an input terminal to form a signal block. FIG. 9 shows a specific configuration example.

In FIG. 9, 27 _{1 to} 27 ₂ represent 1H (H:
Delay element that is delayed by the time of
8 _{1-28 6} a signal of each pixel 1T: a delay element for delaying time of the (T 1 sample period of the pixel).

On the other hand, the two-dimensional NR section 18
LPF processing is performed in the horizontal direction and the vertical direction of the signal of each pixel included in the signal block extracted in step (1).

[0017] That is, first, the subtraction unit 2 ₁ to 2 _n is 7, determines the difference of the target pixel a _i, and _j, and the other pixels.

The correlation detectors 3 _{1 to} 3 _n are provided with subtracting means 2 ₁ to 2 _n.
Are compared with a predetermined threshold level and the magnitude thereof, respectively. If the output is below the predetermined level, it is determined that the correlation with the pixel to be processed is strong. It determines that the correlation is weak and outputs “0” to the counting means 4.

The counting means 4 counts the number of "1" out of the n outputs of the correlation detectors 3 _{1 to} 3 _n , obtains a divisor in the average value processing from the result, and outputs it. Also outputs the position information of the peripheral pixel each time it is determined that the strong correlation in the correlation detector 3 ₁ to 3 _n.

A specific example will be described with reference to the signal block shown in FIG. 7. Now, a pixel a _i , _j to be processed is set to have pixels a _i−1 , _j , a _i , _j−1 , a _i , _{j + 1} , a _{i + 1} , _j
If it is determined that the four pixels have a strong correlation, it is necessary to perform averaging of the five pixels, so that the divisor “5” and the position information of the four pixels are output.

The selection means 5 is the output of the counting means 4
According to the position information of the pixel having a strong correlation, peripheral pixels determined to have a strong correlation, here a _i−1 , _j , a _i , _j−1 ,
All four pixels a _i , _{j + 1} and a _{i + 1} , _j are selected and input to the adding means 6 as they are.

The adding means 6 includes a processing target pixel a _i , _j , and the four peripheral pixels a _i-1 , _j selected by the selecting means 5.
The sum of the outputs of a _i , _j−1 , a _i , _{j + 1} , a _{i + 1} , _j is obtained and input to the dividing means 7.

The dividing means 7 divides the output of the adding means 6 by the divisor which is the output of the counting means 4 to obtain all the pixel values a _i , _j , a _i-1 , _j , a _i ,
The average value of _j-1 , _ai , _{j + 1} , _{ai + 1} , _j is determined. That is, the result of the above equation is obtained.

By performing such processing, noise can be reduced by suppressing dullness of edges and deterioration of detail. This will be described with reference to FIG.

In FIG. 10, it is assumed that the shaded portion on the left side in the figure indicates a low luminance portion, and the other right portion indicates a high luminance portion.

[0026] Now, the difference between the high luminance portion and a low luminance portion of FIG (contrast) is larger than the threshold level set in advance for each of the correlation detector 3 ₁ to 3 _n of FIG. 8, each pixel Assuming that the level of the superimposed noise is smaller than the threshold level, each of the pixels a _i−1 , _j−1 , a _i , _j−1 and a _i existing in the low-luminance part (left side in FIG. 10) ₊₁ and _j-1 are excluded from the averaging process, and the average value of only the remaining pixels existing in the high-luminance part (the right side in FIG. 10) is obtained. Therefore, edge dulling does not occur. The same applies to vertical edges.

Further, as for the detail portion of the image, the detail larger than the above-mentioned threshold is excluded from the averaging process, so that the detail is not lost.

As described above, according to the two-dimensional NR processing, when an edge or detail exists in a signal block, pixels far apart from each other in the correlation value are excluded from the averaging processing. Degradation of resolution, such as dullness, can be reduced to some extent.

Detail enhancement processing The purpose of the detail enhancement processing is to enhance the sharpness of edges and the resolution of the entire screen by enhancing the level of spatially high frequency components. FIG. 11 shows an example of a specific configuration of the above.

In FIG. 11, 1 is a synchronizing means, 15 is a detail processing section, 11 is an HPF (High Pass Filter),
12 is a multiplication means, 13 is a coring circuit, and 14 is an addition means. In the figure, the upper HPF 11 ₁ , the multiplication means 12 ₁ ,
The path of the coring circuit 13 ₁ and the path of the adding means 14 are for vertical detail enhancement processing, and the HPF 11 ₂ at the lower side in FIG.
The path of the multiplying means 12 ₂ , the coring circuit 13 ₂ , and the adding means 14 is for horizontal detail enhancement processing.

The configuration of each of the above HPFs 11 ₁ and 11 ₂ is, for example, as shown in FIG.
It comprises a dividing means 25 and a subtractor 26.

Further, assuming that the input signal is x and the output signal is y, the coring circuits 13 ₁ and 13 ₂ perform processing as shown in the following equation.

Y = 0 (when −k ≦ x ≦ k) y = x−k (when x> k) y = x + k (when x <−k) where k is a positive constant.

That is, the coring circuits 13 ₁ and 13 ₂
As shown in FIG. 13, when the input signal is smaller than a certain level k, the input signal becomes 0. When the input signal exceeds the certain level k, a process of subtracting the input signal by the level k is performed.

The operation of the detail emphasizing processing circuit having this configuration will be described with reference to an example in which the signal block shown in FIG. 7 is used.

The synchronizing means 1 converts a pixel to be processed a _i , _j from the input signal and a predetermined number of peripheral pixels in the horizontal and vertical directions centered on the pixel to be processed a _i , _j , here a _{i + 1} ,
The four pixels _j , a _i−1 , _j , a _i , _j−1 and a _i , _{j + 1} are extracted and output to the detail processing unit 15 at the next stage.

The signals of these pixels a _i , _j , a _{i + 1} , _j , a _i−1 , _j , a _i , _j−1 , a _i , _{j + 1} output from the synchronization means 1 are output. Of which, vertical pixels a _i−1 , _j , a _i , _j , a _{i + 1} , _j
To but above the HPF 11 _1, a horizontal pixel _{a i, j-1, a} i, j, a i, j + 1 is input to the HPF 11 ₂ of the lower spatial vertical and horizontal , A high frequency component is extracted.

Here, in order to facilitate understanding, a description will be given below taking a vertical signal path as an example. For the sake of simplicity, it is assumed that the signal levels of the pixels in the horizontal direction are all the same and do not change.

[0039] On the upper side of the HPF 11 _1, the processing target pixel a _i, pixel after one line before and one line of the _{j a i-1, j,} a
The signals of _{i + 1} and _j are input.

Here, the synchronization means 1 near the vertical edge
The state of the temporal change of each output of the pixels a _{i + 1} , _j , a _i , _j , a _i-1 , _j in the vertical direction including noise is shown in FIG. )become that way. In FIG. 14, a symbol d indicates a delay of one line.

Inside the HPF 11 ₁ , each pixel a _i−1 , _j , a one line before and one line after the pixel a _i , _{j to be} processed.
_After the signals of _{i + 1} and _j are added by the adder 24 and then multiplied by 1/2 by the dividing means 25, the output of the dividing means 25 is added and averaged as shown in (4). The signal is the subtractor 24
Is subtracted from the signal of the processing target pixel a _i , _j shown in (2), and the output is as shown in (5). That is,
A spatially high frequency component in the vertical direction is extracted.

The output of each HPF 11 ₁ is a suitable gain multiplier 12 ₁ is input (here 1 to be) is applied to the next stage of the coring circuit 13 _1.

In the coring circuit 13 ₁ , as shown in (6), a portion where the amplitude is smaller than a certain level k is 0,
The portion exceeding the level k is the amplitude by a predetermined level k is subtracted, the output of the circuit 13 ₁ is as (7). That is, the noise contained in the output of the multiplying means 12 ₁ is removed.

Although the above description has been made taking the vertical signal processing path as an example, the same applies to the horizontal signal processing path.

The outputs of the coring circuits 13 ₁ and 13 ₂ are added to the pixels a _i and _j to be processed by the adder 14 and output.

In the above description, each of the two-dimensional NR processing and the detail emphasis processing has been described. However, since the characteristics of the video camera are actually high in image quality and high in resolution, these characteristics are desirable. It is required to integrate the two processes.

However, as described above, the NR processing is a method of increasing the S / N ratio by sacrificing the details, while the detail emphasizing processing reduces the detail of the video at the expense of the S / N. This is a method for sharpening, and both processes are in a trade-off relationship. For this reason, the configuration is important for achieving both processes.

For example, in a configuration in which two-dimensional NR processing is performed first and then detail enhancement processing is performed,
Since the detail is degraded by the R processing, a sufficient effect cannot be obtained in the detail enhancement processing at the subsequent stage. Conversely, when detail enhancement is performed first,
Since the S / N of the input signal to the R processing circuit deteriorates, it is difficult to distinguish between noise and detail, and it is difficult to obtain a sufficient NR effect.

As described above, if it is attempted to perform both processes in a time-series manner, one of the processes is sacrificed. In the prior art, as shown in FIG. It is proposed that NR processing is performed only on the line containing the pixel to be processed and the detail signal extracted from the signal before the NR processing is added to the NR output, so that the detail that has been slightly deteriorated by the NR processing can be restored. Have been.

In FIG. 15, the two-dimensional NR section 18 is basically the same as the configuration of the two-dimensional NR section 18 shown in FIG. The detail processing unit 15 is also basically the same as the configuration shown in FIG. However, the synchronization means 1 is commonly used to reduce the circuit scale.

The operation of the circuit having the configuration shown in FIG. 15 will be described further with reference to the time chart shown in FIG.
For the sake of simplicity, it is assumed that the signal levels of the pixels in the horizontal direction are all the same and do not change.

Now, focusing on the vertical processing paths 11 _{1 to} 13 ₁ in the detail processing section 15, the processing is performed as described above in (1) to (7) of FIG. Become.

[0053] Then, the output of the coring circuit 13 _1,
After being summed with the horizontal direction of the output signal of the coring circuit 13 ₂ in the adder 14, it is input to the adder 23.

On the other hand, the signals of the processing target pixels a _i , _j shown in (2) of FIG. 14 are reduced in noise by the two-dimensional NR section 18 as described in the description of the operation of the configuration of FIG. 8), which is also input to the adder 23.

The adder 23 outputs the output of the two-dimensional NR unit 18.
(See (8) in FIG. 14) and the output of the detail processing unit 15.
(See (7) in FIG. 14) is added to obtain a signal having the waveform of (9).

As is clear from the figure, the signal of (9) is a waveform in which the edge is emphasized, as compared with the waveform of (2).
In addition, the noise in the portion where the level is flat is reduced to some extent.

[0057]

However, the following problem still remains in the circuit having the structure shown in FIG.

That is, as shown in FIG. 13, the coring level k in the conventional coring processing is always set to be constant irrespective of the noise level superimposed on the input pixel, and the edge portion having a large contrast is obtained. (FIG. 14
As shown in (6), the input signal having an amplitude larger than the coring level k is subjected to the process of subtracting the amplitude by k. It cannot be removed.

If the output of the detail processing unit 15 is directly added to the output signal of the two-dimensional NR unit 18, the result is as shown in FIG. 14 (9). Noise is reduced, but at the edge
(No. A ′ in FIG. 14 (9)) remains as it is, and as a result, the noise at the edge portion A ′ becomes
There has been a problem that the NR process is more noticeable than a flat portion in which noise has been reduced.

The present invention has been made to solve the above problems, and has a NR
Process and detail enhancement process as much as possible,
It is an object of the present invention to provide a video signal processing device which improves an image quality by improving an S / N ratio including an edge portion having a high contrast, and further increases a resolution by detail enhancement.

[0061]

SUMMARY OF THE INVENTION In order to solve this problem, the present invention is configured so that noise information extracted from an input signal by noise extraction means is used for coring processing.

Thus, appropriate coring processing according to the noise level can be performed.

[0063]

1 is a block diagram showing a configuration of a video signal processing apparatus according to an embodiment of the present invention; FIG. 2 is a block diagram showing a configuration of a video signal processing apparatus according to a first embodiment of the present invention; Noise extracting means for extracting a noise component based on an output signal of each pixel of the means,
A first addition unit that adds an output of the noise extraction unit to the input video signal to attenuate noise, a frequency component extraction unit that extracts a high-frequency spatial frequency component from the input video signal, A second adding means for adding an output of the noise extracting means to an output of the frequency component extracting means to attenuate noise, and adding an output of the first adding means and an output of the second adding means. And third adding means for obtaining an output with detail enhancement.

With this configuration, the noise information extracted from the input signal by the noise extracting means can be used for coring processing.

According to a second aspect of the present invention, in the video signal processing apparatus according to the first aspect of the present invention, the noise extracting means includes a pixel at a specific position of a signal block formed by the signal block forming means. And a subtraction unit that takes a difference between the value of the pixel other than the pixel at the specific position, and a magnitude comparison between an output of the subtraction unit and a predetermined level.
A comparator that outputs a signal indicating a comparison result, and among the outputs of the comparator, counts the number of signals indicating a comparison result smaller than a predetermined level, and outputs a pixel that outputs a result of the count and a value smaller than the predetermined level. Counting means for respectively outputting a signal to be specified; selecting means for selecting and outputting only the signal of the pixel specified by the output of the counting means from the output of the subtracting means; and adding the respective outputs of the selecting means It comprises an adding means and a dividing means for dividing the output of the adding means by the output of the counting means.

With this configuration, the average value of the difference between the pixel to be processed and the surrounding pixels can be added to the high frequency spatial frequency component extracted from the input signal.

According to a third aspect of the present invention, in the video signal processing apparatus according to the second aspect of the present invention, the video signal processing apparatus further comprises a numerical value generating means for generating a predetermined numerical value according to the counting result output from the counting means. The division means divides the output of the addition means by the output from the numerical value generation means.

According to this configuration, the average value of the difference between the pixel to be processed and the peripheral pixel can be calculated with a simpler configuration than in the case of the second aspect.

According to a fifth aspect of the present invention, in the video signal processing device according to the first aspect of the present invention, the noise extracting means includes a delay means for delaying the video signal by a predetermined time; A subtraction means for subtracting a video signal input from an output of the subtraction means, and a non-linear processing means for performing non-linear processing on an output of the subtraction means, wherein an output of the first addition means is an input to the delay means, The output of the non-linear processing means is the output of the noise extraction means.

This configuration has the effect that the accuracy of noise extraction can be further improved.

(Embodiment 1) FIG. 1 is a block diagram showing a video signal processing apparatus according to an embodiment of the present invention.
And the parts corresponding to the conventional one shown in FIG.
The same reference numerals are given.

In FIG. 1, 1 is a synchronizing means, 18 ₁ is a two-dimensional NR section, and 15 is a detail processing section.

The feature of the first embodiment is that the two-dimensional NR unit 1
8 ₁ consists noise extraction means 10 ₁ and the adder 8 Prefecture, the output of the subtractor 2 ₁ to 2 _n constituting the noise extraction unit 10 ₁ is applied to the selection means 5, also, the division of the noise extraction means 10 ₁ The output of the means 7 is an adder 8 and a coring circuit 13 ₁ , 1
3 ₂ are adapted to join together, further, the adder 8
Is that has a configuration for adding the output of the dividing means 7 and the output of the noise extraction unit 10 _first synchronizing means 1 together.

[0074] Thus, construction of a two-dimensional NR unit 18 _1, what differs from the configuration shown in FIG. 8, as described below, the output of the noise extracting means 10 _1, the core of the detail processor 15 This is because it is not used for ring processing.

The other structure is the same as that of the conventional example shown in FIG. 15, and the same reference numerals are given to the same parts as those of the conventional example, and the detailed description is omitted here.

The synchronizing means 1 corresponds to the block forming means in the claims, the adder 8 corresponds to the first adding means in the claims, and the correlation detectors 3 _{1 to} 3 _n.
Describes a HPF 11 ₁ , 1 as a comparator in the claims.
A frequency component extracting means 1 ₂ in the appended claims,
The coring circuits 13 ₁ and 13 _{2 correspond} to the second adding means in the claims, and the adder 14 corresponds to the third adding means in the claims.

Next, in the video signal processing circuit having the above configuration, the operation of the two-dimensional NR section 181 will be described _first .

The synchronizing means 1 extracts a predetermined number (nine in the example shown in FIG. 7) of pixels contained in a two-dimensional signal block from the video signal input from the input terminal 16.

[0079] subtraction means 2 ₁ ~2 _{n (n} = 9 in the case of signal blocks in FIG. 2), the processing target pixel a _i, the process from the values of the peripheral pixels other than the _j pixel a _i, subtracts the value of _j Calculated difference,
Clipped to the upper and lower levels can be compared in a subsequent correlation detector 3 ₁ to 3 _n and outputs.

The correlation detectors 3 _{1 to} 3 _n are provided with subtracting means 2 ₁ to 2 _n
Is compared with a predetermined threshold value, and if it is less than the threshold value, it is determined that there is a correlation, and "1" is output if it is larger than the threshold value.

The counting means 4 counts the number of “1” appearing in the outputs of the correlation detectors 3 _{1 to} 3 _n , that is, the number of peripheral pixels determined to have a correlation, and calculates a numerical value to be a divisor in the averaging process. Is output, and every time it is determined that there is a correlation, the position information of the peripheral pixels is also output.

The selecting means 5 determines the subtracting means 2 ₁ to 2 _n according to the position information of the highly correlated pixels output from the counting means 4.
Are selected, and all the differences between the peripheral pixel determined to have a correlation and the pixel to be processed are selected and input to the adding means 6 as they are.

For example, using the signal block shown in FIG. 2, for example, four pixels a _i−1 , _j , a _i , _j−1 , a _i , _{j + 1} , a _{i + 1} , _j are formed. When it is determined that there is a correlation with the processing target pixel a _i , _j , (a _i−1 , _j− a _i , _j ), (a _i , _j−1 −a _i , _j ),
Since it is necessary to average the four differences (a _i , _{j + 1} −a _i , _j ) and (a _{i + 1} , _j −a _i , _j ), these differences are output.

The adding means 6 selects the four selected by the selecting means 5.
The sum of the two differences is obtained and output to the dividing means 7.

The dividing means 7 divides the output of the adding means 6 by the output of the counting means 4 to obtain the average value of the difference between the peripheral pixel and the pixel to be processed. Here, the average value is set to k (t).

The adder 8 adds the value of the pixel a _i , _j to be processed, output from the synchronization means 1, to the output k from the division means 7.
(t) is added.

Here, the output of the two-dimensional NR unit 18 of the conventional two-dimensional adaptive LPF shown in FIG. 8 is as shown in the equation, but now it is assumed that there are n pixels having high correlation (accordingly, All c _i , _j = 1), and the processing target pixels a _i , _j are a ₁ ,
By deploying the formula by replacing the surrounding pixels in a ₂ ~a _n, a
_out = (a ₁ + a ₂ +... + a _n ) / n.

On the other hand, in the configuration of FIG. 1, the output a _out of the adder 8 is added to the value of the pixel a _i , _j to be processed output from the synchronization means 1 by the value k (t) output from the division means 7. ) =
Since ((a ₂ −a ₁ ) +... + (a _n −a ₁ )} / n is added, the following equation is obtained.

A _out = a ₁ + k (t) = a ₁ + {(a ₂ −a ₁ ) +... + (A _n −a ₁ )} / n = (a ₁ + a ₂ +... + A _n ) / N ... In conclusion, when the output of the two-dimensional NR unit 18 of the conventional two-dimensional adaptive LPF shown in FIG. 8 is compared with the output of the adder 8 having the configuration shown in FIG. , Both outputs have the same value.

Here, in the equation, a ₁ is the signal of the pixel to be processed containing noise. By adding the value k (t) output from the dividing means 7 to this signal a ₁ , Is obtained, the output a _out is reduced.
K (t), which is the second term of the equation, can be regarded as "a noise on the pixel to be processed with its polarity inverted".

Therefore, if this noise information is used in the coring processing of the detail processing unit 15 as described below, it is possible to set an appropriate coring amount for each pixel.

The operation of the detail processing unit 15 will be described next.

The detail processing section 15 includes the synchronization means 1
_Ai , _j , _{ai + 1} , _j , a shown in FIG.
_Of the signals of _i-1 , _j , _ai , _j-1 , _ai , _{j + 1} , the vertical pixels _ai-1 , _j , _ai , _j , _{ai + 1} , _j are the upper side. HPF11
To _{1, a i, j-1} , a i, j, a i, j + 1 is input to the HPF 11 ₂ in the lower, high spatial frequency components in the vertical and horizontal directions is a horizontal direction of the pixel Is extracted.

Here, a vertical signal path will be described as an example with reference to the time chart of FIG.

[0095] On the upper side of the HPF 11 _1, the processing target pixel a _i, pixel after one line before and one line of the _{j a i-1, j,} a
The signals of _{i + 1} and _j are input.

Here, the synchronization means 1 near the vertical edge
The state of the temporal change of each output of the pixels a _{i + 1} , _j , a _i , _j , a _i-1 , _j in the vertical direction including noise is shown in FIG. )become that way. In FIG. 2, a symbol d indicates a delay amount for one line.

[0097] In the interior of _{HPF11 1, a i + 1,} j, a
_i-1 and _j are added and averaged as shown in (4), and subtracted from _ai and _j shown in (2), so that the output is as shown in (5). Then, an appropriate gain (here, 1) is multiplied by the multiplication means 12 ₁ and the next stage coring circuit 13 ₁
Is input to

Assuming that the input signal from the multiplication means 12 ₁ is x and the output signal is y, the coring circuit 13 ₁
Alternatively, the processing shown in the equation is performed.

Y = x + k (t) ... or y = x + k (t) (| x |> | k (t) |) y = 0 (| x | ≦ | k (t) |)
... That is, the coring circuit 13 _1, to the signal x input from the multiplication unit 12 ₁ shown in (5), the output k of the dividing means 7 of the noise extraction means 10 as shown in (6) (t )
Is added.

Here, the output k (t) of the dividing means 7 is not a constant value (see the equation) as in the prior art, but a function of the time t which varies for each pixel. Moreover, since it can assumed that the noise is considered to be superimposed on the processing target pixel a ₁ as described above were polarity inversion by adding it to the signal x from the multiplier means 12 _1, (7) As shown,
Not only flat parts but also edge parts with large contrast (Fig. 2
The noise is effectively removed also in (7) the portion indicated by the symbol B).

In the equation, the output k (t) of the dividing means 7 is
Is always regarded as noise whose polarity is inverted. In the equation, only when | x |> | k (t) |, the output k (t) is regarded as noise whose polarity is inverted, and | x | ≦ | K (t)
In the case of |, the noise is regarded as small and the output y is made as flat as possible.

[0102] The adder 14 is the output of the noise extracting means 10 ₁ (8), since adding the output of the coring circuit 13 ₁ (7), is obtained (9). (9) As is clear, not only the flat portion but also the edge portion (reference numeral B ′ in FIG. 2 (9))
) Are also reduced at the same time.

As described above, in the first embodiment, the optimal coring processing for removing noise can be performed by performing the equation or the processing shown in the equation.

Further, even when the detail signal exceeds the coring level at an edge portion having a large contrast, the coring value changes according to the magnitude of the noise, so that the noise can be effectively reduced.

(Embodiment 2) Although a sufficient effect can be obtained by the configuration shown in Embodiment 1, in general, the dividing means 7
Increases the circuit scale. Therefore, the configuration of the second embodiment is such that the same processing as described above is realized by a small-scale circuit.

FIG. 3 is a block diagram showing a video signal processing device according to the second embodiment.

[0107] The feature of this embodiment 2, as a noise extraction unit 10 ₂ constituting the two-dimensional NR processing unit 18 _2, the numeric value generation means 9 together with the newly provided, the dividing means 7 ', 2
, And a bit shifter for performing division by a power of.

Since the other configuration is the same as that of the first embodiment shown in FIG. 1, portions corresponding to those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.

The numerical value generating means 9 outputs an appropriate value of a power of 2 according to the divisor output from the counting means 4.

Here, the numerical value generated by the numerical value generating means 9 will be considered.

For example, considering the case where the sum of n data is divided by a power of 2 m (m 異 な る n) different from n as in the following equation, (a ₁ + a ₂ +... + A _n ) / m = (n / m) · (a ₁ + a ₂ +... + a _n ) / n..., which is an order of n / m times, so that the number of data to be averaged to match the order is also m Need to be

[0112] However, as in this embodiment 2, the noise extraction unit 10 _2, considering the case of obtaining the average value of the difference (see formula), as _{follows, a 1 + {(a 2} -a ₁ ) +... + (A _n −a ₁ )｝ / m = a ₁ + (n / m) · {(a ₂ −a ₁ ) +... + (A _n −a ₁ )} / n = a _{1 + (n / m) ·} k (t) ... next, the gain of the n / m is relative to the average value k of the difference (t) becomes such that, where by selecting only strong peripheral pixel correlation is since taking a difference, only a sufficiently small value compared to the value of each difference is small, thus difference average value k (t) be the data a _1. Therefore, the order of the output of the adder 8 does not change.

This means that the degree of freedom in selecting the divisor can be increased by performing the difference averaging process.

FIG. 4 shows an example of specific input / output characteristics of the numerical value generating means 9 from the above viewpoints.

As described above, the output value does not necessarily need to be larger or smaller than the input value, and can be freely determined.

The dividing means 7 divides the output of the adder 6 by a power of 2 which is the output of the numerical value generating means 9,
That is, the average value of the difference between the peripheral pixel and the processing target pixel is obtained by performing a bit shift by a power.

The output of the dividing means 7 is also input to the coring circuits 13 ₁ and 13 ₂ of the detail processing section 15 together with the adder 8, and the same processing as in the first embodiment is performed. With the above configuration, the same effect can be obtained while greatly reducing the circuit scale of the dividing means 7 'as compared with the first embodiment.

(Embodiment 3) In Embodiment 3, it is possible to extract noise more accurately than in Embodiments 1 and 2.

FIG. 5 is a block diagram showing a video signal processing apparatus according to the third embodiment.

[0120] In this embodiment 3, 18 ₃ are three-dimensional NR unit, the three-dimensional NR section 18, the noise extraction unit 10 ₃ and the adder 8, the 3-dimensional recursive digital filter is constructed.

[0121] noise extraction means ₁₀₃ is composed of a frame memory 19, subtractor 21 and the non-linear processing circuit 20,. Then, the output of the nonlinear processing circuit 20 is added to the coring circuit 1 of the detail processing section 15 together with the adder 8.
3 ₁ and 13 ₂ .

Therefore, the above-mentioned frame memory 19 corresponds to the delay means in the claims.

Next, the operation of the above configuration will be described.

The synchronizing means 1 calculates _ai-1 , _j , _ai , _j , _{ai + 1} , _j , _ai , _j-1 , _ai , _{j + 1 in} FIG. 2 from the input video signal. samples the pixel at the position, of the target pixel a _{i, j}
Is output to the subtractor 21 and the adder 8.

From the frame memory 19, a signal corresponding to the same pixel to be processed a _i , _j one frame before is read out and input to the subtracter 21.

The subtracter 21 subtracts the output signal of the synchronizing means 1 from the output of the frame memory 19.

As shown in FIG. 6, when the absolute value of the input level exceeds a certain value s, the output of the nonlinear processing circuit 20 becomes 0.
The noise is extracted by extracting only a low-level portion from the output of the subtracter 21.

That is, the output of the subtractor 21 indicates the amount of change in the signal before and after one frame, and includes the noise and the moving part of the input video signal. Statistically, noise is at a lower level than the signal in the moving part,
As shown in FIG. 15, noise can be extracted by extracting a signal whose level is smaller than a certain value s.

The adder 8 adds the output of the synchronization means 1 and the output of the nonlinear processing circuit 20. And this adder 8
Is output to the adder 14 of the detail processing unit 15 and also to the frame memory 19 at the same time.

The frame memory 19 delays the output of the adder 8 by one frame period.

The above processing operation can be expressed by the following equation.

V (t) = u (t) + h · {v (t−T) −u (t)} = u (t) + k (t) where k (t) = h · {v (t −T) −u (t)} where u (t) is the output of the synchronization means 1 at time t,
v (t) represents the output signal of the adder 8 at time t,
(tT) represents the output of the frame memory 19 delayed by the frame period T. H indicates the ratio between the output and the input in the nonlinear processing circuit 20 (where 0
.Ltoreq.h.ltoreq.1), which corresponds to the inclination of a straight line connecting the point P and the origin O in FIG.

In the equation, k (t) in the second term indicates the output of the non-linear processing circuit 20, and can be considered as “the inverted polarity of the noise superimposed on the input signal”.

Therefore, this k (t) is converted to the detail processing unit 1
5 to the coring circuits 13 ₁ and 13 ₂ of FIG.
The coring circuit 13 _1, 13 _2, the output k of the nonlinear processing circuit 20 (t) is added to the above equation or the output of the multiplying means 12 _1, 12 ₂ according to the equation, and as a result, the embodiment 1, Similarly to 2, a spatially high frequency component is extracted.

As described above, in the third embodiment, the noise extraction accuracy is higher than that of the two-dimensional NR, so that a higher effect can be obtained. In particular, when the input video signal is a still image, all the outputs of the non-linear processing circuit 20 become noise, so that the noise reduction effect of the coring circuits 13 ₁ and 13 ₂ is further enhanced.

In the third embodiment, the delay time of the frame memory 19 is described as one frame period, but may be one field period or one line period.

In each of the first to third embodiments,
The processing in the coring circuits 13 ₁ and 13 ₂ is not limited to the expression and the expression, and the shape of the signal block is not limited to that shown in FIG. The input / output characteristics of the numerical value generating means 9 are not limited to those shown in FIG.

[0138]

According to the present invention, the following effects can be obtained.

(1) According to the first aspect of the present invention, the coring process according to the noise level can be realized by using the noise information extracted in the noise extraction unit process for the coring process, and the contrast is large. Edge noise can also be effectively reduced.

(2) In particular, according to the third aspect of the present invention, in addition to the above effects, the circuit scale of the dividing means in the noise extraction processing section can be significantly reduced.

(3) Further, according to the fifth aspect of the invention, since the noise extraction accuracy is further improved, the effect of the first aspect is further enhanced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a video signal processing device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing signal waveforms at various parts in FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of a video signal processing device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing an example of an input / output relationship of a numerical value generating means of the apparatus of FIG.

FIG. 5 is a block diagram showing a configuration of a video signal processing device according to a third embodiment of the present invention.

FIG. 6 is a characteristic diagram showing input / output characteristics of a nonlinear processing circuit of the device of FIG. 5;

FIG. 7 is a schematic diagram illustrating an example of a signal block formed by the synchronization unit;

FIG. 8 is a block diagram showing a configuration of a conventional two-dimensional adaptive filter.

FIG. 9 is a block diagram showing a specific configuration example of a synchronization unit of the apparatus of FIG. 8;

FIG. 10 is a schematic diagram for explaining the operation of a two-dimensional adaptive average filter.

FIG. 11 is a block diagram showing a configuration of a conventional detail enhancement circuit.

FIG. 12 is a block diagram showing a configuration example of an HPF in FIG. 11;

FIG. 13 is a characteristic diagram showing characteristics of the coring processing circuit in FIG. 11;

FIG. 14 is a waveform chart showing signal waveforms of various parts of the coring processing circuit of FIG. 13;

FIG. 15 is a block diagram illustrating an example of an integrated configuration of a noise extraction unit process and a coring process;

[Explanation of symbols]

1 ... synchronizing means (signal block formation means), 2 ₁ to 2 _n ... subtractor, 3 ₁ to 3 _n ... correlation detector (comparator), 4 ... counting means,
5 ... selection means, 6 ... adder, 7 ... division means, 8 ... adder
(First adding means), 9 ... numerical value generating means, 10 ₁ , 10 ₂ ,
10 ₃ ... noise extraction means, 11 ₁ , 11 ₂ ... HPF (frequency component extraction means), 13 ₁ , 13 ₂ ... coring circuit (second addition means), 14 ... adder (third addition means), 15 Detail processing unit, 18 ₁ , 18 ₂ Two-dimensional NR unit, 18 ₃
... 3D NR section.

Claims (5)

[Claims] 1. A signal block forming means for forming a signal block comprising output signals of a plurality of pixels from an input video signal, and a noise extracting a noise component based on an output signal of each pixel of the signal block forming means. Extraction means; first addition means for adding the output of the noise extraction means to the input video signal to attenuate noise; frequency component extraction for extracting a high spatial frequency component from the input video signal Means, a second adding means for adding an output of the noise extracting means to an output of the frequency component extracting means to attenuate noise, an output of the first adding means and an output of the second adding means. And a third adding means for obtaining a detail-enhanced output by adding... To the video signal processing device. 2. The video signal processing apparatus according to claim 1, wherein the noise extracting unit includes a value of a pixel at a specific position of the signal block formed by the signal block forming unit and a pixel other than the pixel at the specific position. Subtraction means for taking a difference from the pixel value of the comparator; a comparator for comparing the output of the subtraction means with a predetermined level to output a signal indicating a comparison result; Counting means for counting the number of signals indicating a comparison result smaller than the level and outputting a signal specifying the result of counting and a pixel outputting a value smaller than the predetermined level; and counting the output from the subtracting means. Selecting means for selecting and outputting only the signal of the pixel specified by the output of the adding means; adding means for adding each output of the selecting means; and outputting the output of the adding means to the output of the counting means. A video signal processing apparatus characterized by being composed of a dividing means for dividing to. 3. The video signal processing apparatus according to claim 2, further comprising: a numerical value generating means for generating a predetermined numerical value in accordance with a count result output from said counting means, and wherein said dividing means outputs an output of said adding means. A video signal processing device for dividing by an output from a numerical value generating means. 4. The video signal processing device according to claim 3, wherein said numerical value generating means is configured to, when the input / output characteristic is such that the value of the input signal is not a power of two, change the value of the input signal. A video signal processing device for outputting a maximum power of 2 not exceeding. 5. The video signal processing device according to claim 1, wherein the noise extracting unit delays the video signal by a predetermined time, and subtracts a video signal input from an output of the delay unit. And a non-linear processing means for performing non-linear processing on the output of the subtraction means, wherein the output of the first addition means is input to the delay means, and the output of the non-linear processing means is the output of the noise extraction means. A video signal processing device.