JPH11177440A - Method and system for verifying error correction, error correction device, reproducing device, recording and reproducing device, and communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To evaluate at high speed whether or not a wrong-correction has taken in the error correction by an ECC. SOLUTION: A CRC residue latch 330 latches a CRC residue with respect to a code word before error correction. Through the use of an error position and an error value calculated in the error correction arithmetic operation by an ECC at any time, the value of a CRC working register 342 is updated by exclusive OR between the residue of the error value and each error position. Evaluation arithmetic operation is progressed at high speed, in parallel with error correction. A value of a CRC working register 342 when all the error positions and the error value are specified and the value latched in the CRC residue latch 330 are compared, and when those values are identical, it is verified that the error correction has been properly conducted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction verification method and apparatus, an error correction apparatus, a reproduction apparatus, a recording / reproduction apparatus, and a communication apparatus, and more particularly to an error correction verification suitable for executing error correction on the fly. The present invention relates to a method and a device, an error correction device, a reproducing device, a recording / reproducing device, and a communication device.

[0002]

2. Description of the Related Art When reproducing user data recorded on a recording medium of a storage device, an error may occur in the reproduced user data due to various factors. When recording on a recording medium to correct the error that occurred,
Error correction code (Error Correction cod)
es (hereinafter referred to as ECC) for recording. This technique is also used to improve reliability in data transfer.

However, the number of errors that can be corrected by the ECC has a limit depending on the byte length of the ECC, and if errors exceeding the limit occur, erroneous correction occurs with a certain probability. Here, the erroneous correction is E
When an error that exceeds the correction capability of the CC occurs, the error detection is originally performed, and what should be determined to be an uncorrectable error is erroneously corrected to incorrect data other than normal data (expected value). A phenomenon.

[0004] When such erroneous correction occurs,
There is a case where reliability of data recording / reproduction of the storage device cannot be maintained only by error detection and correction by ECC. For this reason, it is becoming common to use other techniques for error detection and error correction together with ECC. For example, Japanese Patent Application Laid-Open No. 4-259968 discloses a method using a Reed-Solomon code as the ECC and using a cyclic redundancy check code (CRCC) to detect an erroneous correction. Here, the Reed-Solomon code is a non-binary BCH
(Bose-Chaudhuri-Hocquenghem) is a kind of code.

Referring to FIG. 2, a description will be given of a procedure of an arithmetic processing in verifying whether or not the error correction has been normally performed. In FIG. 2, $ user data + CRC
When the parity unit + ECC parity unit｝ is read, in step 201, the arithmetic processing is started. Step 202 and C of ECC syndrome calculation
Steps 204 of RC remainder calculation can be performed in parallel with each other. Such parallel processing includes, for example, providing an independent circuit for performing each processing,
It can be executed by using a parallel processing processor.

In step 203, the above-mentioned step 202
It is determined whether the syndrome calculated in is non-zero or not, and if the syndromes are all zero, it is determined that there is no error (step 205). In this case, no correction operation is performed.
That is, it is determined that normal data has been read.

On the other hand, if it is determined in step 203 that at least one syndrome is non-zero, it is determined that one or more errors have occurred somewhere in the read {user data + CRC parity section + ECC parity section}. Judgment is made, and an error correction operation whose procedure will be described below is started.

In the error correction operation, first, at step 20
An error position polynomial and an error evaluation polynomial are derived from the syndrome calculated in step 2 (step 206).
Then, an error position is calculated by solving the derived error position polynomial, and an error value is calculated based on the calculated error position and the error evaluation polynomial derived in step 206 (step 207). However, the flowchart shown in FIG. 2 illustrates an example of the error correction operation algorithm, and includes a step 206 for deriving an error position polynomial and an error evaluation polynomial derivation, and a step 207 for calculating an error position and an error value. An error correction operation algorithm executed in the step and calculating the error position and the error value without explicitly calculating the error evaluation polynomial may be adopted.

Although not shown here, when the degree of the derived error position polynomial is not equal to the number of found error positions, it is determined that error correction by ECC has failed. That is, it is determined that an uncorrectable error has occurred.

When the calculated error position is one of the user data portion and the CRC parity portion, the corresponding error data among the data stored in the buffer is corrected using the error position and the error value. (Step 208). In parallel with this, the CRC remainder is recalculated using the calculated error position and error value (step 209). The method of recalculating the CRC remainder will be described later.

In step 210, step 209
Is compared with the CRC remainder result calculated in step 204. Based on the comparison result, it is determined whether the correction by the ECC has been successful (step 211). That is, as a result of the comparison, if they match, it is determined that the correction has succeeded, and if they do not match, it is determined that erroneous correction by ECC has occurred.

In recent years, in addition to the above-described reliability of data transfer, a storage device is required to have a large storage data capacity and a high speed of recording and reproduction. In order to increase the capacity of the storage data, the density of the storage data has been increased. One of the measures to support the increase in the density is to improve the performance of an ECC error correction function. That is, the error whose occurrence rate is increased by the high density is to be corrected by the high performance ECC. However, when an ECC having an improved error correction function (in which the number of correctable errors is increased) is mounted, the time required for correction generally tends to increase.

On the other hand, as data recording / reproducing speeds up,
The transfer time per sector is also relatively short. Therefore, the time allowed for the error correction operation is reduced. That is, the correction operation by the ECC and the evaluation operation for evaluating the correction result by the error detection means are completed by the time the transfer of the block (sector) next to the block (sector) in which the error has occurred is completed. It is required to be executed as Otherwise, when an error occurs in a continuous block, the above operation for each block cannot be performed in time, and as a result, a retry of reading data from the medium at the time of data reproduction (ie,
This causes rotation delay time), delays data transfer, and gives data transfer an overhead due to error correction calculations.

In order to speed up the correction operation by the ECC and the evaluation operation for the correction result and realize the on-the-fly correction, it is conceivable that these two operations are performed in parallel and the operation time is apparently shortened.

By the way, in order to execute an evaluation operation on the correction result of the correction by the ECC, for example, an operation of performing error detection using the CRCC, at least the error position and error value calculated by the error correction by the ECC and the code The word {received data before correction + CRCC parity part} and the CRC remainder result are required.
That is, in order to recalculate the CRC remainder from the error position and the error value, it is necessary that the error position and the error value necessary for this calculation process have been determined. Therefore, in order to perform the calculation of the error position and the error value and the recalculation of the CRC remainder in parallel,
The error position and the order of determining the error values must be consistent.

However, in a Chien search algorithm often used as an algorithm for calculating an error position and an error value, generally, a read code word {user data + CRCC parity section + ECC parity section} end is generally used. The error position and error value are determined in order from.

On the other hand, in general recalculation of the CRC remainder,
The calculation is performed in order from the beginning of the codeword (that is, in ascending order). If the calculated position is not an error position, '0'
If the position is an error position, a CRC operation needs to be performed using an error value corresponding to the error position.

Therefore, it is necessary to determine the error position and the error value by the chain search before the CRC.
Cannot start recalculation. Therefore, there is a problem that it is difficult to execute the calculation by the Chien search and the CRC recalculation in parallel.

Some of the techniques devised to solve such a problem will be described below.

For example, US Pat. No. 5,157,157 discloses a technique in which the CRC calculation algorithm is changed and the calculation is performed sequentially from the end of the read codeword (that is, in descending order).
No. 669. If this method is applied, the error position, the error position, and the error value are both calculated (Cheng search) and the CRC residue is recalculated.
The order of determining values can be matched, and these operations can be performed in parallel.

A method of reversing the order in which error positions are specified in the chain search is disclosed in, for example, Japanese Patent Laid-Open No. 5-268.
No. 101 proposes this. By applying this method, the error position and the error value can be calculated by both the calculation for calculating the error position and the error value and the recalculation of the CRC remainder.
The order of determining values can be matched, and these operations can be performed in parallel.

[0022]

However, in the above-mentioned method, the error position and the error value are in ascending order (the order from the beginning to the end of the code word, that is, the order in which the number indicating the position monotonically increases) or Can be applied only to a method (for example, a method such as Chien search) that is determined in descending order (an order from the tail after the code toward the head, that is, an order in which the number indicating the position is monotonically decreasing). . If an algorithm that determines error positions and values in an order that is neither ascending order nor descending order is adopted in the error position and value calculation method, the CRC calculation cannot be performed until all error positions and values are obtained. There is a problem that. As an algorithm in which the order in which the error position and the error value are determined is neither an ascending order nor a descending order, that is, an algorithm that is not a monotonous order (an order in which the number indicating the position monotonically changes), for example, the error position polynomial is used as an equation An algorithm that can be solved is conceivable.

In the verification of error correction, it is expected that a calculation for obtaining a remainder obtained by dividing an error polynomial by an error detection code generation polynomial frequently occurs. For this reason, it is considered that there is a need for a modular arithmetic device that can execute modular arithmetic at high speed.

Further, it is considered that the on-the-fly correction is required not only for reading from a storage medium but also for a receiving operation in a communication device, for example.

It is a first object of the present invention to provide an error correction verification method and apparatus and an error correction apparatus capable of executing an error correction result evaluation operation irrespective of the order in which error positions and error values are determined. The purpose of.

In addition, in such error correction verification, a second aspect of the present invention is to provide a remainder operation device capable of executing a remainder operation performed for an error polynomial for the remainder operation by an error detection code generation polynomial at a high speed. The purpose of.

Further, a reproducing apparatus, a recording / reproducing apparatus, and the like having a function of performing such an error correction evaluation operation.
A third object is to provide a communication device.

[0028]

According to a first aspect of the present invention, there is provided a sequence in which an error detection code is added to user data representing target information. When the error included in the code word to which the error correction code is added is corrected using the error correction code, the error correction verification device for verifying whether an error correction has occurred. A remainder obtained by dividing the code word by an error detection code generation polynomial that generates a code, and an interfacing unit for receiving an error position and an error value of each error included in the code sequence; and Each error obtained by dividing the error polynomial generated from the error position and the error value of the error polynomial by the error detection code generation polynomial for generating the error detection code is calculated. A sum calculating means for calculating an exclusive OR of all the remainders, and comparing the sum obtained by the adding means with the received remainder. There is provided an erroneous correction verification device characterized by having a determination means for determining that a correction has occurred and determining, when they match, that no erroneous correction has occurred.

According to the second aspect of the present invention, user data representing target information, an error detection code generated from the user data by an error detection code generation polynomial, the information code and the error detection code are used. An error correction apparatus for correcting an error included in a code word including an error correction code generated by an error correction code generation polynomial from a sequence including the error detection code, and detecting whether the error is included using the error detection code. An error detection unit for performing error correction by using the error correction code when the error detection unit detects that an error is included, and an error correction unit that performs error correction by using the error correction code. An error correction verifying unit for verifying whether or not an error correction has occurred. A remainder calculating means for obtaining a remainder divided by the error detection code generation polynomial; and a notifying means that the error is included in the error correcting unit when the remainder calculated by the remainder calculating means is non-zero. Notification means, and the error correction unit, the error correction operation means for obtaining the error position and error value of each error included in the series including the user data and the error detection code, and, in the series, Correcting means for converting the byte data at the obtained error position into byte data obtained by performing an exclusive OR operation on the byte data and the obtained error value; An error correction device characterized by being configured using the error correction verification device according to the aspect is provided.

According to the third aspect of the present invention, an error contained in a code word obtained by further adding an error correction code to a sequence obtained by adding an error detection code to user data representing target information is corrected. An error correcting device for detecting whether or not the code word contains an error, and detecting an error in the code word when the detecting unit detects that the code word contains an error. A correction unit for performing a correction operation for correcting a codeword error using a code, and a correction result evaluation unit for evaluating a correction result of the error correction in the correction unit, wherein the correction unit includes a code An arithmetic circuit for determining an error position and an error value of an error included in the word, performing a correction operation for correcting an error of the code word using the determined error position and the error value, and A reporting circuit for reporting an error position and an error value of one or a plurality of errors to the correction result evaluation unit each time an error is calculated, wherein the correction result evaluation unit receives the received error position. And an evaluation circuit for advancing the evaluation of the correction result using the error value and the correction unit and the correction result evaluation unit,
An error correction device is provided, wherein the correction operation in the correction unit and the evaluation of the correction result in the correction result evaluation unit are performed in parallel.

According to the fourth aspect of the present invention, an information code representing information, an error detection code generated from the information code by a cyclic redundancy code generation polynomial, and a sequence including the information code and the error detection code are used. For error correction using the above error correction code for a code word including an error correction code generated by an error correction code generation polynomial, an error correction verification method for verifying whether error correction has occurred during error correction. The remainder of the cyclic redundancy code generation polynomial for the codeword, and accepts the error position and error value of each error included in the sequence including the user data and the error detection code. The above cyclic redundancy code generation polynomial for a polynomial in which terms including error values are the highest-order terms. The remainder of the expression is calculated, the sum of the obtained remainder is calculated by exclusive OR, and the obtained sum is compared with the received remainder.If they do not match, it is determined that an erroneous correction has occurred. Otherwise, there is provided an erroneous correction verification method characterized by determining that erroneous correction has not occurred and verifying the error correction.

According to a fifth aspect of the present invention, in a recording medium storing a program, the program is the first program
And a program capable of causing the second processor to operate in parallel, wherein a sequence in which an error detection code is added to user data representing target information and a codeword in which an error correction code is further added include an error. Detecting whether or not the code word includes an error, and executing a correction operation for correcting the error of the code word using the error correction code using the first processor when the code word includes an error. A correction unit, and a correction result evaluation unit for evaluating a correction result of the error correction in the correction unit by the second processor, wherein the correction unit determines an error position and an error value of an error included in the codeword. A step of performing a correction operation for performing error correction of a codeword using the obtained error position and the obtained error value; Reporting the error position and error value of the error to the correction result evaluator each time the error is calculated, wherein the correction result evaluator has an error position and an error value of one or more errors. A recording medium storing a program, characterized by including a step of performing an operation for evaluating a correction result each time a program is given.

To achieve the second object, according to a sixth aspect of the present invention, in a residue calculating device for calculating a remainder obtained by dividing a given polynomial by a predetermined polynomial, A residue arithmetic device is provided, which includes at least a residue decoder for obtaining a residue obtained by dividing a polynomial of a predetermined order by the predetermined polynomial, for a first-order polynomial.

In order to achieve the third object, according to the seventh aspect of the present invention, information obtained by adding an error detection code to target information data (called user data) is regarded as one data. In a reproducing apparatus for a recording medium in which data obtained by adding an error correction code to the data is recorded,
Reading means for reproducing data from the recording medium in accordance with a command from the host, buffer means for temporarily storing data reproduced from the recording medium, and an error occurring in the data reproduced from the recording medium. Detecting means for detecting, when an error is detected by the detecting means, correcting means for correcting an error of the reproduced data by using an error correction code included in the data, and correcting by the correcting means A correction result evaluation unit for evaluating the result; and an output unit for outputting the information data corrected by the correction unit to the outside, wherein the correction code has an error (error) at a plurality of locations of the data. If it is included, as soon as a part of all errors and the corresponding error value are calculated in the correction operation process, the error And a means for reporting an error value to the correction result evaluation means as needed, wherein the correction result evaluation means uses the received error position and error value to immediately advance the correction result evaluation of the correction means. And a means for executing the correction means and the correction result evaluation means in parallel is provided.

In particular, the correction result evaluation means includes means for advancing the correction result evaluation irrespective of the relationship between the order of error positions to be received and the order of positions on the error correction code.

The correction result evaluation means includes, for example, a means for generating an error polynomial from the received error position and error value, and performing a remainder operation using a detection code generation polynomial using the error polynomial. Means for temporarily storing the data, and when a plurality of error positions and error values are received, the same operation is performed, and the stored value is updated by performing an exclusive OR operation with the stored value. Means, applying the operation to all error positions and error values, and finally calculated results,
Means for comparing the result of the remainder calculation by the detection code generation polynomial using the received word including the error, and means for determining whether the error has been properly corrected by the error correction means based on the result. Implemented in the device.

Further, a plurality of the above means for performing a remainder operation using a detection code generation polynomial using the error polynomial are provided, and when one of the means is in operation, an error position and error value output request is received from the correction means. Then, the other operation may be performed to perform the correction result evaluation operation at a high speed.

Also, two or more independent error detection codes are provided as the error detection code, and two or more independent correction result evaluation means for evaluating the correction result of the correction means using the detection code are provided. You can also.

The error correction code has an interleave structure, the correction means includes means for performing a correction operation for each interleave, and the correction result evaluation means includes an error position, an error position, and an error calculated for each interleave. It is also possible to adopt a configuration including means for receiving the value and recalculating the error position from the error position to the error position as seen by the error detection code.

According to an eighth aspect of the present invention, there is provided a recording / reproducing apparatus including the reproducing apparatus according to the seventh aspect.

According to a ninth aspect of the present invention, there is provided a communication apparatus for correcting an error contained in data received by communication using the error correction apparatus according to any one of the second and third aspects. Is done.

[0042]

Embodiments of the present invention will be described below with reference to the drawings.

First, a first embodiment of the present invention will be described. In the present embodiment, a magnetic disk device capable of executing an error correction method to which the present invention is applied when reproducing data from a magnetic disk as a recording medium will be described. Hereinafter, the configuration of the magnetic disk device, the recording operation of the user data, and the reproducing operation will be sequentially described.

First, the configuration of the magnetic disk drive will be described. The magnetic disk device has a mechanism for recording and reproducing signals using a magnetic disk as a recording medium, and an electronic circuit for processing signals recorded and reproduced by the mechanism.

Referring to FIG. 11, the mechanism of the magnetic disk drive will be described. 11, a magnetic disk device 1680 includes a magnetic disk 810 as a recording medium for recording a signal describing data, a spindle motor 1682 for rotating the magnetic disk 810, and a magnetic disk 810. A head 811 for reading / writing a signal to / from the
An arm 1683 for supporting the head 811;
A voice coil motor 1653 for driving the arm 1683 to move the head 811;
Amplifying the signal read from the
1 for driving and recording a signal.

Next, an electronic circuit section of the magnetic disk drive will be described with reference to FIG. In FIG. 3, a magnetic disk device 1681 is provided with a host interface 826 for connecting to an information processing device such as a host computer.
, A hard disk controller 817 for controlling data transfer and format, etc., the head 811 (see FIG. 11) and a magnetic disk 81.
0 (see FIG. 11), a servo control circuit 814 for controlling the relative positional relationship, and a read / write control circuit 812.
It has a signal processing circuit 813 for processing signals from (see FIG. 11), a data buffer 816 for temporarily storing data, and a CPU (central processing unit) 815 for controlling these. Is done.

The CPU 815 is mainly composed of the HDC 817
And the servo control of the magnetic disk 810 via the servo control circuit 814 is performed.

The servo control circuit section 814 includes a spindle control circuit 1685 for controlling the spindle motor 1682 (see FIG. 11) and a voice coil motor 165.
3 (see FIG. 11). Servo control circuit section 814
Performs bidirectional transmission and reception of signals with the CPU 815,
The rotation control of the magnetic disk 810 using the spindle control circuit 1685 and the voice coil motor control circuit 16
The position of the head 811 using the position control 54 is executed in accordance with a command from the CPU 815.

Next, with reference to FIG. 4, an outline of a recording operation and a reproducing operation of user data in the magnetic disk device will be described focusing on an HDC (hard disk controller).

First, the configuration of the HDC 817 will be described. The HDC 817 is a part for generally controlling recording and reproduction of user data on the magnetic disk 810. The HDC 817 can be formed of, for example, one integrated circuit (IC) as shown in FIG.
The HDC 817 includes a buffer control unit 818, a CPU input / output control unit 819, a drive control unit 290, and a host interface control unit 825.

The CPU input / output control unit 819 includes a CPU
815 and the HDC 817 for interfacing with the CPU 815 via a signal line 836.
To the host interface control unit 825 via the signal line 832 and the buffer control unit 818 via the signal line 831.
And a drive control unit 290 via a signal line 864.

The buffer controller 833 sends the data to the host interface controller 825 via the data bus 833.
It is connected to a data buffer 816 via a data bus 827 and to a drive control unit 290 via a data bus 828, respectively. In addition, the drive control unit 290
It is connected to a signal processing circuit 813 via a data line 829.

The drive control circuit 290 has a CRCC
For performing the CRC operation and the operation for generating the
An RC circuit 260 and an EC for performing an operation for generating an ECC and an operation for correcting an error using the ECC.
It comprises a C circuit 262 and a verification circuit 261 for verifying error correction.

In addition to the connection of the drive control circuit 290 and the buffer control circuit 818 by the data buffer 828, the ECC circuit 262 is connected to the buffer control unit 818 via a signal line 828.

Next, a recording operation for recording user data given from the host will be described with reference to FIG.

The user data sent via the host interface 826 is sent to the host interface controller 82
5, transmitted to the data buffer 816 via the data bus 833, the buffer control unit 818, and the data bus 827. The user data transmitted to the data buffer 816 is further transmitted to the data bus 827 and the buffer control unit 81.
8, transmitted to the drive control unit 290 via the data bus 828.

The drive control section 290 adds an CRC parity section to the user data from the CRC circuit 2610 and performs error detection encoding.
The ECC parity part is further added by the CC circuit 830, and the code word {user data + CRC parity part + EC
A C parity part｝ is generated. This code word {user data + CRC parity section + ECC parity section} is transmitted to the signal processing circuit 813 via the data bus 829 and encoded. Then, the encoded recording signal is
The data is recorded on the magnetic disk 810 by the read / write control circuit 812 under the control of the drive control unit 290. In this way, the recording operation for recording the user data on the magnetic disk 810 is performed.

Further, referring to FIG. 4, a reproducing operation for reproducing data recorded on the magnetic disk will be described.

Under the control of the drive control unit 820, a recording signal recorded on the magnetic disk 810 is transmitted to the signal control circuit 813 via the magnetic head 811 and the read / write control circuit 812, and the code word {user data + CRC parity part + ECC parity part}. The decoded codeword {user data + CRC parity unit + ECC parity unit} is transmitted to the drive control unit 290 via the data bus 829.
The drive control unit 290 transmits the codeword {user data + CRC parity unit} excluding the ECC parity unit ECC parity unit to the data buffer 816 via the data bus 828, the buffer control unit 818, and the data bus 827, and The circuit 262 is controlled to detect an error included in the code word {user data + CRC parity section + ECC parity section}. At the same time, it controls the CRC circuit 260 to calculate the CRC remainder of the codeword {user data + CRC parity part}. This CRC remainder is
Used later to detect ECC miscorrections.

When an error is detected by the ECC circuit 262, error correction processing is continuously performed, and the data buffer 816 is determined based on the calculated error position and error value.
{User data + CRC parity part}
Of the corresponding error data.

When the error correction processing is completed by the ECC circuit 262, the error correction result is verified by the verification circuit 261 based on the calculated CRC remainder (before error correction), the error position and the error value. You. This verification determines whether the ECC circuit 262 has made an erroneous correction. If the correction in the ECC circuit 262 is successful and the erroneous correction of the ECC circuit 262 is not detected in the verification circuit 262, it is determined that the correction is successful.

ECC circuit 262 and CRC circuit 260
When the user data is compensated for by the
Only the user data out of the {user data + CRC parity unit} temporarily stored in 16 is sent to the host interface control unit 825 via the data bus 827, the buffer control unit 818, and the data bus 833. The host receives user data from the host interface control unit 825 via the host interface 826. Thus, the reproducing operation for reproducing the user data from the magnetic disk 810 is performed.

Next, the details of the drive control section 290 will be described. First, the nature of the CRC, the general theory of the evaluation operation of the error correction result, and the operation theory of the evaluation operation to which the present invention is applied are sequentially described. Further, the drive control unit 290 of the present embodiment to which this operation theory is applied is described. Details of the configuration and operation will be described.

First, error detection by CRC will be described.

User data (for example, when data is recorded, data sent from the host side is expressed in a polynomial form as shown in (Equation 1).

[0066]

(Equation 1)

In (Equation 1), d _x indicates the x-th 8-bit pattern (ie, symbol value) counted for each byte of the user data.

Here, assuming that the CRC generating polynomial is G _CRC (x), the code W (x) generated from D (x) is shown as (Equation 2).

[0069]

(Equation 2)

Here, R is a CRC redundancy number. For example, R = 32 for a 4-byte CRC.

This code W (x) is always divisible by G _CRC (x). An ECC byte is added to this code W (x) and used as a recording code for recording on a medium. Now, an error occurs when reading out the code W (x) (in this case, {user data + CRC parity part in particular}) and the corresponding ECC parity part from the medium, and the original code W (x) is If different codes M (x) are reproduced, they have the relationship of (Equation 3).

[0072]

(Equation 3)

In (Equation 3), E (x) is an error polynomial, and this error polynomial E (x) can be expressed as (Equation 4).

[0074]

(Equation 4)

[0075] Here, e _x indicates an error value, also, j _x shows the corresponding error location. l is the number of error bytes generated in the user data and CRC byte portions.

The error detection by CRC at the time of reading data from the code M (x) (reproduced received word) represented by (Equation 4) can be executed according to (Equation 5). However, the detection here is not an error correction check of ECC but an error detection of data before ECC correction.

[0077]

(Equation 5)

(Equation 5) shows that the result of the remainder operation on the code M (x) depends only on the error polynomial E (x). The error polynomial E (x) is determined from an error position and an error value. Since it is determined that an error detected when S is not equal to zero, CRC errors detected can be achieved by long as x ^R E (x) is not divisible by G _CRC (x). Because
If there is no error in the code M (x), that is, E
This is because if (x) = 0, then M (x) = W (x) holds and must be divisible by G _CRC (x).

Therefore, erroneous correction verification after ECC correction can be realized by utilizing this property. Hereinafter, the erroneous correction verification will be described.

The error position occurring in the data part or CRC parity part and the corresponding error value are determined by ECC
It can be calculated by correcting. Unless incorrectly corrected, these error locations and values are
Respectively corresponding to the e _x and j _x in Equation (4). Of course, the user data part and CRC calculated by ECC correction
The number of errors that occurred in the part should be equal to l in (Equation 4).

E ′ (x) expressed as a polynomial is generated using an error position and an error value obtained by ECC correction. E ′ (x) can be expressed as (Equation 6).

[0082]

(Equation 6)

Here, e _x ′ and j _x ′ are ECC
The error value and the error position calculated by the calculation are shown. Also, l ′ indicates the number of errors generated in the user data part and the CRC parity part calculated by the ECC operation.

Using this E ′ (x), the remainder calculation is executed in the same manner as in (Equation 5), and if the result is equal to the result of (Equation 5), the ECC correction is performed normally and the CRC to decide. That is, if S ′ can be expressed by (Equation 7) and S = S ′, then E
Indicates that the erroneous correction of CC was not detected by CRC.

[0085]

(Equation 7)

As described above, the detection of the ECC error correction by the CRC is performed by detecting the error position and error value calculated by the ECC operation, the CRC remainder calculation result from the read {user data + CRC parity part} (before ECC correction). It is feasible if there is one.

Next, an evaluation operation to which the present invention is applied will be described.

The expression (7) derived as described above can be modified as shown in the expression (8) when attention is paid to the polynomial expression.

[0089]

(Equation 8)

In (Equation 8), the operator “+” indicates exclusive OR. The following theory is derived from (Equation 7) and (Equation 8). That is, for each term of the error polynomial E ′ (x) including the error position and the error value calculated by the ECC circuit, the calculation of (Equation 7) is applied independently. Then, a result value S ′ can be obtained by performing an exclusive OR operation on the operation results in the respective terms.

The verification circuit 261 of this embodiment utilizes this theory. That is, in the verification circuit 261, the error position and the error value are stored in the ECC circuit 26.
2, the calculation of each term in (Equation 8) can be executed independently for each term at any time, and the value S ′ to be finally obtained is updated according to the result obtained for each term. To go. Therefore, the verification operation can be executed in parallel for each term, and the speed of the verification can be increased, and the time required for the error correction verification can be reduced.

Next, with reference to FIG. 5, the operation of the drive control unit 290 in the present embodiment, to which the above-described arithmetic theory is applied, will be described in detail.

In FIG. 5, the drive control unit 290
CRC circuit 260, verification circuit 261, ECC circuit 2
62. The configuration and operation of each block will be described later. Here, an outline of the operation of these three blocks will be described focusing on the transmission and reception of data between the blocks, separately for the case of writing and reading of user data to and from a storage medium (the magnetic disk 810 in FIG. 4).

First, writing of user data to the magnetic disk 810 will be described. This writing operation is basically performed in the same manner as the operation conventionally used.

First, user data to be written to the data bus 258 of the drive control unit 290 is sent in 8-bit units via the data buffer 816 (see FIG. 4) and the buffer control unit 818 (see FIG. 4). . The drive control unit 290 transmits the user data to the CRC circuit 260,
And to the ECC circuit 262. Therefore, at this time, the selector 264 selects the data bus 258 and outputs data from the data bus 258 to the bus 253.

Until all user data is transferred to the above two blocks (CRC circuit 260 and ECC circuit 262), each block operates as follows.
That is, the CRC circuit 260 recognizes the transferred user data as a polynomial, performs a remainder operation using a CRC generation polynomial (see (Equation 2)), and
2 recognizes the transferred user data as a polynomial,
A remainder operation is performed using an ECC generating polynomial. The ECC circuit 262 outputs the user data transferred in parallel from the codeword output bus 255 in 8-bit units.

When all the user data has been transferred to the two blocks (CRC circuit 260 and ECC circuit 262), each block operates as follows. That is, since a CRC parity section (4 bytes in the present embodiment) is generated in the CRC circuit 260, the CRC parity section is transferred to the ECC circuit 262 via the data bus 257 in 8-bit units. That is, during this period, the selector 264 selects the data bus 257 and outputs data from the data bus 257 to the data bus 253.

The ECC circuit 262 continuously performs the remainder operation by the ECC generating polynomial using the CRC parity part transferred via the data bus 257 following all the user data bytes. In addition, the ECC circuit 262 outputs the transferred CRC parity unit from the codeword output bus 255 in 8-bit units in parallel.

When all of the CRC parity section (4 bytes in this embodiment) is transferred to the ECC circuit 262,
Since the ECC parity part is generated inside the C circuit 262, the 8
The ECC parity unit is output bit by bit.

As described above, in the drive control unit 290 to which the present embodiment is applied, by inputting user data via the data bus 258, the code word {user data portion + CRC parity portion + ECC parity portion} Are sequentially output from the codeword output bus 255. With such an operation, the drive control unit 290 to which the present invention is applied can determine the code word {user data unit + CR
C parity unit + ECC parity unit｝
9 (see FIG. 4) through the magnetic disk 810 (FIG. 4).
Record).

Next, an operation of reading user data from a storage medium (magnetic disk 810 (see FIG. 4)) in drive control section 290 in the present embodiment will be described with reference to FIG. Acquisition of the recording signal from the storage medium, decoding processing of the acquired recording signal, etc.
Although the processing is the same as the processing performed conventionally, the processing in the present embodiment is based on error correction by ECC and
It differs in the CRC of CC error correction. The following description focuses on the differences.

First, a magnetic disk 8 as a storage medium
The codeword {user data section + CRC parity section + ECC parity section} read from 10 (see FIG. 4) is input to CRC circuit 260 and ECC circuit 262 via data bus 258. That is, during this period, the selector 264 selects the data bus 258 and outputs data from the data bus 253 to the data bus 253 during this period.

The CRC circuit 260 modulates the code word {user data section + CRC parity section} by using a CRC generating polynomial to calculate a 4-byte CRC remainder. Then, the calculated CRC remainder is output to the verification circuit 261 via the data bus 256 every four bytes. Verification circuit 2
At 61, the received 4-byte CRC remainder is stored internally.

The ECC circuit 262 calculates a syndrome from {user data section + CRC parity section + ECC parity section}. If at least one of the calculated syndromes is non-zero, the ECC circuit 262 determines
Read {user data part + CRC parity part + EC}
It is determined that an error is included in the C parity section｝, and a correction operation is started. If the calculated syndromes are all zero, it is determined that no error has been included in the read {user data section + CRC parity section + ECC parity section}, and normal data transfer to the drive control section 290 has been performed. Report.

Next, the correction operation will be described.

When the ECC circuit 262 performs a correction operation using the syndrome, if the number of generated errors is within the correction capability range of the ECC, the pair of the error position and the error value is set to one.
Calculate more than pairs (for the number of errors actually occurred).

At this time, every time a pair of an error position and an error value (where the error position is a user data portion or a CRC parity portion) is found, verification is performed via a data bus 251 and a data bus 252, respectively. An error position and an error value pair are output to the circuit 261.

The verification circuit 261 performs an erroneous correction verification operation using the received error position and error value. The verification circuit 261 calculates and updates a CRC re-residue for erroneous correction verification every time it receives an error position and an error value. In the present embodiment, the number of clock cycles required for the CRC re-residue update operation using one pair of error positions and error values is reduced from several clock cycles to one.
The number has been reduced to zero clock cycles. Therefore, the speed of the update operation is increased. The detailed operation of the verification circuit 261 will be described later.

The ECC circuit 262 tries to output the error position and the error value to the verification circuit 261 every time a pair of the error position and the error value is found. Here, if the verification circuit 261 has not completed updating of the CRC re-residue using the error position and error value that have already been passed, the verification circuit 261 determines that the update has not been completed via the control line 253. , The ECC circuit 262 waits for the output of the error position and the error value until it is completed.

When the update of the CRC remainder is completed, the error position and error value are output to the verification circuit 261, and the calculation of the next error position and error value is started.

The ECC circuit 262 calculates all pairs of expected error positions and error values, and the verification circuit 261 updates the CRC re-residue using all the calculated error position and error value pairs. Is completed, the CRC stored in the verification circuit 261 is
The re-residue value should match the CRC remainder already stored in the verification circuit 261 if there is no error correction by ECC.

Therefore, the verification circuit 261 interprets that the correction by the ECC has been performed normally if the CRC remainder value is equal to the CRC remainder value. Otherwise (if the CRC re-residue value is not equal to the CRC remainder value), it is determined that erroneous correction by ECC has been performed, and the occurrence of erroneous correction is reported to the ECC circuit 262 via the bus 250.

The ECC circuit 262 uses the pair of the calculated error position and error value to generate the data bus 83.
4. The corresponding error byte data stored in the data buffer 816 (see FIG. 4) is corrected to normal data via the buffer control unit 818 (see FIG. 4). Specifically, the error byte data stored in the data buffer memory 816 is specified from the error position, and the ECC
The data is read into the circuit 262 and the exclusive OR of the error byte data and the error value is re-stored at the same position (specified from the error position) in the data buffer memory 816.

On the other hand, when the ECC circuit 262 determines that the data cannot be corrected or receives a report of the occurrence of an erroneous correction from the verification circuit 261, the ECC circuit 262 determines that the received data could not be corrected. To the control circuit that controls That is, whether the correction operation was performed by the ECC circuit 262 but the correction was unsuccessful (uncorrectable) is determined from the operation result in the ECC circuit 262, or the error correction of the ECC is detected in the verification circuit 261. When this is reported to the ECC circuit 262 via the bus 250, the ECC circuit 262
Via a non-correctable report signal 254, a control circuit (for example, CPU 815 or the like) that performs higher-level control sends a {user data + CRC parity unit +
Reports that ECC parity unit # could not be corrected. At this time, the higher-level control circuit recognizes that the read user data contains an error and cannot be corrected by the ECC circuit 262, and performs a re-read (retry) process of the user data.

As described above, according to the present embodiment, when the ECC circuit 262 calculates a pair of an error position and an error value, the value is immediately output to the verification circuit 261 and the next error position and error value are calculated. Start to calculate. The verification circuit 261 calculates the error position and error value of the ECC circuit 262 in parallel with the error correction verification operation of the ECC.
The update operation of C-remainder proceeds. So, apparently, EC
The calculation of the error position and the error value by the C circuit 262 and the ECC erroneous correction verification operation by the verification circuit 261 can be executed simultaneously.

Next, the CRC circuit 2 in the present embodiment
60, the ECC circuit 262, and the verification circuit 261 will be described in detail.

First, referring to FIG. 7, CRC circuit 260
Will be described in detail.

In FIG. 7, the CRC circuit 260 has four 8-bit delay registers (401, 402, 403, 4).
04), an error detection block 410, an 8-bit operation feedback circuit 405, and control logic (not shown) for controlling these.

Hereinafter, the operation of the CRC circuit 260 will be described separately for the operation of writing data to the storage medium and the operation of reading data.

First, the operation of the CRC circuit 260 during the operation of writing data to the storage medium will be described with reference to FIG.

First, the four 8-bit delay registers (401, 402, 403, 404) are all reset to zero by the control logic. When the user data is input from the data bus 258 in 8-bit units, the 8-bit operation feedback circuit 405
An 8-bit delay register (40) input to the 8-bit operation feedback circuit 405 via the data bus 256
, 402, 403, 404) and the user data in units of 8 bits, and calculates a feedback value via the data bus 400.
402, 403, 404) update the value. This behavior
For each of the 8-bit user data input via the data bus 258, this is performed as needed in synchronization with the clock.

Here, the 8-bit operation feedback circuit 405 uses the remainder initial value specified via the data bus 256 and the CRC generation polynomial to perform the 8th-order remainder operation (see (Expression 2)). This is a random logic configured to calculate a 32-bit result when performed in one clock.

In this manner, all the user data are stored in the CR
When the C circuit 260 receives the data via the data bus 258 and repeats the above operation, finally, a 4-byte CR is stored in an 8-bit delay register (401, 402, 403, 404).
The C remainder value (in this case, a CRC parity byte because of the generation operation) can be calculated. Then, the CRC circuit 260 outputs the calculated 4-byte CRC parity byte via the data bus 257 one by one. At this time, the 8-bit operation feedback circuit sequentially performs different operations. That is, the value of the 8-bit delay register 402 is input to the 8-bit delay register 401 at the next clock, the value of the 8-bit delay register 403 is input to the 8-bit delay register 402, and The operation is performed so that the value of the bit delay register 404 is input to the 8-bit delay register 403. By outputting the value of the 8-bit delay register 401 via the data bus 257 while repeating this operation for 4 clock cycles, the aforementioned 4-byte CRC parity byte can be output in 1-byte units.

Next, referring to FIG. 7, the CRC circuit 26 operates at the time of reading data from the storage medium.
The operation of 0 will be described.

First, four 8-bit delay registers (40
1, 402, 403, 404) are all reset to zero by the control logic. Then, from the data bus 258, {user data + CRC parity section} is set to 8
When input in bit units, the feedback value is calculated from the values of the 8-bit delay registers (401, 402, 403, 404) input to the 8-bit operation feedback circuit via the data bus 256 and the user data in 8-bit units. , 8-bit operation feedback circuit 405 calculates and updates the values of the 8-bit delay registers (401, 402, 403, 404) via the data bus 400. Synchronizing this operation with the clock, 8-bit unit {user data + CRC input through data bus 258
This is performed as needed for each of the parity units (the same processing as in the above-described writing operation to the medium).

In this way, when all the user data is received via data bus 258 and the above operation is repeated, finally, an 8-bit delay register (40
1,402,403,404) 4 byte CR
A C remainder value is calculated. Then, the CRC circuit 260
The error detection 410 detects whether the calculated remainder value has a non-zero value. If there is at least one non-zero value, it is determined that an error has occurred in the read {user data + CRC parity part}, and the calculated remainder value is sent to the verification circuit 261 via the data bus 256. Output with clock.

Next, the configuration and operation of the ECC circuit according to the present embodiment will be described in detail with reference to FIG. The details of the operation of the ECC circuit 262 will be described separately for the operation of writing data to a recording medium and the operation of reading data.

In FIG. 6, the ECC circuit 262
A code generation / syndrome calculation circuit 301 for performing a calculation for generating a C parity byte and a calculation for calculating a syndrome; an error position and a value calculator 302 for obtaining an error position and an error value of an error that has occurred; The circuit includes a circuit 305, an uncorrectable determination circuit 307, and control logic (not shown) for controlling these circuits.

First, the operation of the ECC circuit 262 during the operation of writing data to the storage medium will be described with reference to FIG.

When {user data + CRC parity section} is input in 8-bit units via data bus 253, code generation / syndrome calculation circuit 301 functions as a code generation circuit. That is, the code generation / syndrome calculation circuit 301 receives the input {user data + C
Residue operation by ECC generation polynomial is performed on RC parity section｝. Further, in parallel with the remainder operation, the input {user data + CR
C parity part｝ is output in 8-bit units. as a result,
E is stored in the internal register of the code generation / syndrome calculation circuit.
The remainder for the same number of bytes as the degree of the CC generator polynomial is stored. This is the ECC parity byte (ECC parity part) calculated for {user data + CRC parity part}. Then, the calculated ECC parity byte is added to {user data + CRC parity part},
The data is output in 8-bit units via the data bus 255.

In this way, from the input {user data + CRC parity section}, the corresponding ECC parity section is calculated and {user data + CRC parity section + ECC parity section} is output via data bus 255. Can be.

Next, referring to FIG. 6, ECC circuit 262 at the time of reading data from the storage medium is performed.
Will be described.

When {user data + CRC parity section + ECC parity section} is input in 8-bit units via the data bus 253, the code generation / syndrome calculation circuit 301 functions as a syndrome calculation circuit. That is, the code generation / syndrome calculation circuit 301 performs a syndrome calculation operation on the input {user data + CRC parity unit + ECC parity unit}, and calculates the calculated syndrome via the data bus 303 as an error position and value calculation. Output to the container 302. The error position / value calculator 302 derives an error position polynomial and an error evaluation polynomial based on the received syndrome using the Euclidean algorithm. Further, an error position and an error value corresponding thereto are calculated by solving an error position polynomial and an error evaluation polynomial. If a plurality of errors have occurred and the number of errors is within the number that can be corrected, pairs of error positions and error values should be calculated for the number of errors.

Here, as a method of solving the error position polynomial, for example, a Chien search algorithm can be used. However, the present invention does not depend on the method of solving the error position polynomial. May be calculated in any order.

Each time an error position and a corresponding error value pair are calculated as described above, the error position / value calculator 302 checks the data bus if the error position is a user data portion or a CRC parity portion. The error position is output to the buffer interface circuit 305 via the data bus 252 and the error position via the data bus 252, and is also output to the verification circuit 261 (see FIG. 5). However, at this time, the value of the control line 253 is checked, and if the verification circuit 261 indicates a busy state,
Until 3 indicates an idle state, it waits without outputting. However, since the verification circuit 261 (see FIG. 5) executes the calculation for each error position and error value at high speed, the overhead due to the above-described wait operation is small.

When the output of the error position and the error value to the buffer interface circuit 305 and the verification circuit 261 is completed, the error position and the value calculator 302 continues to calculate the next error position and the error value. The same process is repeated until all error positions and error values are calculated.

When receiving the error position and error value, the buffer interface circuit 305 utilizes the buffer control unit 818 (see FIG. 4) via the data bus 834 to store the error in the data buffer 816 (see FIG. 4). Correct the byte data to normal data. Specifically, the error byte data stored in the data buffer memory 816 is identified from the error position, read into the buffer interface circuit 305, and the byte data obtained by taking the exclusive OR of the error byte data and the error value is obtained. Also, the data is re-stored at the same position (specified from the error position) in the data buffer memory 816.

On the other hand, when the expected number of error positions and error values cannot be specified in the error position / value calculator 302, the error position / value calculator 302 determines that an error exceeding the correctable range has occurred. And control line 310
The occurrence of an uncorrectable error is reported to the uncorrectable determination circuit 307 via the. The verification circuit 261 (FIG. 5)
If an error correction of ECC is detected in
The fact that erroneous correction has occurred is reported to the uncorrectable determination circuit 307 via 50.

In the uncorrectable determination circuit 307, the ECC circuit 262 outputs {user data + CRC parity part + EC
When the correction operation for the C parity unit｝ is completed, it is checked whether an error position has been reported from the value calculator 302 as to whether correction has not been possible, and whether there has been a report from the verification circuit 261 that an erroneous correction has occurred. If there is any one of them, the uncorrectable determination circuit 307 calculates {user data + CR
An error occurs in the C parity section + ECC parity section｝,
Further, it is determined that the error was uncorrectable, and the control line 254
The occurrence of an uncorrectable error is reported to the upper-level drive control unit 261 via the.

Next, the configuration and operation of the verification circuit according to the present embodiment will be described in detail with reference to FIG.

In FIG. 1, the verification circuit 261 has a CRC
A remainder latch 330, a remainder storage register 334, a comparator 331, an error value remainder encoder 341;
It has a working register 342, a [16] cycle remainder decoder 343, a [1] cycle remainder decoder 344, a remainder decoder selector 348, a selector 335, a selector 340, a selector 345, and control logic (not shown). It is composed.

For example, the CRCC generator polynomial is expressed as x ^ 32 + x ^ 2
6 + x ^ 23 + x ^ 22 + x ^ 16 + x ^ 12 + x ^ 11 + x ^ 10 + x ^ 8 + x ^ 7 + x ^ 5 + x ^ 4 + x ^
When 2 + x + 1 is set, [16] cycle remainder decoder 34
3 can be easily realized by hardware that executes the following calculation.

Here, [16] cycle remainder decoder 343
And the value of the 32-bit output data bus of the [16] cycle remainder decoder 343 is out1 [31: 0]. In the following expression, “∪” represents an exclusive OR of bits, and can be easily calculated by a combination circuit using an XOR circuit as hardware.

Out1 [31] = d1 [31] ∪d1 [30] ∪d1 [29] ∪d1 [28] ∪d1 [26] ∪d1 [22] ∪d1 [21] ∪d1 [20] ∪d1 [ 19] ∪d1 [17] ∪d1 [16] ∪d1 [14] ∪d1 [13] ∪d1 [9] ∪d1 [7] ∪d1 [6] ∪d1 [4] ∪d1 [2] ∪d1 [ 1] ∪d1 [0] ∪1 out1 [30] = d1 [30] ∪d1 [29] ∪d1 [28] ∪d1 [27] ∪d1 [25] ∪d1 [21] ∪d1 [20] ∪d1 [19] ∪d1 [18] ∪d1 [16] ∪d1 [15] ∪d1 [13] ∪d1 [12] ∪d1 [8] ∪d1 [6] ∪d1 [5] ∪d1 [3] ∪d1 [1] ∪d1 [0] ∪1 out1 [29] = d1 [29] ∪d1 [28] ∪d1 [27] ∪d1 [26] ∪d1 [24] ∪d1 [20] ∪d1 [19] ∪ d1 [18] ∪d1 [17] ∪d1 [15] ∪d1 [14] ∪d1 [12] ∪d1 [11] ∪d1 [7] ∪d1 [5] ∪d1 [4] ∪d1 [2] ∪ d1 [0] ∪1 out1 [28] = d1 [28] ∪d1 [27] ∪d1 [26] ∪d1 [25] ∪d1 [23] ∪d1 [19] ∪d1 [18] ∪d1 [17] ∪d1 [16] ∪d1 [14] ∪d1 [13] ∪d1 [11] ∪d1 [10] ∪d1 [6] ∪d1 [4] ∪d1 [3] ∪d1 [1] ∪1 out1 [27 ] = d1 [31] ∪d1 [27] ∪d1 [26] ∪d1 [25] ∪d1 [24] ∪d1 [22] ∪d1 [18] ∪d1 [17] ∪d1 [16] ∪d1 [15 ] ∪d1 [13] ∪d1 [12] ∪d1 [10] ∪d1 [9] ∪d1 [5] ∪d1 [3] ∪d1 [2] ∪d1 [0] ∪1 out1 [26] = d1 [ 30] ∪d1 [26] ∪d1 [25] ∪d1 [24] ∪d1 [23] ∪d1 [21] ∪d1 [17] d1 [16] ∪d1 [15] ∪d1 [14] ∪d1 [12] ∪d1 [11] ∪d1 [9] ∪d1 [8] ∪d1 [4] ∪d1 [2] ∪d1 [1] ∪ 1 out1 [25] = d1 [30] ∪d1 [28] ∪d1 [26] ∪d1 [25] ∪d1 [24] ∪d1 [23] ∪d1 [21] ∪d1 [19] ∪d1 [17] ∪d1 [15] ∪d1 [11] ∪d1 [10] ∪d1 [9] 9d1 [8] ∪d1 [6] ∪d1 [4] ∪d1 [3] ∪d1 [2] ∪1 out1 [24 ] = d1 [31] ∪d1 [29] ∪d1 [27] ∪d1 [25] ∪d1 [24] ∪d1 [23] ∪d1 [22] ∪d1 [20] ∪d1 [18] ∪d1 [16 ] ∪d1 [14] ∪d1 [10] ∪d1 [9] 9d1 [8] ∪d1 [7] ∪d1 [5] ∪d1 [3] ∪d1 [2] ∪d1 [1] ∪1 out1 [ 23] = d1 [31] ∪d1 [30] ∪d1 [28] ∪d1 [26] ∪d1 [24] ∪d1 [23] ∪d1 [22] ∪d1 [21] ∪d1 [19] ∪d1 [ 17] ∪d1 [15] ∪d1 [13] ∪d1 [9] 9d1 [8] ∪d1 [7] ∪d1 [6] ∪d1 [4] ∪d1 [2] ∪d1 [1] ∪d1 [ 0] ∪1 out1 [22] = d1 [28] ∪d1 [27] ∪d1 [26] ∪d1 [25] ∪d1 [23] ∪d1 [19] ∪d1 [18] ∪d1 [17] ∪d1 [13] ∪d1 [12] ∪d1 [9] ∪d1 [8] ∪d1 [5] ∪d1 [4] ∪d1 [3] ∪d1 [2] ∪1 out1 [21] = d1 [30] ∪ d1 [29] ∪d1 [28] ∪d1 [27] ∪d1 [25] ∪d1 [24] ∪d1 [21] ∪d1 [20] ∪d1 [19] ∪d1 [18] ∪d1 [14] ∪ d1 [13] ∪d1 [12] ∪d1 [11] ∪d1 [9] ∪d1 [8] ∪d1 [6] ∪d1 [3] ∪d1 [0] 1 out1 [20] = d1 [29] ∪d1 [28] ∪d1 [27] ∪d1 [26] ∪d1 [24] ∪d1 [23] ∪d1 [20] ∪d1 [19] ∪d1 [18] ∪d1 [17] ∪d1 [13] ∪d1 [12] ∪d1 [11] ∪d1 [10] ∪d1 [8] ∪d1 [7] ∪d1 [5] ∪d1 [2] ∪1 out1 [19 ] = d1 [31] ∪d1 [28] ∪d1 [27] ∪d1 [26] ∪d1 [25] ∪d1 [23] ∪d1 [22] ∪d1 [19] ∪d1 [18] ∪d1 [17 ] ∪d1 [16] ∪d1 [12] ∪d1 [11] ∪d1 [10] ∪d1 [9] ∪d1 [7] ∪d1 [6] ∪d1 [4] ∪d1 [1] ∪1 out1 [ 18] = d1 [30] ∪d1 [27] ∪d1 [26] ∪d1 [25] ∪d1 [24] ∪d1 [22] ∪d1 [21] ∪d1 [18] ∪d1 [17] ∪d1 [ 16] ∪d1 [15] ∪d1 [11] ∪d1 [10] ∪d1 [9] ∪d1 [8] ∪d1 [6] ∪d1 [5] ∪d1 [3] ∪d1 [0] ∪1 out1 [17] = d1 [29] ∪d1 [26] ∪d1 [25] ∪d1 [24] ∪d1 [23] ∪d1 [21] ∪d1 [20] ∪d1 [17] ∪d1 [16] ∪d1 [15] ∪d1 [14] ∪d1 [10] ∪d1 [9] ∪d1 [8] ∪d1 [7] ∪d1 [5] 1d1 [4] ∪d1 [2] ∪1 out1 [16] = d1 [31] ∪d1 [28] ∪d1 [25] ∪d1 [24] ∪d1 [23] ∪d1 [22] ∪d1 [20] ∪d1 [19] ∪d1 [16] ∪d1 [15] ∪ d1 [14] ∪d1 [13] ∪d1 [9] ∪d1 [8] ∪d1 [7] ∪d1 [6] ∪d1 [4] ∪d1 [3] ∪d1 [1] ∪1 out1 [15] = d1 [29] ∪d1 [28] ∪d1 [27] ∪d1 [26] ∪d1 [24] ∪d1 [23] ∪d1 [20] ∪d1 [1 8] ∪d1 [17] ∪d1 [16] ∪d1 [15] ∪d1 [12] ∪d1 [9] ∪d1 [8] ∪d1 [5] ∪d1 [4] ∪d1 [3] ∪d1 [ 1] ∪1 out1 [14] = d1 [28] ∪d1 [27] ∪d1 [26] ∪d1 [25] ∪d1 [23] ∪d1 [22] ∪d1 [19] ∪d1 [17] ∪d1 [16] ∪d1 [15] ∪d1 [14] ∪d1 [11] ∪d1 [8] ∪d1 [7] ∪d1 [4] ∪d1 [3] ∪d1 [2] ∪d1 [0] ∪1 out1 [13] = d1 [27] ∪d1 [26] ∪d1 [25] ∪d1 [24] ∪d1 [22] ∪d1 [21] ∪d1 [18] ∪d1 [16] ∪d1 [15] ∪ d1 [14] ∪d1 [13] ∪d1 [10] ∪d1 [7] ∪d1 [6] ∪d1 [3] ∪d1 [2] ∪d1 [1] [1 out1 [12] = d1 [31] ∪d1 [26] ∪d1 [25] ∪d1 [24] 24d1 [23] 23d1 [21] [d1 [20] 1d1 [17] ∪d1 [15] ∪d1 [14] ∪d1 [13] ∪d1 [12] ∪d1 [9] ∪d1 [6] ∪d1 [5] ∪d1 [2] ∪d1 [1] ∪d1 [0] ∪1 out1 [11] = d1 [29] ∪d1 [28 ] ∪d1 [26] ∪d1 [25] ∪d1 [24] ∪d1 [23] ∪d1 [21] ∪d1 [17] ∪d1 [12] ∪d1 [11] ∪d1 [9] ∪d1 [8 ] ∪d1 [7] ∪d1 [6] ∪d1 [5] ∪d1 [2] ∪1 out1 [10] = d1 [31] ∪d1 [30] ∪d1 [29] ∪d1 [27] ∪d1 [ 26] ∪d1 [25] ∪d1 [24] ∪d1 [23] ∪d1 [21] ∪d1 [19] ∪d1 [17] ∪d1 [14] ∪d1 [13] ∪d1 [11] ∪d1 [ 10] ∪d1 [9] ∪d1 [8] ∪d1 [5] ∪d1 [2] ∪d1 [0] ∪1 out1 [9] = d1 [31] ∪ d1 [25] ∪d1 [24] ∪d1 [23] ∪d1 [21] ∪d1 [19] ∪d1 [18] ∪d1 [17] ∪d1 [14] ∪d1 [12] ∪d1 [10] ∪ d1 [8] ∪d1 [6] ∪d1 [2] ∪d1 [0] ∪1 out1 [8] = d1 [30] ∪d1 [24] ∪d1 [23] ∪d1 [22] ∪d1 [20] ∪d1 [18] ∪d1 [17] ∪d1 [16] 16d1 [13] ∪d1 [11] ∪d1 [9] ∪d1 [7] ∪d1 [5] ∪d1 [1] ∪1 out1 [7 ] = d1 [30] ∪d1 [28] ∪d1 [26] ∪d1 [23] ∪d1 [20] ∪d1 [15] ∪d1 [14] ∪d1 [13] ∪d1 [12] ∪d1 [10 ] ∪d1 [9] ∪d1 [8] ∪d1 [7] ∪d1 [2] ∪d1 [1] ∪1 out1 [6] = d1 [31] ∪d1 [30] ∪d1 [28] ∪d1 [ 27] ∪d1 [26] ∪d1 [25] ∪d1 [21] ∪d1 [20] ∪d1 [17] ∪d1 [16] ∪d1 [12] ∪d1 [11] ∪d1 [8] ∪d1 [ 4] ∪d1 [2] ∪1 out1 [5] = d1 [31] ∪d1 [30] ∪d1 [29] ∪d1 [27] ∪d1 [26] ∪d1 [25] ∪d1 [24] ∪d1 [20] ∪d1 [19] ∪d1 [16] ∪d1 [15] ∪d1 [11] ∪d1 [10] ∪d1 [7] ∪d1 [3] ∪d1 [1] ∪1 out1 [4] = d1 [31] ∪d1 [25] ∪d1 [24] ∪d1 [23] ∪d1 [22] ∪d1 [21] ∪d1 [20] ∪d1 [18] ∪d1 [17] ∪d1 [16] ∪ d1 [15] ∪d1 [13] ∪d1 [10] ∪d1 [7] ∪d1 [4] ∪d1 [1] ∪1 out1 [3] = d1 [29] ∪d1 [28] ∪d1 [26] ∪d1 [24] ∪d1 [23] ∪d1 [15] ∪d1 [13] ∪d1 [12] ∪d1 [7] ∪d1 [4] ∪d1 [3] ∪d1 [2] ∪d1 [1] ∪1 out1 [2] = d1 [31] ∪d1 [28] ∪d1 [27] ∪d1 [25] ∪d1 [23] ∪d1 [22] ∪d1 [14 ] ∪d1 [12] ∪d1 [11] ∪d1 [6] ∪d1 [3] ∪d1 [2] ∪d1 [1] ∪d1 [0] ∪1 out1 [1] = d1 [29] ∪d1 [ 28] ∪d1 [27] ∪d1 [24] ∪d1 [20] ∪d1 [19] ∪d1 [17] ∪d1 [16] ∪d1 [14] ∪d1 [11] ∪d1 [10] ∪d1 [ 9] ∪d1 [7] ∪d1 [6] ∪d1 [5] ∪d1 [4] ∪1 out1 [0] = d1 [31] ∪d1 [30] ∪d1 [29] ∪d1 [27] ∪d1 [23] ∪d1 [22] ∪d1 [21] ∪d1 [20] ∪d1 [18] ∪d1 [17] ∪d1 [15] ∪d1 [14] ∪d1 [10] ∪d1 [8] ∪d1 [7] ∪d1 [5] ∪d1 [3] ∪d1 [2] ∪d1 [1] ∪d1 [0] ∪1 Similarly, the [1] cycle remainder decoder 344 performs the following operation It can be easily realized by executing hardware. Here, the value of the 32-bit input data bus to the [1] cycle remainder decoder 344 is d2 [31: 0].
[1] The value of the 32-bit output data bus of the cycle remainder decoder 344 is set to out2 [31: 0]. Further, “式” in the following expression represents an exclusive OR of bits, and can be easily calculated by a combination circuit using an XOR circuit as hardware.

Out2 [31] = d2 [29] ∪d2 [23] ∪1 out2 [30] = d2 [31] ∪d2 [28] ∪d2 [22] ∪1 out2 [29] = d2 [31] ∪ d2 [30] ∪d2 [27] ∪d2 [21] ∪1 out2 [28] = d2 [30] ∪d2 [29] ∪d2 [26] ∪d2 [20] ∪1 out2 [27] = d2 [31 ] ∪d2 [29] ∪d2 [28] ∪d2 [25] ∪d2 [19] ∪1 out2 [26] = d2 [30] ∪d2 [28] ∪d2 [27] ∪d2 [24] ∪d2 [ 18] ∪1 out2 [25] = d2 [27] ∪d2 [26] ∪d2 [17] ∪1 out2 [24] = d2 [31] ∪d2 [26] ∪d2 [25] ∪d2 [16] ∪ 1 out2 [23] = d2 [30] ∪d2 [25] ∪d2 [24] ∪d2 [15] ∪1 out2 [22] = d2 [24] ∪d2 [14] ∪1 out2 [21] = d2 [ 29] ∪d2 [13] ∪1 out2 [20] = d2 [28] ∪d2 [12] ∪1 out2 [19] = d2 [31] ∪d2 [27] ∪d2 [11] ∪1 out2 [18] = d2 [31] ∪d2 [30] ∪d2 [26] ∪d2 [10] ∪1 out2 [17] = d2 [30] ∪d2 [29] ∪d2 [25] ∪d2 [9] ∪1 out2 [ 16] = d2 [29] ∪d2 [28] ∪d2 [24] ∪d2 [8] ∪1 out2 [15] = d2 [31] ∪d2 [29] ∪d2 [28] ∪d2 [27] ∪d2 [7] ∪1 out2 [14] = d2 [31] ∪d2 [30] ∪d2 [28] ∪d2 [27] ∪d2 [26] ∪d2 [6] ∪1 out2 [13] = d2 [31] ∪d2 [30] ∪d2 [29] ∪d2 [27] ∪d2 [26] ∪d2 [25] ∪d2 [5] ∪1 out2 [12] = d2 [30] ∪d2 [29] ∪d2 [28 ] ∪d2 [26] ∪d2 [25] ∪d2 [24] ∪d2 [4] ∪ 1 out2 [11] = d2 [28] ∪d2 [27] ∪d2 [25] ∪d2 [24] ∪d2 [3] ∪1 out2 [10] = d2 [29] ∪d2 [27] ∪d2 [26 ] ∪d2 [24] ∪d2 [2] ∪1 out2 [9] = d2 [29] ∪d2 [28] ∪d2 [26] ∪d2 [25] ∪d2 [1] ∪1 out2 [8] = d2 [28] ∪d2 [27] ∪d2 [25] ∪d2 [24] ∪d2 [0] ∪1 out2 [7] = d2 [31] ∪d2 [29] ∪d2 [27] ∪d2 [26] ∪ d2 [24] ∪1 out2 [6] = d2 [31] ∪d2 [30] ∪d2 [29] ∪d2 [28] ∪d2 [26] ∪d2 [25] ∪1 out2 [5] = d2 [31 ] ∪d2 [30] ∪d2 [29] ∪d2 [28] ∪d2 [27] ∪d2 [25] ∪d2 [24] ∪1 out2 [4] = d2 [30] ∪d2 [28] ∪d2 [ 27] ∪d2 [26] ∪d2 [24] ∪1 out2 [3] = d2 [31] ∪d2 [27] ∪d2 [26] ∪d2 [25] ∪1 out2 [2] = d2 [31] ∪ d2 [30] ∪d2 [26] ∪d2 [25] ∪d2 [24] ∪1 out2 [1] = d2 [31] ∪d2 [30] ∪d2 [25] ∪d2 [24] ∪1 out2 [0 ] = d2 [30] ∪d2 [24] ∪1 Next, details of the operation of the verification circuit according to the present embodiment will be described with reference to FIG. Verification circuit 261
Is used only during the operation of reading data from the storage medium, so the operation in this case will be described. Here, in particular, an error has occurred in the read {user data + CRC parity part + ECC parity part}, and the EC
The operation of the verification circuit 261 when performing a correction operation in the C circuit 262 will be described.

First, the CRC via the data bus 256
From the circuit 260 (see FIG. 5), the CRC remainder value (3) for {user data + CRC parity part (before error correction)}
2) and stores it in the CRC remainder latch 330.

When a plurality of errors occur, each time an error position and an error value in {user data + CRC parity section} are specified in ECC circuit 262 (see FIG. 5), only one error occurs. If
Only once, the error position and the error value are output from the data bus 251 and the data bus 252, respectively.

Upon receiving the error value from the data bus 252, the verification circuit 261 decodes the error value (8-bit data) by the error value
Bit data is created, and the 32-bit data is transferred to the CRC working register 342 by the data bus 338 and the selector 3.
Store via 40.

Here, the error value remainder decoder 341
This is a random logic for decoding 32-bit data as a result of expanding the received error value (8-bit data) into a polynomial and performing a remainder operation (see (Equation 2)) with a CRC generation polynomial. That is, the result of the CRC remainder operation of the error value (8-bit data) received by the operation of the error value remainder decoder 341 using the CRC generation polynomial is C
It is stored in the RC working register 342.

The remainder decoder selector 348 receives the error position via the data bus 251. The remainder decoder selector 348 performs sequence control on the operation of the selector 345 depending on the value of the received error position. 1
6] CRC working register 342 using cycle remainder decoder 343 and [1] cycle remainder decoder 344.
Update the value of.

Here, the sequence of the sequence control in the remainder decoder selector 348 (see FIG. 1) will be described with reference to FIG.

In FIG. 8, when the sequence control is started (step 450), first, the value of the received error position is stored in a counter (step 4).
51). Then, it is determined whether the value of the error position stored in the counter is 16 or more (step 45).
2). As a result of this determination, if the value of the error position is 16 or more, the value of the error position stored in the counter is 16
Subtraction (step 453), [16] cycle remainder decoder 3
43, and updates the value of the CRC working register 342 (step 453). Then, step 452
And the same determination is made. If the result of determination in step 452 is that the value of the error position is smaller than 16, it is checked whether the value of the error position is 1 or more (step 455). As a result of this investigation, if the value of the error position is 1 or more, 1 is subtracted from the value of the error position (step 45).
7), [1] CR using cycle remainder decoder 344
The value of the C working register 342 is updated (step 457). Then, the process returns to step 455 to make the same determination.

Thereafter, the above operation is repeated until the error position becomes zero.

Next, the operation of updating the value of the CRC working register 342 will be described in more detail with reference to FIG.

In FIG. 1, the value of the CRC working register 342 is input to the [16] cycle remainder decoder 343 via the data bus 347. [16] The cycle remainder decoder 343 outputs to the selector 345 32-bit data obtained by decoding the input 32-bit data using a random gate. Here, the [16] cycle remainder decoder 343 converts the input 32-bit data into a CRC.
Adopted as the initial value of the remainder calculation, followed by CRC remainder calculation in which 16-byte data of value 0 is input.
It outputs bit data.

The value of the CRC working register 342 is input to the [1] cycle remainder decoder 344 via the data bus 347. [1] Cycle remainder decoder 3
Reference numeral 44 denotes a selector 3 which outputs 32-bit data obtained by decoding the input 32-bit data by a random gate.
45. This [1] cycle remainder decoder 344
Uses the input 32-bit data as an initial value of the CRC remainder calculation, and outputs 32-bit data resulting from the CRC remainder calculation in which the data of one byte value 0 is input.

The selector 345 is controlled by the remainder decoder selector 348 to select either the path of the [16] cycle remainder decoder 343 or the [1] cycle remainder decoder as a decoder.
The value of the CRC working register 342 is set to 32
Update with bit data.

By performing the above operation, the verification circuit 261 realizes an operation corresponding to each term of (Equation 8) from the received error position and error value.

When the sequence control operation described with reference to FIG. 8 is completed, exclusive OR with the value of the remainder storage register 334 is performed using the 32-bit data stored in the CRC working register 342, and the remainder storage operation is performed. The value of the register 334 is updated. That is, the 32-bit data of the CRC working register 342 is stored in the data bus 347.
And the remainder storage register 334 sent via the data bus 333 by the 32-bit exclusive OR circuit 337
(However, the initial value is 0) is exclusive-ORed, and the operation result is obtained by the data bus 336 and the selector 335.
The remainder storage register 334 is updated via However, the remainder storage register 334 updates with its own value in synchronization with the clock except at this time (that is, the CRC is updated).
When data is not sent from the working register 342, the register value does not change.) That is, the remainder storage register 334 updates with its own value via the data bus 333 and the selector 335 except for the update process described above.

The operation when one error position and one error value are received has been described above. When a plurality of errors occur, the data bus 251, the data bus 25
Further, the error position and error value pair via E
The same operation is performed because it is output from the CC circuit 262 (see FIG. 5). However, while the CRC working register 342 or the remainder storage register 334 is being updated for each error position and error value pair, the ECC circuit 262 is notified via the control line 253 that it is busy. Output of error position and error value of

When the above operation is completed for all error positions and error values, the remainder storage register 334
Stores a value obtained by calculating a CRC remainder by a CRC generation polynomial from an error polynomial specified by an error position and an error value calculated by the ECC circuit 262. In other words, at this time, the value corresponding to the value S ′ obtained by (Equation 8) is stored in the remainder storage register 334.

The comparator 331 includes a remainder storage register 334.
Is compared with the CRC remainder value stored in the CRC remainder latch 330 and calculated from the {user data + CRC parity part} including the error. As a result of the comparison, if these two values match, it is determined that the ECC circuit 262 has performed the error correction operation normally. If they do not match, the ECC circuit 262 determines that erroneous correction has occurred during the error correction operation, and reports to the ECC circuit 262 via the control line 250 that the erroneous correction of the ECC circuit has been detected.

When the present embodiment is applied, the error correction circuit does not depend on the error correction algorithm,
While determining the error value, a value for evaluating whether or not the error correction has been performed by the error correction operation of the error correction circuit can be determined in parallel. This makes it possible to evaluate erroneous corrections at high speed.

That is, as shown in the flowchart of FIG. 9, step 507 for calculating an error position and an error value and step 509 for calculating a CRC remainder from the error position and the error value are executed in parallel. it can. Therefore, ECC correction operation and E
It is possible to speed up the execution of the verification operation of the CC correction operation.

The error value remainder decoder 341, CRC working register 342, selector 3 shown in FIG.
40, a plurality of operation blocks each including a [16] cycle remainder decoder 343, a [1] cycle remainder decoder 344, and a remainder decoder selector 348. When an error position and an error value transmission request come from the ECC circuit 262, one Even when the operation block is in operation, another open operation block can receive the error position and the error value and perform the same operation. This makes it possible to execute the ECC correction result evaluation operation at a higher speed.

Further, in the above description, the code used for the ECC correction operation does not have an interleave structure, but the present invention uses the code having the interleave structure as E
It is needless to say that the present invention is applicable when used for CC correction.

Next, a second embodiment of the present invention will be described with reference to FIG. In the magnetic disk device of the present embodiment, the drive control circuit includes a CRC.
This embodiment differs from the first embodiment in that a plurality of pairs of circuits and verification circuits are provided. Blocks other than the drive control circuit can be basically configured in the same manner, so that the description thereof will not be repeated here, and differences will be mainly described. In the present embodiment, by adopting such a configuration of the drive control circuit, it is possible to avoid an increase in the circuit scale for the remainder operation even in the case of supporting a large CRC parity unit.

In the first embodiment described above, C
The RC parity part is assumed to be 4 bytes. For example, in order to increase the verification capability against ECC error correction, CR bytes are used.
If the C parity part is increased, the circuit scale of the [16] cycle remainder decoder and [1] cycle decoder in FIG. This embodiment is an example of a technique for avoiding the enlargement of the circuit scale.
That is, in the first embodiment, one CRC code is used as a means for detecting an erroneous correction of an ECC correction operation. In the present embodiment, however, a plurality of CRCCs (or similar detection means) are used. The present invention is applied to:
In the following description, a case where two are set as the number of CRCCs to be used will be described. However, it is needless to say that the present invention can be applied to a combination of three or more CRCCs.

As a configuration of data to be read, for example, {user data + CRC parity unit 1 + CRC parity unit 2 + ECC parity unit} can be considered. This data block can be generated as follows.
That is, first, the first CRCC
The CRC parity unit 1 is calculated by Then, the CRC parity unit 2 is calculated by the second CRCC for the data block of {user data + CRC parity unit 1}. Then, {user data + CRC parity part 1 + C
An ECC parity part is calculated by the ECC for RC parity part 2 #. In the present embodiment, an example will be described in which the size of each of the CRC parity unit 1 and the CRC parity unit 2 is set to 4 bytes. In contrast to the code having such a configuration, in the magnetic disk device of the present embodiment,
This is handled by using a drive control circuit including a plurality of pairs of a CRC circuit and a verification circuit.

In FIG. 10, C in the present embodiment is shown.
Each of the RC circuit B660 and the CRC circuit C601 is a CRC circuit 260 (FIG. 7) according to the first embodiment.
And the basic configuration is the same. Further, each of the verification circuit B661 and the verification circuit C603 in the present embodiment is the same as the verification circuit 261 in the first embodiment.
The basic configuration is the same as that shown in FIG. These circuits are different from the first embodiment in that a CRC circuit B6
60, a pair of a verification circuit B661 and a CRC circuit C60
1. Independent CR for each pair of the verification circuit C603
That is, a C-generating polynomial is used.

Hereinafter, referring to FIG. 10, the configuration and operation of drive control section B 690 in the present embodiment will be described in terms of writing and reading of user data to and from magnetic disk 810 (see FIG. 4) as a storage medium. So,
Each will be described. First, writing of user data to the magnetic disk 810 (see FIG. 4) will be described.

Data bus 25 of drive control unit B690
User data to be written to the data buffer 8
6 (see FIG. 4), and is transmitted in 8-bit units via the buffer control unit 818 (see FIG. 4). The drive control unit B690 stores the user data in the CRC circuits B660 and C660.
The signals are input to the RC circuit C601 and the ECC circuit 662. Therefore, at this time, the selector 664 selects the data bus 258 and outputs the data supplied from the data bus 258 to the output bus 653.

Until all the user data is transferred to the three blocks (CRC circuit B660, CRC circuit C601, and ECC circuit 662), each block operates as follows. That is, the CRC circuits B660, C660
Each of the RC circuits C601 regards the transferred user data as a polynomial, performs a remainder operation using the respective CRC generating polynomials (see (Equation 2)), and
The circuit 662 regards the transferred user data as a polynomial and performs a remainder operation on the ECC generation polynomial. Also, EC
In parallel with this remainder operation, the C circuit 662 converts the transferred user data into codeword output buses 65 in 8-bit units.
5 is output.

When all the user data has been transferred to the above three blocks (CRC circuit B660, CRC circuit C601, and ECC circuit 662), each block operates as follows. That is, in the CRC circuit B660, C
Since the RC parity unit 1 (4 bytes in the present embodiment) is generated, the CRC circuit C is transmitted via the data bus 657.
The CRC parity unit 1 is transferred to the ECC circuit 601 and the ECC circuit 662 in 8-bit units. That is, during this period, the selector 664 selects the data bus 657, and outputs data from the data bus 657 to the data bus 653. The selector 621 selects the data bus 657, and outputs data from the data bus 657 to the CRC circuit C601.

CRC circuit C601 and ECC circuit 66
2 continuously performs the remainder operation by the respective generator polynomials using the CRC parity unit 1 transferred via the data bus 657 described above, following all the user data bytes. In parallel with this remainder operation, EC
The C circuit 662 outputs the transferred CRC parity unit 1 from the codeword output bus 655 in 8-bit units.

When all the CRC parity units 1 (4 bytes in this embodiment) are transferred to the CRC circuit C 601 and the ECC circuit 662, the CRC
Since the C parity unit 2 is generated, thereafter, the generated CRC parity unit 2 is output via the data bus 608 in units of 8 bits.

The ECC circuit 662 uses the above-described CRC parity unit 2 transferred via the data bus 657 to perform the remainder operation using the ECC generation polynomial following all the {user data bytes + CRC parity unit 1}. Continue. In parallel with the remainder operation, the ECC circuit 662 outputs the transferred CRC parity unit 2 from the codeword output bus 655 in 8-bit units.

When all the CRC parity units 2 (4 bytes in this embodiment) are transferred to the ECC circuit 662, E
Since the ECC parity section is generated inside the CC circuit 662, the ECC parity section is thereafter output via the data bus 655 in units of 8 bits.

By inputting user data via data bus 258 by drive control section 690 in this manner, {user data section + CRC parity section 1 + CRC parity section 2 + ECC parity section} from codeword output bus 255. Are sequentially output.

The drive control section 690 is composed of {user data section + CRC parity section 1 + CRC parity section 2 + ECC
Parity section｝ is recorded on magnetic disk 810 (see FIG. 4) via data bus 829 (see FIG. 4).

As described above, drive control section 690 in the present embodiment performs an operation of writing user data to a recording medium.

Next, referring to FIG. 10, error correction by ECC in the operation of reading user data from magnetic disk 810 (see FIG. 4) and EC
A description will be given of a detection operation of C erroneous correction by CRC.

{User data portion + CRC parity portion 1+ read from magnetic disk 810 (see FIG. 4)}
The CRC parity unit 2 and the ECC parity unit｝ are connected to the CRC circuit B 660 and the CRC circuit C via the data bus 258.
601 and the ECC circuit 662. Therefore, during this period, the selector 664 sets the data bus 25
8 and outputs the data therefrom to the output bus 653.

In CRC circuit B660, {user data part + CRC parity part 1} is subjected to remainder operation by the CRC generating polynomial to calculate CRC remainder 1 of 4 bytes.
Then, the calculated CRC remainder 1 is output to the verification circuit B 661 via the data bus 656 every four bytes at a time. The verification circuit B661 stores the received 4-byte CRC remainder.

Similarly, in CRC circuit C601, {user data section + CRC parity section 1 + CRC parity section 2}
Is subjected to a remainder operation using the CRC generation polynomial to calculate a 4-byte CRC remainder 2. And CRC remainder 2 is
The data is output to the verification circuit C603 via the data bus 602 at a time of 4 bytes. The verification circuit C603 stores the received 4-byte CRC remainder internally.

The ECC circuit 662 calculates a syndrome from {user data section + CRC parity section 1 + CRC parity section 2 + ECC parity section}. If at least one of the calculated syndromes is non-zero, the ECC circuit 662 reads the {user data part + C
It is determined that an error is included in RC parity section 1 + CRC parity section 2 + ECC parity section｝, and a correction operation is started. Also, if the calculated syndromes are all zero, it is read {user data part + CRC parity part 1
+ CRC parity section 2 + ECC parity section｝ determines that no error is included, and reports to drive control section B690 that normal data transfer has been performed.

Next, the correction operation will be described.

When the correction operation using the syndrome is performed by the ECC circuit 662, if the number of generated errors is within the correction capability range of the ECC, one or more pairs of error positions and error values are set (the number of actually generated errors). Minutes only).

At this time, every time a pair of an error position and an error value is found (provided that the error position is the user data portion or the CRC parity portion 1), the error signal is transferred via the data bus 651 and the data bus 652, respectively. An error position and an error value pair are output to the verification circuit B661.

The verification circuit B661 performs an erroneous correction verification operation using the received error position and error value. The verification circuit B661 calculates and updates the CRC re-residue for erroneous correction verification every time it receives an error position and an error value. In this embodiment, it is possible to reduce the number of clock cycles required for the update operation of the CRC remainder using a set of error positions and error values to several to several tens clock cycles, and to execute the update operation at high speed. It is possible to

Similarly, a pair of an error position and an error value (when the error position is the user data portion, CRC parity portion 1 or CRC parity portion 2) is 1
Each time it is found, it outputs a pair of an error position and an error value to the verification circuit C603 via the data bus 604 and the data bus 605, respectively.

The verification circuit C603 performs an erroneous correction verification operation using the received error position and error value. The verification circuit C603 calculates and updates the CRC re-residue for erroneous correction verification every time an error position and an error value are received. In this embodiment, it is possible to reduce the number of clock cycles required for the update operation of the CRC remainder using a set of error positions and error values to several to several tens clock cycles, and to execute the update operation at high speed. It is possible to

Each time a pair of an error position and an error value is found (if the error position satisfies the position described above), the ECC circuit 662 sends the detected error position and error value to the verification circuit B 661 and the verification circuit C 603. However, if the verification circuit B661 and the verification circuit C603 have not completed updating the CRC re-residue using the error position and the error value that have already been passed, the verification circuit B661 and the verification circuit C603, respectively. C603 is
ECC circuit 662 waits for the output of the found error location and error value until it is completed, since it reports that it is incomplete via control lines 653 and 607, respectively. Then, when the update of the CRC remainder is completed, the error position and the error value are determined by the verification circuit B66.
1. Output to each of the verification circuits C603,
Start calculating the next error position and error value.

The ECC circuit 662 calculates all expected error positions and error value pairs, and the verification circuit B
661, in each of the verification circuits C603, using the pair of all the received error positions and error values,
When the updating of the C remainder is completed, the verification circuit B66
1. Each CRC residual value stored inside the verification circuit C603 is, if there is no error correction by ECC,
The CRC remainder already stored in each of the verification circuits B661 and C603 and the CRC circuits B660 and CR
C already received from the C circuit C601 and stored respectively.
The RC remainders should match each other.

If the CRC remainder value and the CRC residue value are equal, the verification circuit B 661 and the verification circuit C 603
Are interpreted as having been corrected normally.
Otherwise (if these CRC re-surplus values are not equal to the CRC remainder values), it is determined that an erroneous correction by ECC has been performed, and an erroneous correction is generated via buses 650 and 606 as E.
Report to CC circuit 662. At this time, it is determined whether an erroneous correction of the ECC is detected in one or both of the verifying circuit B 661 and the verifying circuit C 603 according to the erroneous correction occurrence pattern. That is, if an error is corrected in at least one or more positions in the {user data section + CRC parity section 1}, both the verification circuit B661 and the verification circuit C603 can detect the error correction in many cases (the CRC detection capability is low). Due to limitations, there is a certain probability that you may miss an error correction.)
In addition, if the error correction is made in at least one or more positions only in the CRC parity unit 2, the error correction can be verified only in the verification circuit C603 (similarly, due to the limitation of the CRC detection capability, the error correction is performed at a certain probability. You may miss a mistake.)

The ECC circuit 662 uses the pair of the calculated error position and error value to generate the data bus 634,
The corresponding error byte data stored in the data buffer 816 (see FIG. 4) is corrected to normal data via the buffer control unit 818 (see FIG. 4).

By the way, the correction operation was performed by the ECC circuit 662. However, the ECC circuit 662 determines that the correction was unsuccessful (uncorrectable) from the operation result, or the above-described verification circuit B 661 and verification circuit C 603 (both, Erroneous correction of ECC is detected by buses 650 and 6
If the erroneous correction is reported to the ECC circuit 662 via the ECC 06, the ECC circuit 662 outputs the uncorrectable report signal 65.
4 to the upper drive control unit B690,
Correction attempted {user data + CRC parity part 1 + C
It reports that RC parity unit 2 + ECC parity unit｝ was uncorrectable. At this time, the drive control unit B690
Indicates that the read user data contains an error and EC
It recognizes that the data cannot be corrected even by the C circuit 662, and performs rereading (retry) processing of the user data.

As described above, in the present embodiment,
Even in the case of a system using a plurality of CRC codes,
The erroneous correction detection to which the present invention is applied can be executed in a state in which the circuit scale for the remainder operation is prevented from increasing.

[0199]

According to the present invention, error correction by ECC and erroneous correction verification of the ECC correction result by error detection means such as CRC can be efficiently parallelized. The total operation time including the verification operation of the correction result is shortened. In other words, apparently, the verification operation time approaches zero.

As a result, even when a complicated (time-consuming) correction operation algorithm is employed or under high-speed data transfer, an error correction operation and a verification operation of the correction result can be realized on the fly.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a verification circuit according to a first embodiment.

FIG. 2 is a flowchart showing a conventional ECC operation and CRC operation.

FIG. 3 is an explanatory diagram showing an electronic circuit unit of the magnetic disk drive to which the present invention is applied.

FIG. 4 is a configuration diagram showing a magnetic disk drive to which the present invention is applied.

FIG. 5 is a block diagram illustrating a drive control unit according to the first embodiment of the present invention.

FIG. 6 is a block diagram showing an ECC circuit to which the present invention is applied.

FIG. 7 is a block diagram showing a CRC circuit to which the present invention is applied.

FIG. 8 is a flowchart showing sequence control of a remainder decoder selector to which the present invention is applied.

FIG. 9 is a flowchart showing an ECC operation and a CRC operation to which the present invention is applied.

FIG. 10 is a block diagram illustrating a drive control unit according to a second embodiment of the present invention.

FIG. 11 is an explanatory diagram showing a magnetic disk drive to which the present invention is applied.

[Explanation of symbols]

 290: Drive control unit 260: CRC circuit 261: Verification circuit 262: ECC circuit 301: Code generation / syndrome calculation circuit 302: Error position / value calculator 305: Buffer interface circuit 307: Uncorrectable determination circuit 330: CRC remainder latch 331 ... Comparator 334 ... Remainder storage register 341 ... Error value remainder decoder 342 ... CRC working register 343 ... [16] Cycle remainder decoder 344 ... [1] Cycle remainder decoder 348 ... Remainder decoder selector 405 ... 8-bit operation feedback circuit 815 ... CPU 819 CPU input / output control unit 825 host interface control unit 818 buffer control unit 816 data buffer

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Katsumi Yamamoto, Inventor 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. Within Hitachi Storage Systems Division

Claims (17)

[Claims] 1. A method for correcting an error contained in a code word obtained by adding an error correction code to a sequence obtained by adding an error detection code to user data representing target information using the error correction code. In the erroneous correction verification device for verifying whether erroneous correction has occurred, the remainder obtained by dividing the codeword by an error detection code generation polynomial that generates the error detection code, and the remainder included in the code sequence An interfacing means for receiving an error position and an error value of each error; and an error detection code generation for generating the error detection code using the received error polynomials respectively generated from the error position and the error value of each error Remainder calculating means for calculating each remainder divided by a polynomial, and adding means for obtaining an exclusive OR of all the remainders; Comparing the sum calculated by the adding means with the received remainder, and determining that the erroneous correction has not occurred when they do not match, and that the erroneous correction has not occurred when they match. An erroneous correction verification device, comprising: a determination unit. 2. The error correction verification device according to claim 1, wherein the remainder operation means calculates a remainder obtained by dividing an error polynomial generated from an error position and an error value by the error detection code generation polynomial for each error. An error correction verification device, wherein the calculation for obtaining the remainder is executed in accordance with a temporal order in which the error position and the error value are received. 3. The erroneous correction verification device according to claim 1, wherein said adding means calculates an exclusive OR of all the residuals by sequentially adding the residuals each time the residuals are obtained. An error correction verification device characterized by the following. 4. The erroneous correction verification device according to claim 1, wherein the remainder calculating means calculates a remainder obtained by dividing a polynomial of a predetermined order by the error detection code generation polynomial. An error correction verifying apparatus comprising at least a residue decoder for a first-order polynomial. 5. User data representing target information;
An error included in a code word including an error detection code generated by the error detection code generation polynomial from the user data and an error correction code generated by an error correction code generation polynomial from a sequence including the information code and the error detection code. In the error correction device for correcting the error, an error detection unit for detecting whether an error is included using the error detection code, and when the error detection unit detects that the error is included, An error correction unit for performing error correction using the error correction code, and at the time of error correction in the error correction unit, an error correction verification unit for verifying whether or not erroneous correction has occurred; An error detection unit, which calculates a remainder obtained by dividing the codeword by the error detection code generation polynomial; Notifying means for notifying the error correction unit that the error is included when the remainder calculated by the remainder calculation means is non-zero, the error correction unit comprising: Error correction calculating means for calculating an error position and an error value of each error included in the series including the detection code; and, in the series, the byte data at the obtained error position, the byte data and the obtained error. Correction means for obtaining byte data obtained by taking an exclusive OR of values, wherein the erroneous correction verification unit is configured using the erroneous correction verification device according to any one of claims 1 to 4. An error correction device, characterized in that: 6. An error correction apparatus for correcting an error contained in a code word obtained by further adding an error correction code to a sequence in which an error detection code is added to user data representing target information, A detection unit for detecting whether or not the word includes an error; and when the detection unit detects that the codeword includes an error, the error of the codeword is detected using an error correction code. A correction unit for performing a correction operation for correcting, and a correction result evaluation unit for evaluating a correction result of the error correction in the correction unit, wherein the correction unit includes: An arithmetic circuit for determining an error value and performing a correction operation for correcting an error of a codeword using the determined error position and error value; A report circuit for reporting the error position and error value of the number of errors to the correction result evaluation unit each time an error is calculated, wherein the correction result evaluation unit uses the received error position and error value. The correction unit and the correction result evaluation unit execute the correction operation in the correction unit and the evaluation of the correction result in the correction result evaluation unit in parallel. An error correction device characterized by the above-mentioned. 7. The error correction device according to claim 6, wherein the correction result evaluation unit determines the order of the received error positions,
An error correction device characterized in that evaluation of a correction result is advanced irrespective of the relationship with the position order on the error correction code. 8. The error correction device according to claim 6, wherein the correction result evaluation unit creates an error polynomial from the received error position and error value, and uses the error polynomial to generate an error polynomial. A remainder operation circuit for performing a remainder operation using a generator polynomial of an error detection code, a register for storing a value, a value stored in the register, and a value of the remainder calculated by the remainder operation circuit. An exclusive OR, an updating circuit for updating the value stored in the storage means with the value obtained by taking the exclusive OR, and an update circuit for all error positions and error values included in the code word. When the remainder operation is performed by the remainder operation circuit and the value stored in the storage means is updated with the value of the exclusive OR of the remainder, the value is stored in the register. And a result of the remainder operation by the error detection code generation polynomial using the codeword, and when they are equal, a determination circuit is provided for determining that the error has been properly corrected by the error correction means. An error correction device, characterized in that: 9. The error correction device according to claim 8, wherein the correction result evaluation unit includes a plurality of the remainder operation circuits, and further includes: when one remainder operation circuit is operating, further correcting the other errors. An error correction device, wherein when an error position and an error value are further given from the means, an operation is performed on the given error position and the error value using another remainder operation circuit. 10. The error correction device according to claim 6, wherein the codeword includes two or more independent error detection codes as error detection codes, and the correction result evaluation unit includes: An error correction device comprising two or more independent correction result evaluation means for evaluating a correction result of the correction means using each of the two or more independent error detection codes. 11. The error correction device according to claim 6, wherein the codeword has an interleave configuration of the error correction code, and the correction means performs a correction operation for each interleave. The correction result evaluator includes a circuit for receiving an error position and an error value calculated for each interleave, and recalculating the error position to an error position in the error detection code. An error correction device characterized by the above-mentioned. 12. A reproduction device comprising the error correction device according to claim 5. Description: 13. A recording / reproducing apparatus comprising the reproducing apparatus according to claim 12. 14. A communication device comprising the error correction device according to claim 5. Description: 15. An information code representing information, an error detection code generated from the information code by a cyclic redundancy code generation polynomial, and an error correction code generation polynomial generated from a sequence including the information code and the error detection code. For error correction using the error correction code for a code word including an error correction code, in the error correction verification method for verifying whether error correction has occurred during error correction, the cyclic redundancy code for the code word The remainder of the generator polynomial, and the error position and error value of each error included in the sequence including the user data and the error detection code are received. For each of the errors, the term including the received error position and error value is the highest order term, respectively. The remainder of the cyclic redundancy code generation polynomial for the polynomial The sum of the remainder obtained by exclusive OR is calculated, and the obtained sum is compared with the received remainder. If they do not match, it is determined that an erroneous correction has occurred. An erroneous correction verification method comprising determining that no correction has occurred and verifying the error correction. 16. A recording medium storing a program, wherein the program is a program capable of operating the first and second processors in parallel, wherein an error detection code is added to user data representing target information. It is detected whether or not an error is included in the code word to which the error correction code is added in the sequence that has been added. If the code word includes an error, the error correction code is used to detect the error of the code word. Correction operation for correcting an error
And a correction result evaluation unit for evaluating a correction result of the error correction in the correction unit by the second processor, wherein the correction unit is included in a code word. Determining the error position and error value of the error to be corrected, and performing a correction operation for performing error correction of the codeword using the determined error position and error value; Reporting the error position and the error value to the correction result evaluator each time an error is calculated, wherein the correction result evaluator has an error position and an error value of 1
Alternatively, a recording medium storing a program, comprising a step of performing an operation for evaluating a correction result each time a plurality of errors are given. 17. A remainder calculating device for calculating a remainder obtained by dividing a given polynomial by a predetermined polynomial, wherein a remainder obtained by dividing a polynomial of a predetermined order by the predetermined polynomial is obtained. And a residue decoder for at least a first-order polynomial.