JPH11177099A - Thin-film transistor and its manufacturing method, substrate for liquid crystal, liquid crystal device, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an ON current from decreasing and to reduce an off-leak current with a high breakdown voltage due to offset structure by setting an offset length to a specific range when performing a hydrogenation treatment such as a hydrogen plasma treatment. SOLUTION: A gate electrode 4 is formed near the center of a polysilicon operation layer 2. At this time, by overetching the gate electrode 4, a photo resist film 5 is allowed to project from the edge part of the gate electrode 4 by 0.25 μm in an overhang part. Then, ions are implanted with the photoresist film 5 as a mask. Then, heavily doped regions 6a and 6b that become a source/ drain regions are formed away from the edge part of the gate electrode 4 at both parts of the polysilicon operation layer 2 that is not covered with the photoresist film 5 by Loff. After that, patterning is made, thus forming the source/drain electrodes 8a and 8b connected to the source/drain regions 6a and 6b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT), and more particularly to a technique suitable for use in an active matrix type liquid crystal panel provided with a polysilicon TET using polysilicon as an operation layer.

[0002]

2. Description of the Related Art Conventionally, as a liquid crystal panel, pixel electrodes are formed in a matrix on a glass substrate, and polysilicon is used as an operation layer corresponding to each pixel electrode.
An FT is formed, and a predetermined voltage is applied to each pixel electrode by a TFT to drive a liquid crystal panel or a liquid crystal panel configured to drive a liquid crystal. 2. Description of the Related Art A liquid crystal panel provided integrally with a driving circuit including a TFT for forming a voltage has been put to practical use. Further, in a liquid crystal panel on which a drive circuit is mounted, a liquid crystal panel in which a drive circuit is formed by a so-called CMOS circuit known as a MOS semiconductor integrated circuit in order to reduce power consumption has been put to practical use.

In a liquid crystal panel having a polysilicon TFT as described above, in order to improve the characteristics (breakdown voltage and off-leak current) of the TFT, a source / drain region is formed at a position away from the gate electrode. In some cases, a TFT having the offset structure described above is used. Further, a hydrogen plasma treatment may be performed to compensate for crystal defects of polysilicon serving as an operation layer of the TFT with hydrogen atoms and improve TFT characteristics.

[0004]

When a hydrogen plasma process is applied, a self-aligned TFT having no offset has the advantage that the trap level of polysilicon in the active layer is reduced and the mobility is improved by this process. However, in a TFT having an offset structure, as shown in FIG.
TFT without hydrogen plasma treatment, especially N-channel type TF
It has been found that there is a problem that the on-current of the TFT subjected to the hydrogen plasma treatment is lower than the drain current when T is on (hereinafter, simply referred to as the on-current). In FIG. 5, the curve indicated by the symbol a indicates the drain current characteristic of the N-channel TFT without the hydrogen plasma treatment, and the curve indicated by the symbol A indicates the drain current characteristic of the P-channel TFT subjected to the hydrogen plasma treatment. Show. However, the offsets of the TFTs denoted by a and A are both 0.75 μm.

Accordingly, the present inventors have studied the cause of the decrease in the on-state current of the TFT subjected to the hydrogen plasma treatment as compared with the on-state current of the TFT not subjected to the hydrogen plasma treatment. As a result, it was found that when hydrogen plasma treatment was performed on polysilicon, as shown in FIG. 6, the sheet resistance ρs increased by almost one digit. This is considered because the crystal defect is compensated by hydrogen atoms by the hydrogen plasma treatment, so that the polysilicon at the offset portion approaches the direction of the intrinsic semiconductor.

SUMMARY OF THE INVENTION An object of the present invention is to impair the advantage that, in a semiconductor device having a TFT having an offset structure, the on-current does not decrease even when hydrogen plasma processing is performed, and that the offset structure has a high breakdown voltage and a small off-leak current. To provide a TFT and a manufacturing technique therefor.

[0007]

According to the present invention, in order to attain the above object, in a polysilicon TFT having an offset structure, when a hydrogenation treatment such as a hydrogen plasma treatment is performed, the offset length is desirably 0.25 μm or less. Is set to 0.2 μm or less, more preferably 0.1 μm or less. Note that the hydrogen plasma treatment is an example of the hydrogenation treatment and is not limited thereto.

Conventionally, polysilicon TF having an offset structure
At T, the offset length is generally about 1 μm, and according to the experience of the present inventors, 0.75 μm was considered to be optimal. However, in a polysilicon TFT that performs hydrogen plasma processing, the crystal defect is compensated by hydrogen atoms, so that the polysilicon at the offset portion approaches the direction of the intrinsic semiconductor, so that the sheet resistance increases and the on-current decreases. .

On the other hand, the present invention sets the offset length to 0.
Since the resistance is set to 25 μm or less, preferably 0.2 μm or less, and more preferably 0.1 μm or less, the offset length is set to 1 μm without performing the hydrogen plasma treatment.
m, so that the on-current does not decrease even if the hydrogen plasma treatment is performed, and the advantage that the offset structure has a high withstand voltage and a small off-leak current is not impaired. Can be obtained. Note that the minimum offset length is desirably 0.05 μm or more in relation to the breakdown voltage and the off-leak current.

Further, a first method for obtaining a TFT having the above structure is described.
In this method, a gate electrode is formed by over-etching using a photoresist film as a mask, and ion implantation for forming a source / drain region with respect to a polysilicon operation layer is performed while the photoresist film remains. There is a method of performing a hydrogen plasma treatment after removing the photoresist film serving as a mask.

Further, it is desirable that the over-etching of the gate electrode be performed by dry etching such as reactive ion etching or plasma etching.

As a second method for obtaining the TFT of the present invention, a hydrogen plasma treatment is performed after the formation of the gate electrode, and the surface of the gate electrode is oxidized to form a so-called sidewall. Ion implantation for forming source / drain regions for the semiconductor device.

An anodic oxidation method is suitable as a method for oxidizing the gate electrode.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention and the effectiveness thereof will be described below with reference to the drawings.

FIGS. 1 and 2 show a main part of a process to which the present invention is applied in the order of steps.

1 and 2, reference numeral 1 denotes a glass substrate. In this embodiment, first, a polysilicon layer is formed on a glass substrate 1 to a thickness of, for example, 1000 angstroms by a CVD method or the like. After the amorphous silicon is deposited, the polysilicon layer may be formed by a solid phase growth method or a laser annealing method. Next, by performing patterning by dry etching or the like, an island (2) of a polysilicon layer serving as an operation layer of the TFT is formed at a location where the TFT is to be formed.
TF is formed on the polysilicon operation layer 2 by a CVD method or the like.
A silicon oxide film 3 serving as a T gate insulating film is formed (FIG. 1A).

Thereafter, a conductive layer 4 made of a metal such as aluminum, tantalum, molybdenum, titanium, tungsten or a silicide thereof is formed on the silicon oxide film 3 by sputtering or the like, and a photoresist film is formed thereon. The conductive layer 4 is patterned by dry etching such as reactive ion etching or plasma etching using the remaining photoresist film 5 as a mask by applying, exposing and developing by spinning or the like, as shown in FIG. As shown in FIG.
The gate electrode 4 located substantially at the center is formed.

At this time, by over-etching the gate electrode 4, the photoresist film 5 is left in a state of eaves protruding from the end of the gate electrode 4 by 0.1 to 0.25 μm (FIG. 1 (c)).

Next, using the photoresist film 5 as a mask, an impurity serving as an acceptor such as boron for a P-channel TFT and an impurity serving as a donor such as phosphorus for an N-channel TFT are applied from above the substrate, for example, at 100 Ke.
Ion implantation is performed with energy such as V. Then
A high-concentration region 6 serving as a source / drain region is located at a position Loff away from the end of the gate electrode 4 on both sides of the polysilicon operation layer 2 not covered with the photoresist film 5.
a, 6b are formed (FIG. 2 (d)).

An interlayer insulating film 7 made of a silicon oxide film or BPSG (silicon oxide glass containing boron and phosphorus) is formed so as to cover the gate electrode 4 and the gate insulating film (silicon oxide film 3). Subsequently, heat treatment, lamp annealing, laser annealing, or the like for activating the impurities implanted in the source / drain portions is performed. Then, after removing the photoresist film 5 serving as a mask, a hydrogen plasma treatment is performed (FIG. 2E). Thereby, the crystal defects of the polysilicon operation layer 4 can be compensated by the hydrogen atoms. Note that the above-described hydrogen plasma treatment is performed using a parallel plate type plasma C.
The etching can be performed by using a VD apparatus or an RIE type plasma etching apparatus.
Power: 1-2 kW, electrode spacing: 2-10 cm, set temperature: 100-300 ° C, H2 gas flow: 200-700
The pressure in the chamber may be set to 0.1 to 2 Torr.

Thereafter, contact holes are formed in the interlayer insulating film 7 and the gate insulating film (silicon oxide film 3), and a conductive layer of aluminum or the like is formed by a sputtering method or the like. Source / drain electrodes 8a and 8b connected to the drain regions (6a and 6b) are formed (FIG. 2 (f)).

In the steps of the above embodiment, the TF constituting a driving circuit such as a shift register provided around the pixel region is used.
The present invention can be applied not only to the manufacturing process of T but also to a pixel switching TFT provided in a pixel region and applying a desired voltage corresponding to an image signal to a pixel electrode.

In the above embodiment, the description has been given of the case where the hydrogen plasma treatment is performed after the activation of the source / train section. Membrane (for example,
It may be performed in any process before the deposition of ITO or the like.

Next, another embodiment of the manufacturing process of the TFT having the offset structure will be described with reference to FIG.

The steps up to the point before FIG. 3B in the process of this embodiment are the same as the steps in FIGS. 1A and 1B. In this embodiment, a gate electrode 4 having the same size as the resist mask 5 is formed without over-etching, and a hydrogen plasma process is performed in the state shown in FIG. Thereafter, an oxide film 9 is formed on the surface of the gate electrode 4 by an anodic oxidation method or the like (FIG. 4D). Then, using the oxide film 9 as a mask, an impurity serving as an acceptor such as boron for a P-channel TFT and an impurity serving as a donor such as phosphorus for an N-channel TFT are ion-implanted from above the substrate with an energy such as 100 KeV. I do. Then, high-concentration regions 6a and 6b serving as source / drain regions are formed at positions on both sides of the polysilicon operation layer 2 that are not covered with the resist mask 5 and away from the ends of the gate electrode 4 by Loff (FIG. 4
(e)).

Thereafter, the same processing as that of the step of FIG. 2 (f) of the above embodiment is carried out, so that the source / drain electrodes 8a, 8b connected to the interlayer insulating film 8 and the high-concentration N-type regions 6a, 6b are formed. Is formed (FIG. 4F).

FIG. 5 shows the P formed by the above embodiment.
The result of measuring the characteristic of the drain current Ids of the channel TFT is shown corresponding to the magnitude of the offset length Loff. In the figure, reference symbol B denotes a drain current characteristic when the offset length Loff is 0.50 μm, reference symbol C denotes a drain current characteristic when the offset length Loff is 0.25 μm, and reference symbol B denotes a drain current characteristic when the offset length Loff is 0. Shows the drain current characteristics of the respective samples. In FIG. 5, the drain current characteristic measured for a TFT having an offset of 0.75 μm and not subjected to the hydrogen plasma treatment is indicated by a symbol a. As shown in the figure, when the offset length Loff is 0.25 μm or less, the drain current characteristic shows that the offset is 0.75 μm.
It can be understood that the drain current characteristic becomes equal to or higher than that of the TFT not subjected to the hydrogen plasma treatment.

FIG. 7 shows a liquid crystal panel 100 in which a driving circuit comprising the TFT of the above embodiment is provided around the pixel area.
1 shows a system configuration example of the TFT-side substrate. In the figure,
Reference numerals 90 denote pixels arranged corresponding to intersections of the gate lines 21 and the signal lines 22 which are arranged so as to cross each other. Each pixel 90 has a pixel electrode 14 made of ITO or the like and a signal applied to the pixel electrode 14. And a TFT 91 for applying a voltage corresponding to the image signal on the line 22. T in the same row (Y direction)
The FT 91 has a gate connected to the same gate line 21 and a drain connected to the corresponding pixel electrode 14. The sources of the TFTs 91 in the same column (X direction) are connected to the same signal line 22. In this embodiment, the transistors constituting the driving circuits (X and Y shift registers and sampling means) 50 and 60 around the pixel area and the TFTs for driving the pixels are both so-called polysilicon TFTs having a polysilicon layer as an operation layer. The transistors constituting the peripheral driving circuits 50 and 60 and the pixel driving TFT are formed almost simultaneously by the same process.

In this embodiment, a shift register (hereinafter referred to as an X shift register) 51 for sequentially selecting the signal lines 22 is arranged on one side (upper side in the figure) of a pixel area (pixel matrix) 20. On the other side, a shift register (hereinafter referred to as a Y shift register) 61 for sequentially selecting and driving the gate lines 21 is provided. A buffer 63 is provided as necessary at the next stage of the Y shift register 61. A sampling switch (TFT) 52 is provided at the other end of each of the signal lines 22. These sampling switches 52 Image signals VID1 to VID1 input to the external terminals 74, 75, 76
It is connected between video lines 54, 55, and 56 for transmitting VID3, and is configured to be sequentially turned on / off by a sampling pulse output from the X shift register 51. The X shift register 51 has a terminal 7
Clock CLX externally input via the external clocks 2 and 73
1, sampling pulses X1, X2, X3,... Xn for sequentially selecting all signal lines 3 once during one horizontal scanning period on the basis of CLK2 and control terminals of a sampling switch 52. To supply. On the other hand, the Y shift register 61 is operated in synchronization with clocks CLY1 and CLY2 input from the outside via terminals 77 and 78, and sequentially drives the gate lines 2.

FIG. 8 shows a configuration example of a liquid crystal panel 30 to which the liquid crystal panel substrate is applied. As shown in the figure, on the liquid crystal panel substrate (TFT array substrate) 10, an image is displayed by a pixel region regulated by a plurality of pixel electrodes 23 (actually, the orientation state of the liquid crystal layer 37 changes). A seal member 36 made of a photocurable resin is provided along the pixel region as an example of a seal member that surrounds the liquid crystal layer 37 by bonding the two substrates together around the (liquid crystal panel region). Further, a light-shielding peripheral parting layer 35 is provided on a portion of the incident side counter substrate 31 having the color filter layer 33 corresponding to the above-mentioned pixel region outside seal material 36 inside region.

When the liquid crystal panel substrate 10 is set in a light-shielding case in which an opening is formed corresponding to an image region later, the peripheral parting layer 35 may have a problem in that the pixel region may not be formed due to a manufacturing error or the like. A band-shaped light-shielding material having a width of about 500 μm and 1 mm around the pixel area so as not to be hidden by the edge of the opening, that is, for example, to allow about several hundred μm as a deviation from the case of the liquid crystal panel substrate 10. It is formed. Such a light-shielding peripheral parting layer 35 is made of, for example, Cr (chromium), Ni (nickel),
The counter substrate 31 is formed by sputtering, photolithography, and etching using a metal material such as Al (aluminum). Instead of the above metal materials,
The peripheral parting layer 35 may be formed of a material such as resin black in which carbon or Ti (titanium) is dispersed in a photoresist.

A peripheral circuit (scanning line drive circuit) 50 and a pad 70 as an external terminal are provided along the lower side of the pixel region in a region outside the sealing member 36, and are provided on both sides (two right and left sides in the figure) of the pixel region. A peripheral circuit (signal line driving circuit) 60 is provided along the side. Further, wirings 105 for electrically connecting the peripheral circuits 60 provided on both sides of the pixel region are provided on the upper side of the pixel region. Columns 106 made of a conductive source voltage material for establishing electrical continuity between the liquid crystal panel substrate 10 and the counter substrate 31 are provided at the four corners of the seal material 36. The counter substrate 31 having substantially the same contour as the sealing material 36
Are fixed to the liquid crystal panel substrate 10 by the sealing material 36.

FIG. 9 shows another configuration example of the liquid crystal panel 30 to which the liquid crystal panel substrate is applied. The liquid crystal panel 30 of the embodiment shown in FIG. 9 has an incident side glass substrate 3 having a color filter layer 33 on the surface side of the liquid crystal panel substrate 10.
1 are arranged at appropriate intervals, and the periphery thereof is a sealing material 36.
TN (Twisted Nematic) liquid crystal in the gap sealed with
Or liquid crystal 3 such as SH (Super Homeotropic) type liquid crystal
7 is filled to form a liquid crystal panel 30. The upper part of the peripheral circuits 50 and 60 is configured to be shielded from light by a black mask or the like provided on the counter substrate 31, for example. The position where the sealing material is provided is determined so that the pad 70 as an external terminal for inputting a signal from the outside is located outside the sealing material 36. Reference numeral 38 denotes a liquid crystal injection port provided on the counter substrate 31 side.

Next, an electronic apparatus using the liquid crystal device of the above-described embodiment is provided with a display information output source 10 shown in FIG.
00, display information processing circuit 1002, display drive circuit 100
4, a display panel 1006 such as a liquid crystal panel, a clock generation circuit 1008, and a power supply circuit 1010. The display information output source 1000 includes a memory such as a ROM or a RAM, a tuning circuit that tunes and outputs a television signal, and the like, and outputs display information such as a video signal based on a clock from a clock generation circuit 1008. I do. The display information processing circuit 1002 includes a clock generation circuit 1
The display information is processed and output based on the clock from 008. The display information processing circuit 1002 can include, for example, an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, a clamp circuit, and the like. The display driving circuit 1004 includes a scanning side driving circuit and a data side driving circuit, and drives the liquid crystal panel 1006 for display. The power supply circuit 1010 supplies power to each of the above circuits.

As an electronic apparatus having such a configuration, FIG.
, A personal computer (PC) and an engineering workstation (EWS) for multimedia shown in FIG. 12, a pager shown in FIG. 13, or a mobile phone, a word processor, a television, a viewfinder type video or a monitor direct view type video. Examples include a tape recorder, an electronic organizer, an electronic desk calculator, a car navigation device, a POS terminal, and a device having a touch panel.

FIG. 11 is a schematic configuration diagram showing a main part of the projection display device. In the figure, 10 is a light source, 13 and 14 are dichroic mirrors, 15, 16 and 17 are reflection mirrors, 1
8, 19, and 20 indicate relay lenses, 22, 23, and 24 indicate liquid crystal light valves, 25 indicates a cross dichroic prism, and 26 indicates a projection lens. The light source 10 includes a lamp 11 such as a metal halide and a reflector 1 that reflects light from the lamp.
Consists of two. The dichroic mirror 13 that reflects blue light and green light transmits red light of the white light flux from the light source 10 and reflects blue light and green light. The transmitted red light is reflected by the reflection mirror 17 and enters the red light liquid crystal light valve 22. On the other hand, green light of the color light reflected by the dichroic mirror 13 is reflected by the dichroic mirror 14 that reflects green light, and is incident on the liquid crystal light valve 23 for green light. On the other hand, the blue light also passes through the second dichroic mirror 14. For blue light, in order to prevent light loss due to a long optical path, a light guide means 21 including a relay lens system including an incident lens 18, a relay lens 19, and an exit lens 20 is provided. The light enters the liquid crystal light valve 24 for light. The three color lights modulated by the respective light valves enter the cross dichroic prism 25. This prism has four right-angle prisms bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface. The three color lights are combined by these dielectric multilayer films to form light representing a color image. The synthesized light is projected on a screen 27 by a projection lens 26 which is a projection optical system,
The image is displayed enlarged.

The personal computer 12 shown in FIG.
00 is a main body 1204 having a keyboard 1202
And a liquid crystal display screen 1206.

A pager 1300 shown in FIG. 13 includes a liquid crystal display substrate 1304, a light guide 1306 having a backlight 1306a, a circuit board 1308, and first and second shield plates 1310 and 13 in a metal frame 1302.
12, two elastic conductors 1314 and 1316, and a film carrier tape 1318. Two elastic conductors 1314 and 1316 and film carrier tape 13
Reference numeral 18 denotes a connection between the liquid crystal display substrate 1304 and the circuit board 1308.

Here, the liquid crystal display substrate 1304 has liquid crystal sealed between two transparent substrates 1304a and 1304b, thereby forming at least a dot matrix type liquid crystal display panel. On one transparent substrate, FIG.
Or a display information processing circuit 1002 in addition to the above. Circuits not mounted on the liquid crystal display substrate 1304 are external circuits of the liquid crystal display substrate, and can be mounted on the circuit substrate 1308 in the case of FIG.

FIG. 13 shows the configuration of the pager, and therefore requires a circuit board 1308 in addition to the liquid crystal display substrate 1304. In this case, a liquid crystal display device is used as one component for electronic equipment. When a display driving circuit or the like is mounted on a transparent substrate, the minimum unit of the liquid crystal display device is the liquid crystal display substrate 1304. Alternatively, a structure in which the liquid crystal display substrate 1304 is fixed to a metal frame 1302 serving as a housing can be used as a liquid crystal display device which is one component for electronic devices. Further, in the case of a backlight type, a liquid crystal display substrate 1304 and a light guide 1306 provided with a backlight 1306a can be incorporated in a metal frame 1302 to constitute a liquid crystal display device. Instead of these, as shown in FIG.
Two transparent substrates 130 constituting the liquid crystal display substrate 1304
4a and 1304b, a TCP (Tape Carrier Package) in which an IC chip 1324 is mounted on a polyimide tape 1322 on which a metal conductive film is formed.
e) 1320 can be connected to be used as a liquid crystal display device, which is one component for electronic equipment.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, the present invention is not limited to being applied to the driving of the above-described various liquid crystal panels, but is also applicable to electroluminescence and plasma display devices.

[0042]

As described above, according to the present invention, in a polysilicon TFT having an offset structure, when a hydrogenation treatment such as a hydrogen plasma treatment is performed, the offset length is set to 0.25 μm or less, preferably 0.2 μm or less. More desirably, the resistance is set to 0.1 μm or less, so that the resistance value of the offset portion can be made approximately the same as when the offset length is set to about 1 μm without performing the hydrogen plasma processing. Even if it is carried out, the advantage that the ON current does not decrease and the advantage that the OFF leakage current is small due to the high withstand voltage due to the offset structure is maintained.
There is an effect that FT can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one embodiment of a TFT manufacturing process (first half) to which the method of the present invention is applied, in the order of steps.

FIG. 2 is a cross-sectional view showing one embodiment of a TFT manufacturing process (second half) to which the method of the present invention is applied, in the order of steps.

FIG. 3 is a sectional view showing another manufacturing process (first half) of a TFT to which the method of the present invention is applied, in the order of steps;

FIG. 4 is a cross-sectional view showing another manufacturing process (second half) of a TFT to which the method of the present invention is applied, in the order of steps.

FIG. 5 is a characteristic diagram showing a relationship between a gate-source voltage and a drain current in a TFT having an offset structure.

FIG. 6 is a characteristic diagram showing a relationship between illuminance of irradiation light and a sheet resistance value before and after a hydrogen plasma treatment in a polysilicon layer serving as a TFT operation layer.

FIG. 7 is a block diagram showing a system configuration example of a liquid crystal panel substrate suitable for applying the present invention.

8A and 8B are a cross-sectional view and a plan view illustrating a configuration example of a liquid crystal panel using the liquid crystal panel substrate according to the present invention.

9A and 9B are a plan view and a cross-sectional view illustrating another configuration example of the liquid crystal panel using the liquid crystal panel substrate according to the present invention.

FIG. 10 is a diagram illustrating a configuration of an electronic device of the invention.

FIG. 11 is a diagram illustrating a configuration of a projection display device which is an example of the electronic apparatus of the invention.

FIG. 12 illustrates an example of an electronic device of the invention.

FIG. 13 illustrates an example of an electronic device of the invention.

FIG. 14 illustrates an example of an electronic device of the invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Insulating substrate (glass substrate) 2 Polysilicon layer (TFT working layer) 3 Gate insulating film 4 Gate electrode 5 Photoresist film 6a, 6b Source / drain region of TFT 7 Interlayer insulating film 8a, 8b Source / drain electrode 9 Oxidation Film 20 Pixel region 30 Liquid crystal panel 31 Counter substrate 33 Counter electrode 36 Sealing material 37 Liquid crystal 50, 60 Peripheral circuit 51 X shift register 52 Sampling switch 54 to 56 Video line 61 Y shift register 72 to 78 External terminal 90 Pixel 91 Pixel drive For TFT 100 Substrate for liquid crystal panel

Claims (12)

[Claims] 1. A source / drain region is formed in a polycrystalline semiconductor layer opposed to a gate electrode via an insulating film, at a position apart from both ends of the gate electrode, and hydrogenation is performed on the polycrystalline semiconductor layer. A thin film transistor to be processed, wherein a distance between the gate electrode and the source / drain region is 0.25 μm or less. 2. The thin film transistor according to claim 1, wherein a distance between the gate electrode and the source / drain region is 0.2 μm or less. 3. The thin film transistor according to claim 2, wherein a distance between the gate electrode and the source / drain region is 0.15 μm or less. 4. The thin film transistor according to claim 1, wherein the hydrogenation treatment is a treatment using hydrogen plasma. 5. A step of forming a polycrystalline semiconductor layer on a substrate, a step of forming an insulating film on the polycrystalline semiconductor layer,
Forming a gate electrode on the insulating film using a photoresist film as a mask and over-etching the gate electrode; and separating from the both ends of the gate electrode of the polycrystalline semiconductor layer using the photoresist film as a mask. Ion implantation of impurities into the
A method for manufacturing a thin film transistor, comprising: forming a high-concentration region serving as a drain region; and hydrogenating the polycrystalline semiconductor layer after removing the photoresist film. 6. The method according to claim 5, wherein the hydrogenation process is a process using hydrogen plasma. 7. A step of forming a polycrystalline semiconductor layer on a substrate, a step of forming an insulating film on the polycrystalline semiconductor layer,
Forming a gate electrode on the insulating film using a photoresist film as a mask, removing the photoresist film and then performing a hydrogenation treatment on the polycrystalline semiconductor layer, and forming an oxide film on the gate electrode surface Forming a high-concentration region serving as a source / drain region by ion-implanting impurities into the polycrystalline semiconductor layer at positions separated from both ends of the gate electrode using the oxide film as a mask. A method for manufacturing a thin film transistor, comprising: 8. The method according to claim 7, wherein the hydrogenation process is a process using hydrogen plasma. 9. The method according to claim 7, wherein the oxide film is formed by an anodic oxidation method. 10. A pixel electrode is arranged in a matrix on a substrate, and is applied to the pixel electrode and the transistor in the vicinity of a pixel region where a transistor for applying a voltage to each pixel electrode is formed corresponding to each pixel electrode. A liquid crystal panel substrate on which a drive circuit for generating a voltage is arranged, wherein the drive circuit is constituted by the thin film transistor according to claim 1. 11. The liquid crystal panel substrate according to claim 10 and a transparent substrate having a counter electrode are arranged at an appropriate interval, and are disposed in a gap between the liquid crystal panel substrate and the transparent substrate. A liquid crystal device in which liquid crystal is sealed. 12. An electronic apparatus comprising the liquid crystal device.