JPH11177094A - Semiconductor thin film transistor and semiconductor thin film transistor array substrate including semiconductor thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a TFT (semiconductor thin film transistor) having a structure in which on-resistance of the TFT can be reduced, and a TFT array substrate in which a TFT-LCD can be realized high display quality by improving driving capability and the uniformity of TFT characteristics in a display face. SOLUTION: This TFT is constituted of a gate electrode 2 on an insulating substrate (glass substrate 1), gate insulating film 3 on the gate electrode 2, a first n-type semiconductor layer (first n-layer 5a) including n-type impurity on the gate insulating film 3, an intrinsic semiconductor layer (i-layer 4) on the first n-layer 5a, a second n-type semiconductor layer (second n-layer 5b) including n-type impurity on the i-layer 4, and a source electrode 9 and a drain electrode 7 made of metal on the second n-layer 5b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor thin film transistor used for a matrix type display device and a semiconductor thin film transistor array substrate including the semiconductor thin film transistor.

[0002]

2. Description of the Related Art A matrix type display device generally includes a semiconductor thin film transistor array substrate (hereinafter, referred to as a "TFT array substrate"), a counter substrate, and a liquid crystal display provided between the TFT array substrate and the counter substrate. The display material is configured to selectively apply a voltage to the display material.

[0003] The counter substrate comprises, for example, a transparent insulating substrate, a color filter and a black matrix provided on the insulating substrate.

On the other hand, the TFT array substrate includes, for example, a transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film formed on the gate wiring, A plurality of source wirings intersecting with the gate wiring via a gate insulating film; a semiconductor thin film transistor (hereinafter, referred to as a “TFT”) provided at an intersection of the gate wiring and the source wiring; And a pixel electrode made of a transparent conductive film, and a storage capacitor electrode line (hereinafter, referred to as “Cs wiring”) that forms a storage capacitor by opposing the pixel electrode via an insulating film. Note that instead of providing a Cs wiring, a storage capacitor may be formed by forming a gate wiring so as to face a pixel electrode with an insulating film interposed therebetween.

The TFT includes, for example, a gate electrode formed on an insulating substrate, a gate insulating film formed on the gate electrode, and an n-type impurity formed on the gate insulating film and containing n-type impurities. Type semiconductor layer (hereinafter, referred to as “n layer”)
And an intrinsic semiconductor layer (hereinafter, referred to as an “i-layer”) formed on the n-type semiconductor layer, and a source electrode and a drain electrode made of a metal formed on the intrinsic semiconductor layer.

FIG. 5 is an explanatory diagram showing an example of an equivalent circuit of a conventional TFT array substrate. In FIG. 5, 10 is T
FT, 11 is a storage capacity (hereinafter referred to as “Cs capacity”),
51 _G1 , _51G2 , and _51G3 are gate wirings ("scanning signal lines").
, 52 _S3 , 52 _S2 , 52 _S1 are source wirings (also called “video signal lines”), 53 _Cs1 , 5
3 _Cs2 and 53 _Cs3 indicate Cs wirings. Each pixel includes a gate line 51 _G1 , 51 _G2 , 51 _G3 and a source line 52 _S1 ,
52 _S2 and 52 _S3 are defined as boundaries. Note that for simplicity, FIG. 5 shows only nine pixels.

A pixel electrode (not shown) is made of ITO (indium).
It is a transparent electrode made of tin oxide). TFT10
Are provided as switching elements, and control charging and discharging of charges to the pixel electrodes. The TFT 10 is turned on and off by the gate signal input to the gate lines 51 _G1 , 51 _G2 , 51 _G3 being input to each TFT 10. The gate wirings 51 _G1 , 51 _G2 , 51 _G3
The part electrically connected to the TFT 10 functions as a gate electrode. Further, the pixel electrode is electrically connected to each of the source wirings 52 _S1 , 52 _S2 , 52 _S3 via the TFT 10. Note that a portion of the source wiring which is electrically connected to the TFT 10 functions as a source electrode.

[0008] Depending on the level of the video signal input to the source wiring, the amount of charge charged to the pixel electrode changes, and the potential of the pixel electrode is set. When the counter electrode is provided on the counter substrate, the displacement amount of the liquid crystal array changes for each pixel according to the potential difference between the pixel electrode and the counter electrode, and the transmitted light amount of light emitted from the back surface of the display device changes. . Therefore, by controlling the signal level of the source wiring, the transmitted light amount of each pixel is selectively changed, and the change is displayed as an image.

In order to improve the quality of an image, it is necessary to minimize fluctuations in the potential of each pixel due to a change in the signal level of a scanning signal input to a gate wiring or the like. In order to reduce the fluctuation of the potential, a Cs capacitance 1
1 may be provided to increase the total capacity of each pixel.
The Cs capacitor 11 is formed by providing a Cs wiring having the same potential as the counter electrode on the pixel electrode via an insulating film.

Next, an example of a layout of each pixel of the conventional TFT array substrate will be described. FIG. 6 is an explanatory diagram showing an example of one pixel included in a conventional TFT array substrate and its peripheral portion. Further, FIG. 7 illustrates the T
FIG. 3 is a cross-sectional explanatory view of the FT along the line AA. 6 and 7, 1 is a glass substrate, 2 is a gate electrode, 3 is a gate insulating film, 4 is an i layer, 5 is an n layer, 6 is a pixel electrode, 7 is a drain electrode, 8 is a source electrode, and 9 is An insulating film, 13 is a gate wiring, 14 is a source wiring, 15 is a Cs wiring, and 16 is a semiconductor layer composed of an i-layer and an n-layer.

Next, the conventional TFT array substrate TFT
An example of the production method will be described. 8, 9, 10, and 11 are process cross-sectional views showing an example of a conventional TFT being manufactured. 8, 9, 10, and 11, the same portions as those in FIGS. 6 and 7 are denoted by the same reference numerals.

First, as shown in FIG. 8A, a metal film 82 serving as a gate electrode is formed on the glass substrate 1, and as shown in FIG. 8B, the resist pattern 80 is developed. The gate electrode 2 is formed by etching the metal film 82. After removing the resist pattern, FIG.
As shown in (c), a gate insulating film 3, a first semiconductor layer 84 to be an i-layer, and a second semiconductor layer 85 to be an n-layer are formed from below. Next, as shown in FIG. 9A, the resist pattern 80 is developed, and the first semiconductor layer 84 and the second semiconductor layer 85 are etched to form the i-layer 4 and the n-layer 5. After removing the resist pattern, an ITO thin film 86 serving as a pixel electrode is formed as shown in FIG. 9B, and the resist pattern 80 is developed as shown in FIG. 86
Is etched to form a pixel electrode 6. After removing the resist pattern, a metal film 87 to be a source electrode and a drain electrode is formed as shown in FIG. 10A, and the resist pattern 80 is developed as shown in FIG. Then, the metal film 87 is etched to form the source electrode 7 and the drain electrode 8. Furthermore, TF
After etching all of the n-layer 5 and a part of the i-layer 4 on the back channel side of T (also referred to as “back channel etching”), and removing the resist pattern as shown in FIG. As shown in FIG. 11B, an insulating film 9 is formed. Note that a TFT on which the back channel etching is performed during the manufacturing process is called a back channel etching type TFT.

Next, the structure and function of a conventional TFT will be described with reference to the drawings. TF shown in FIG.
At T, the case where the pixel electrode 6 is charged with electric charge will be described. The TFT is turned on by applying a positive voltage of, for example, about 20 V to the gate electrode 2. At this time, by applying a voltage of, for example, about 9 V to the source electrode 8, the drain electrode 7 and the pixel electrode 6 are charged to near 9V. Thereafter, when the potential of the pixel electrode has risen sufficiently, the gate electrode 2
Then, a negative voltage of about -5 V is applied to turn off the TFT. As a result, the charge is charged in the pixel electrode, and the charge is confined in the pixel including the pixel electrode.

In the operation relating to the above-described charge charging, the degree of increase in the potential of the pixel electrode depends on the magnitude of the pixel capacitance including the Cs capacitance connected to the pixel electrode 6, and the on-resistance of the TFT (the TFT in the on-state). Resistance value). FIG. 12 is an explanatory sectional view showing the vicinity of the channel of the TFT of FIG. FIG. 13 is an explanatory diagram equivalently showing the resistance of the TFT in FIG. 12 and 13, the same parts as those in FIG. 7 are denoted by the same reference numerals. FIG. 14 is an explanatory diagram showing the resistance of FIG. In a conventional TFT, the on-resistance of the TFT can be considered by cutting out a cross section near the channel of the TFT as shown in FIG. 12 and corresponding to the cross-sectional structure as shown in FIG. 13, and separating the resistance for each component. . That is, as the on-resistance,
A resistance (Rss) 131 on the source electrode side, a resistance (Rsc) 132 on the channel portion, and a resistance (Rsd) 1 on the drain electrode side
There are 33. The drain electrode 7 and the source electrode 8 are made of metal, and the resistance of the n layer 5 provided below the drain electrode 7 and the source electrode 8 is sufficiently smaller than the above-mentioned Rss131, Rsc132 and Rsd133. This is a level that can be ignored as the on-resistance of the TFT. Therefore, as shown in FIG. 14, the TFT in a state where a voltage is applied to the gate electrode has an R on the drain electrode side.
sd133, Rsc132 on the channel part, R on the source electrode side
It is shown as an equivalent circuit connecting ss131. Conventional T
In the FT, since Rss131 and Rsd133 are large, there is a problem that the ON resistance is large and the pixel electrode cannot be sufficiently charged within a predetermined time. When the thickness of the i-layer is reduced for the purpose of reducing Rss131 and Rsd133, a part of the i-layer to be left as a channel portion is etched during the back channel etching, and the i-layer of the remaining channel portion is etched. The thickness is smaller than the thickness of the i-layer below the source electrode or the drain electrode.

FIG. 15 shows the thickness of the remaining i-layer (i-layer remaining thickness).
4 is a graph showing a relationship between the resistance of the channel portion (Rsc). In FIG. 15, the vertical axis represents Rsc (au), and the horizontal axis represents the remaining i-layer thickness (nm).

As shown in FIG. 15, when the thickness of the remaining i-layer in the channel portion is reduced, the resistance Rsc in the channel portion increases, and the on-resistance of the TFT as a whole cannot be reduced. Therefore, the conventional TFT structure has a problem that it is difficult to reduce Rsc and Rss and to improve TFT characteristics.

[0017]

(1) In the conventional TFT structure on the TFT array substrate, a large series resistance is connected to the source electrode side and the drain electrode side of the TFT, and the on-resistance of the TFT is high. . Therefore, the time required to charge a pixel to a predetermined potential is long. Furthermore, as the number of gate lines of a TFT-LCD (liquid crystal display device including a TFT) increases from XGA (168 lines) to SXGA (1024 lines) and UXGA (1200 lines), it is allocated per pixel. The charging time is shorter. As a result, it becomes difficult to sufficiently charge the battery within a predetermined time, and the display quality is degraded.

(2) The TFT characteristics are greatly affected by the thickness of the i-layer below the source electrode or the drain electrode and the remaining thickness of the i-layer. In the back channel etching, it is necessary to remove all the back channel side n-layers of all TFTs in the substrate surface at a position corresponding to the display area of the LCD. Therefore, usually, it is necessary to consider the film thickness distribution and the etching distribution of the n-layer and to set the etching time to be considerably longer than the time required to remove all the n-layers having the average thickness. As a result, the i-layer in the channel portion of the TFT is also etched deeply, and the distribution of the remaining i-layer thickness becomes non-uniform. When the remaining thickness of the i-layer in the channel portion after the back channel etching is reduced, the resistance of the channel portion is increased as shown in FIG. 15, so that the i-layer cannot be made very thin. That is, the thickness of the i-layer needs to be equal to or greater than a certain thickness of the i-layer remaining thickness of the channel portion after the channel etching. However, when the thickness of the i-layer is increased, there is a structural problem that the series resistance on the source electrode side and the drain electrode side increases as described in (1) above.

The present invention has been made in order to solve the above-mentioned problems, and provides a TFT having a structure capable of reducing the on-resistance of the TFT, and has a driving capability and uniformity of TFT characteristics in a display surface. It is an object of the present invention to provide a TFT array substrate capable of realizing a TFT-LCD with high display quality by increasing the quality.

[0020]

According to the present invention, there is provided a TFT comprising a gate electrode formed on an insulating substrate, a gate insulating film formed on the gate electrode, and a gate insulating film formed on the gate insulating film. A first n-type semiconductor layer containing an n-type impurity, an intrinsic semiconductor layer formed on the n-type semiconductor layer, and a second n-type semiconductor containing an n-type impurity formed on the intrinsic semiconductor layer And a source electrode and a drain electrode made of a metal formed on the second n-type semiconductor layer.

The TFT of the present invention comprises a gate electrode formed on an insulating substrate, a gate insulating film formed on the gate electrode, and a first intrinsic semiconductor layer formed on the gate insulating film. A first n-type semiconductor layer containing n-type impurities formed on the first intrinsic semiconductor layer, a second intrinsic semiconductor layer formed on the first n-type semiconductor layer, A second n-type impurity including an n-type impurity formed on the second intrinsic semiconductor layer;
And a source electrode and a drain electrode made of metal formed on the second n-type semiconductor layer.

The TFT of the present invention has a gate electrode formed on an insulating substrate, a gate insulating film formed on the gate electrode, and an n-type semiconductor layer including an uppermost layer containing an n-type impurity. At least one intrinsic semiconductor layer and a plurality of n-type semiconductor layers alternately formed on the gate insulating film, and a source electrode and a drain electrode made of a metal formed on the uppermost n-type semiconductor layer. Things.

In the TFT of the present invention, a gate electrode formed on an insulating substrate, a gate insulating film formed on the gate electrode, and an n-type semiconductor layer containing an n-type impurity as the uppermost layer are formed. A plurality of intrinsic semiconductor layers and a plurality of n-type semiconductor layers alternately formed on the gate insulating film, and a source electrode and a drain electrode made of a metal formed on the uppermost n-type semiconductor layer. It is.

According to the TFT array substrate of the present invention, a transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film formed on the gate wiring, A plurality of source wirings intersecting with the gate wiring through a film, a TFT provided at an intersection of the gate wiring and the source wiring, a pixel electrode electrically connected to the TFT and made of a transparent conductive film, A TF for a matrix type display device comprising a storage capacitor electrode line which forms a storage capacitor by opposing the pixel electrode via an insulating film.
A T-array substrate, wherein the TFT is a back channel etch type TFT according to claim 1.

[0025] The TFT array substrate of the present invention comprises a transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film formed on the gate wiring, and a gate insulating film. A plurality of source wirings intersecting with the gate wiring through a film, a TFT provided at an intersection of the gate wiring and the source wiring, and a transparent conductive film electrically connected to the TFT and comprising an insulating film. A TFT array substrate for a matrix-type display device, comprising a pixel electrode that forms a storage capacitor by being opposed to a gate wiring through the TFT, wherein the TFT is a back-channel-etch TFT according to claim 1.

The TFT array substrate according to the present invention comprises a transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film formed on the gate wiring, and a gate insulating film. A plurality of source wirings intersecting with the gate wiring through a film, a TFT provided at an intersection of the gate wiring and the source wiring, a pixel electrode electrically connected to the TFT and made of a transparent conductive film, A TF for a matrix type display device comprising a storage capacitor electrode line which forms a storage capacitor by opposing the pixel electrode via an insulating film.
A T array substrate, wherein the TFT is a back channel etch type TFT according to claim 2.

[0027] The TFT array substrate of the present invention comprises a transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film formed on the gate wiring, and a gate insulating film. A plurality of source wirings intersecting with the gate wiring through a film, a TFT provided at an intersection of the gate wiring and the source wiring, and a transparent conductive film electrically connected to the TFT and comprising an insulating film. A TFT array substrate for a matrix type display device comprising a pixel electrode which forms a storage capacitor by being opposed to a gate wiring through the TFT, wherein the TFT is a back channel etch type TFT according to claim 2.

[0028] The TFT array substrate of the present invention comprises a transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film formed on the gate wiring, and a gate insulating film. A plurality of source wirings intersecting with the gate wiring through a film, a TFT provided at an intersection of the gate wiring and the source wiring, a pixel electrode electrically connected to the TFT and made of a transparent conductive film, A TF for a matrix type display device comprising a storage capacitor electrode line which forms a storage capacitor by opposing the pixel electrode via an insulating film.
A T-array substrate, wherein the TFT is a back channel etch type TFT according to claim 3.

According to the TFT array substrate of the present invention, a transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film formed on the gate wiring, A plurality of source wirings intersecting with the gate wiring through a film, a TFT provided at an intersection of the gate wiring and the source wiring, and a transparent conductive film electrically connected to the TFT and comprising an insulating film. A TFT array substrate for a matrix type display device, comprising a pixel electrode which forms a storage capacitor by being opposed to a gate wiring through the TFT, wherein the TFT is a back channel etch type TFT according to claim 3.

According to the TFT array substrate of the present invention, a transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film formed on the gate wiring, A plurality of source wirings intersecting with the gate wiring through a film, a TFT provided at an intersection of the gate wiring and the source wiring, a pixel electrode electrically connected to the TFT and made of a transparent conductive film, A TF for a matrix type display device comprising a storage capacitor electrode line which forms a storage capacitor by opposing the pixel electrode via an insulating film.
A T-array substrate, wherein the TFT is a back channel etch type TFT according to claim 4.

According to the TFT array substrate of the present invention, a transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film formed on the gate wiring, A plurality of source wirings intersecting with the gate wiring through a film, a TFT provided at an intersection of the gate wiring and the source wiring, and a transparent conductive film electrically connected to the TFT and comprising an insulating film. A TFT array substrate for a matrix type display device, comprising a pixel electrode which forms a storage capacitor by being opposed to a gate wiring through the TFT, wherein the TFT is a back channel etch type TFT according to claim 4.

[0032]

Next, embodiments of the TFT of the present invention and a TFT array substrate including the TFT will be described.

Embodiment 1 Embodiment 1 of a TFT of the present invention and a TFT array substrate including the TFT will be described with reference to the drawings.

FIG. 1 is an explanatory sectional view showing Embodiment 1 of the TFT of the present invention. 1, the same portions as those in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted. In addition, 5
a indicates a first n-layer and 5b indicates a second n-layer. The TFT according to the present embodiment is the same as the conventional TFT except that the semiconductor layer includes a plurality of n layers and at least one i layer. That is, the TFT according to the present embodiment
Is that the semiconductor layers are the first n-layer 5a, the i-layer 4, and the second n-layer 5a.
It consists of layer 5b. Note that the thickness of the semiconductor layer of the TFT in this embodiment is substantially the same as the thickness of the semiconductor layer of the conventional TFT.

Next, a method of manufacturing a TFT according to the present embodiment will be described.

FIG. 2 is a process cross-sectional view showing a TFT during manufacture according to the first embodiment of the TFT of the present invention. 2, the same parts as those in FIG. 1 are denoted by the same reference numerals. In the method of manufacturing the TFT according to the first embodiment, a conventional TFT is used until the gate electrode 2 is formed on the glass substrate 1.
It is exactly the same as the FT manufacturing method. After the gate electrode 2 is formed, as shown in FIG. 2A, a gate insulating film 3, a first semiconductor layer 21 serving as a first n-layer, and a first semiconductor layer 21 serving as an i-layer are formed on the gate electrode 2. Second semiconductor layer 22 and second n
A third semiconductor layer 23 to be a layer is formed. Next, FIG.
As shown in FIG. 2B, a resist pattern 20 is developed on a portion serving as a channel of the TFT, and as shown in FIG. 2C, a first portion other than the portion covered with the resist pattern is formed.
The semiconductor layer 21, the second semiconductor layer 22, and the third semiconductor layer 23 are etched. After that, a TFT is formed in exactly the same manner as the conventional TFT manufacturing method.

In the TFT of the present embodiment, the thickness of the semiconductor layer is substantially the same as that of the conventional TFT, and the semiconductor layer is composed of two n layers and one i layer. Therefore, the thickness of the i-layer under the source electrode and the drain electrode can be reduced while the thickness of the semiconductor layer remaining in the channel portion after the back channel etching is made the same level as that of the conventional semiconductor layer. As a result, the resistance on the source electrode side and the resistance on the drain electrode side decrease, the on-resistance of the TFT decreases, and the driving capability of the TFT increases.

Further, when a TFT array substrate is formed using the TFTs of the present embodiment and a matrix type display device, for example, a TFT-LCD is formed, a TFT-LCD with high display quality can be obtained.

In the first embodiment, the case where the semiconductor layer is composed of two n-layers and one i-layer has been described. However, the present invention is not limited to this case. What is necessary is just to be formed from the i layer. Note that the uppermost layer of the semiconductor layers is an n-layer.

Embodiment 2 Next, a second embodiment of the TFT of the present invention and a TFT array substrate including the TFT will be described with reference to the drawings.

FIG. 3 is an explanatory sectional view showing Embodiment 2 of the TFT of the present invention. 3, the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In addition, 4
a indicates a first i-layer and 4b indicates a second i-layer. The TFT according to the present embodiment is the same as the conventional TFT except that the semiconductor layer includes a plurality of n layers and a plurality of i layers. That is, in the TFT according to the present embodiment, the semiconductor layers are the first i-layer 4a, the first n-layer 5a, and the second i-layer 4a.
b and the second n-layer 5b. Note that the thickness of the semiconductor layer of the TFT in this embodiment is substantially the same as the thickness of the semiconductor layer of the conventional TFT.

Next, a method of manufacturing a TFT according to the present embodiment will be described.

FIG. 4 is a process sectional view showing a TFT during manufacture according to the second embodiment of the TFT of the present invention. 4, the same parts as those in FIG. 3 are denoted by the same reference numerals. In the method of manufacturing the TFT according to the second embodiment, a conventional TFT is used until the gate electrode 2 is formed on the glass substrate 1.
It is exactly the same as the FT manufacturing method. After the gate electrode 2 is formed, as shown in FIG. 4A, a gate insulating film 3, a first semiconductor layer 41 serving as a first i-layer, and a first n-layer are formed on the gate electrode 2. The second semiconductor layer 42 and the second i
A third semiconductor layer 43 serving as a layer and a fourth semiconductor layer 44 serving as a second n-layer are sequentially formed. Next, FIG.
As shown in FIG. 4, a resist pattern 40 is developed on a portion to be a channel of the TFT, and as shown in FIG. 4C, the first semiconductor layer 41 and the second semiconductor layer other than the portion covered with the resist pattern are formed. The semiconductor layer 42, the third semiconductor layer 43, and the fourth semiconductor layer 44 are etched. After that,
A TFT is formed in exactly the same manner as a conventional TFT manufacturing method.

In the TFT of the present embodiment, the thickness of the semiconductor layer is substantially the same as the thickness of the semiconductor layer of the conventional TFT, and the semiconductor layer is composed of two i layers and two n layers. Therefore, the thickness of the i-layer under the source electrode and the drain electrode can be reduced while the thickness of the semiconductor layer remaining in the channel portion after the back channel etching is made the same level as that of the conventional semiconductor layer. As a result, the resistance on the source electrode side and the resistance on the drain electrode side decrease, the on-resistance of the TFT decreases, and the driving capability of the TFT increases.

Further, when a TFT array substrate is formed using the TFTs of the present embodiment to form a matrix type display device, for example, a TFT-LCD, a TFT-LCD with high display quality can be obtained.

In the second embodiment, the case where the semiconductor layer is composed of two n-layers and two i-layers has been described. However, the present invention is not limited to this, and the semiconductor layer may be composed of a plurality of n-layers and a plurality of i-layers. It may be formed from a layer. Note that the uppermost layer of the semiconductor layers is an n-layer.

[0047]

According to the present invention, the thickness of the i-layer under the source electrode and the drain electrode can be reduced while the thickness of the semiconductor layer remaining in the channel portion after the back channel etching is made the same level as that of the conventional semiconductor layer. it can. Therefore, Rss and Rsd can be reduced without increasing Rsc. Therefore, the on-resistance of the TFT including Rss, Rsc, and Rsd is reduced, and the driving capability of the TFT is improved. As a result, when the number of gate wirings of the TFT-LCD increases from XGA to SXGA and UXGA, even if the time allotted to charge the pixel electrode is shortened, the pixel electrode of the TFT is reduced. It can be charged to a sufficiently high potential, and has an effect that high display quality can be obtained in a TFT-LCD. Also, the etching amount of the conventional back channel remains the same as before,
An i-layer having a sufficient thickness can be secured in the channel portion. As a result, variations in TFT characteristics are small within the substrate surface corresponding to the display area of the LCD, and variations in display characteristics in the TFT-LCD caused by variations in TFT characteristics can be suppressed.

[Brief description of the drawings]

FIG. 1 is an explanatory sectional view showing Embodiment 1 of a TFT of the present invention.

FIG. 2 is an explanatory cross-sectional view showing a process of manufacturing the TFT according to the first embodiment of the present invention;

FIG. 3 is an explanatory sectional view showing Embodiment 2 of the TFT of the present invention.

FIG. 4 is a process cross-sectional view showing a TFT during manufacture according to a second embodiment of the TFT of the present invention.

FIG. 5 is an explanatory diagram showing an example of an equivalent circuit of a conventional TFT array substrate.

FIG. 6 is an explanatory diagram illustrating an example of one pixel included in a conventional TFT array substrate and a peripheral portion thereof.

FIG. 7 is an explanatory cross-sectional view taken along line AA of the TFT shown in FIG. 6;

FIG. 8 is an explanatory process sectional view showing an example of a conventional TFT during manufacturing.

FIG. 9 is an explanatory process sectional view showing an example of a conventional TFT during manufacturing.

FIG. 10 is an explanatory process sectional view showing an example of a conventional TFT being manufactured.

FIG. 11 is an explanatory process sectional view showing an example of a conventional TFT during manufacturing.

12 is an explanatory sectional view showing the vicinity of the channel of the TFT in FIG. 7;

13 is an explanatory diagram equivalently showing the resistance of the TFT in FIG.

FIG. 14 is an explanatory diagram showing the resistance of FIG.

FIG. 15 is a graph showing the relationship between the remaining i-layer thickness and Rsc.

[Explanation of symbols]

 Reference Signs List 1 glass substrate 2 gate electrode 3 gate insulating film 4 i layer 5 n layer 6 pixel electrode 7 drain electrode 8 source electrode 9 insulating film 10 TFT 11 pixel electrode 13 gate wiring 14 source wiring 15 Cs wiring 16 semiconductor layer

Claims (12)

[Claims] 1. A gate electrode formed on an insulating substrate, a gate insulating film formed on the gate electrode, and a first n-type impurity including an n-type impurity formed on the gate insulating film.
A semiconductor layer, an intrinsic semiconductor layer formed on the n-type semiconductor layer, a second n-type semiconductor layer containing an n-type impurity formed on the intrinsic semiconductor layer, and a second n-type semiconductor layer. A back channel etch type semiconductor thin film transistor comprising a source electrode and a drain electrode made of a metal formed on a semiconductor layer. A gate electrode formed on the insulating substrate; a gate insulating film formed on the gate electrode; a first intrinsic semiconductor layer formed on the gate insulating film; A first n-type semiconductor layer containing an n-type impurity formed on the first intrinsic semiconductor layer, a second intrinsic semiconductor layer formed on the first n-type semiconductor layer, and the second intrinsic semiconductor layer. A second n-type semiconductor layer including an n-type impurity formed on the semiconductor layer;
A back channel etch type semiconductor thin film transistor comprising a source electrode and a drain electrode made of a metal formed on the second n-type semiconductor layer. 3. A gate electrode formed on an insulating substrate, a gate insulating film formed on the gate electrode, and the gate insulating film so that the uppermost layer is an n-type semiconductor layer containing an n-type impurity. Back channel etch type comprising at least one intrinsic semiconductor layer and a plurality of n-type semiconductor layers alternately formed on a film, and a source electrode and a drain electrode made of a metal formed on the uppermost n-type semiconductor layer Semiconductor thin film transistor. 4. A gate electrode formed on an insulating substrate, a gate insulating film formed on the gate electrode, and the gate insulating film so that the uppermost layer is an n-type semiconductor layer containing an n-type impurity. A back channel etch type semiconductor comprising a plurality of intrinsic semiconductor layers and a plurality of n-type semiconductor layers alternately formed on a film, and a source electrode and a drain electrode made of a metal formed on the uppermost n-type semiconductor layer Thin film transistor. 5. A transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film formed on the gate wiring, and the gate via the gate insulating film. A plurality of source wirings intersecting wirings, a semiconductor thin film transistor provided at an intersection of the gate wiring and the source wiring, a pixel electrode electrically connected to the semiconductor thin film transistor, and formed of a transparent conductive film; 2. A semiconductor thin film transistor array substrate for a matrix type display device comprising a storage capacitor electrode line forming a storage capacitor by opposing via an insulating film, wherein the semiconductor thin film transistor is a back channel etch type semiconductor thin film transistor according to claim 1. A semiconductor thin film transistor array substrate. 6. A transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film formed on the gate wiring, and the gate via the gate insulating film. A plurality of source wirings intersecting wirings, a semiconductor thin film transistor provided at an intersection of the gate wiring and the source wiring, and a gate wiring which is electrically connected to the semiconductor thin film transistor, is made of a transparent conductive film, and has an insulating film interposed therebetween. 2. A semiconductor thin film transistor array substrate for a matrix type display device, comprising: a pixel electrode forming a storage capacitor by opposing the semiconductor thin film transistor, wherein the semiconductor thin film transistor is a back channel etch type semiconductor thin film transistor according to claim 1. . 7. A transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film formed on the gate wiring, and the gate via the gate insulating film. A plurality of source wirings intersecting wirings, a semiconductor thin film transistor provided at an intersection of the gate wiring and the source wiring, a pixel electrode electrically connected to the semiconductor thin film transistor, and formed of a transparent conductive film; 3. A semiconductor thin film transistor array substrate for a matrix type display device comprising a storage capacitor electrode line forming a storage capacitor by opposing via an insulating film, wherein the semiconductor thin film transistor is a back channel etch type semiconductor thin film transistor according to claim 2. A semiconductor thin film transistor array substrate. 8. A transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film formed on the gate wiring, and the gate via the gate insulating film. A plurality of source wirings intersecting wirings, a semiconductor thin film transistor provided at an intersection of the gate wiring and the source wiring, and a gate wiring which is electrically connected to the semiconductor thin film transistor, is made of a transparent conductive film, and has an insulating film interposed therebetween. 3. A semiconductor thin film transistor array substrate for a matrix type display device comprising a pixel electrode which forms a storage capacitor by being opposed to a semiconductor thin film transistor array substrate, wherein the semiconductor thin film transistor is a back channel etch type semiconductor thin film transistor according to claim 2. . 9. A transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film formed on the gate wiring, and the gate via the gate insulating film. A plurality of source wirings intersecting wirings, a semiconductor thin film transistor provided at an intersection of the gate wiring and the source wiring, a pixel electrode electrically connected to the semiconductor thin film transistor, and formed of a transparent conductive film; 4. A semiconductor thin film transistor array substrate for a matrix type display device comprising a storage capacitor electrode line which forms a storage capacitor by being opposed via an insulating film, wherein the semiconductor thin film transistor is a back channel etch type semiconductor thin film transistor according to claim 3. A semiconductor thin film transistor array substrate. 10. A transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film formed on the gate wiring, and the gate via the gate insulating film. A plurality of source wirings intersecting wirings, a semiconductor thin film transistor provided at an intersection of the gate wiring and the source wiring, and a gate wiring which is electrically connected to the semiconductor thin film transistor, is made of a transparent conductive film, and has an insulating film interposed therebetween. 4. A semiconductor thin film transistor array substrate for a matrix type display device comprising a pixel electrode which forms a storage capacitor by being opposed to a semiconductor thin film transistor array substrate, wherein the semiconductor thin film transistor is a back channel etch type semiconductor thin film transistor according to claim 3. . 11. A transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film formed on the gate wiring, and the gate via the gate insulating film. A plurality of source wirings intersecting wirings, a semiconductor thin film transistor provided at an intersection of the gate wiring and the source wiring, a pixel electrode electrically connected to the semiconductor thin film transistor, and formed of a transparent conductive film; 5. A semiconductor thin film transistor array substrate for a matrix type display device comprising a storage capacitor electrode line which forms a storage capacitor by being opposed via an insulating film, wherein the semiconductor thin film transistor is a back channel etch type semiconductor thin film transistor according to claim 4. A semiconductor thin film transistor array substrate. 12. A transparent insulating substrate, a plurality of gate wirings juxtaposed on the insulating substrate, a gate insulating film formed on the gate wiring, and the gate via the gate insulating film. A plurality of source wirings intersecting wirings, a semiconductor thin film transistor provided at an intersection of the gate wiring and the source wiring, and a gate wiring which is electrically connected to the semiconductor thin film transistor, is made of a transparent conductive film, and has an insulating film interposed therebetween. 5. A semiconductor thin film transistor array substrate for a matrix type display device, comprising: a pixel electrode which forms a storage capacitor by being opposed to a semiconductor thin film transistor array substrate, wherein the semiconductor thin film transistor is a back channel etch type semiconductor thin film transistor according to claim 4. .